General Instructions

FM27C256 is a 256K electrically programmable read-only memory. It is EPROM fabricated with Fairchild's latest CMOS split gate technology, enabling it to run equally fast with 90 ns access times over the entire operating range. FM27C256 is the most operating system and application software. Its 90 ns access time provides high-speed operation using a high-performance CPU. The FM27C256 provides a microcontroller solution to code storage requirements for 100 % firmware-based devices. Common software programs are quickly executed from EPROM memory, greatly enhancing system utilities. The FM27C256 configures it in the standard EPROM pins as it is currently using the standard EPROM. Block Diagram May 2001 The FM27C256 is a member of the high-density EPROM family with densities ranging up to 4MB.

feature

High performance CMOS - 90, 120, 150 ns access time JEDEC standard pin configuration - 32-pin PLCC package - 28-pin CERDIP package replaces 27C256 or 27256

Package Type: FM27C256 Q, V XXXQ=Quartz Window Ceramic Impregnated V=Surface Mount PLCC All packages are JEDEC compliant. All versions are guaranteed to run at lower speeds

Absolute Maximum Ratings (Note 1) Storage Temperature -65°C to +150°C All Input Voltages Except A9 -0.6V to +7V with respect to Ground -0.6V to +7V with respect to VPP and A9 Ground -0.7V to +14V

VCC supply voltage relative to ground -0.6V to +7V ESD protection>2000V All output voltages relative to ground VCC +1.0V to ground -0.6V

AC test conditions Output load 1 TTL gate and CL=100 pF (Note 8) Input rise and fall time ≤ 5ns Input pulse level 0.45 to 2.4V Timing measurement reference level (Note 10) Input 0.8V and 2.0V Output 0.8V and 2.0 V

Note 1: The stresses listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is only the pressure rating and functional operation of the device under the above or any other conditions stated in the operating section of this specification is not implied. Extended exposure to absolute maximum rating conditions may affect device reliability.

Note 2: This parameter is only sampled, not 100% tested.

Note 3: After CE falling edge, OE can be delayed up to tACC-tOE without affecting tACC.

Note 4: The tDF and tCF comparison levels are determined as follows: as high as tri-state, measure VOH1(DC) -0.10V; as low as tri-state, measure VOL1(DC) +0.10V.

Note 5: Tri-state can be achieved using OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended to use at least a 0.1µF ceramic capacitor between VCC and GND on each device.

Note 7: The output must be limited to VCC+1.0V to avoid latch-up and device damage.

Note 8: TTL gate: IOL=1.6mA, IOH=-400µA. CL=100pF includes clamp capacitance.

Note 9: VPP can be connected to VCC except during programming.

Note 10: Input and output may be less than -2.0V, 20 ns maximum.

Note 11: CMOS input: VIL=GND±0.3V, VIH=VCC±0.3V.

Note 12: Fairchild's standard product warranty applies to devices programmed to the specifications described herein.

Note 13: VCC must be used at the same time or before VPP and removed at the same time or after VPP. Do not insert or remove EPROMs with voltages applied to VPP or VCC.

Note 14: The maximum absolute allowable voltage that can be applied to the VPP pin during programming is 14V. Prevents overshoot exceeding the 14V maximum specification. A minimum of a 0.1µF capacitor is required between VPP, VCC, and GND to suppress stray voltage transients that could damage the device.

Note 15: During the power-on process, the PGM pin must be at a high level (≥VIH), either at the same time as VPP, or before powering on VPP

Function description Device operation: Table 1 lists the six working modes of EPROM. It should be noted that all inputs for the six modes are at TTL levels. The required power supplies are VCC and VPP. The VPP power supply must be 12.75V in the three programming modes and 5V in the other three modes. The VCC supply must be 6.5V in the three programming modes, and 5V in the other three modes. The read mode EPROM has two control functions, both of which must be logically active in order to obtain data on the output. Chip Enable (CE/PGM) is a power control that applies to device selection. Output Enable (OE) is the output control and should be used to transfer data to the output pins, independent of the device selection. Assuming the address is stable, the address access time (tACC) is equal to the delay from CE to output (tCE). Data is at the output toe-in, available after the falling edge of OE, assuming CE/PGM is always low and the address is stable for at least tACC-tOE. Standby Mode The EPROM has a standby mode that reduces active power losses by more than 99%, from 385 MW to 0.55 MW. EPROM by applying a CMOS high signal to the CE/PGM input. When in standby mode, the output is in a high impedance state, independent of the OE input. Output Disable Signal sent to OE input by applying TTL high, EPROM is in output disable state. When the input and output are disabled, all circuits are enabled, but the output is in a high impedance state (tri-stated). Output or Type Because EPROMs are often used in larger memory arrays, Fairchild provides a two-wire control function that accommodates the use of multiple memory connections. 2-wire control

The function allows:

1. The lowest possible memory power consumption, and

2. It is fully guaranteed that output bus contention will not occur. For the most efficient use of these two control lines, it is recommended that CE/PGM be decoded and used as the main device selection function, while OE is connected to all devices in the array and connected to the system control bus. This ensures that all deselected memory devices are in a low-power standby mode, and the pins are only active when data from a particular memory device is required.

Programming Note: Exceeding 14V on pin 1 (VPP) will damage the EPROM. Initially, after each erase, all bits of the EPROM are in the "1" state. Data is introduced into the desired bit position by selectively programming "0"s. Although only "0" will be programmed, both "1" and "0" can be displayed in the data word. The only way to change "0" to "1" is UV Erase. When the VPP is powered on, the EPROM is in programming mode with a supply voltage of 12.75V and a running experience of VIH. A minimum of 0.1µF capacitors are required between VPP, VCC, and ground to suppress stray voltage transients that can damage the device. The data to be programmed is applied in parallel with the data on the 8-bit output pins. The level required for address and data input is TTL. When the address and data are stable, an active low TTL program pulse is applied to the CE/PGM input. A program pulse must be applied to each address location to be programmed. The EPROM is programmed using the turbo programming algorithm as shown. Each address is programmed with a series of 50 microsecond pulses until verified well, up to a maximum of 10 pulses. Most memory cells will be programmed using a single 50 microsecond pulse. (Standard National Semiconductor algorithm can also be used, but it will take longer to program.) EPROM must not be used for CE/PGM input. Programming multiple EPROMs in parallel with the same data is easy to implement because of the simplicity of programming. Similar inputs of parallel EPROMs can be connected when programming them with the same data. The valley is applied to the level TTL pulse parallel EPROM of the CE/PGM input program.

It is also easy to program multiple eproms in parallel with different data. Except for CE/PGM, it may be common for all inputs to be the same for parallel eproms (including OE). A TTL low program pulse applied to the CE/PGM input of the EPROM will program the EPROM when VPP is 12.75V. TTL high level CE/PGM input inhibits programming of other EPROMs. Program Verification should be performed on the programming bit to determine if it was programmed correctly. Verification may be performed with VPP at 12.75V. VPP must be on VCC except during programming and program verification. An opaque label should be attached to the EPROM window after programming to prevent inadvertent erasure. Covering the windows will also prevent temporary malfunctions due to photo-generated ocean currents. Manufacturer Identification Code EPROMs have a manufacturer identification code to aid in programming. When the device is plugged into the EPROM programmer socket, the programmer reads the code and then automatically calls the section. This automatic programming is controlled only by programmers who have the ability to read code. The manufacturer's identification code, as shown in the table, is used exclusively to identify the manufacturer and device type. The code for the FM27C256 is "8F04", where "8F" means it is made by Fairchild, and "04" means 256K parts. The code is accessed by applying 12V±0.5V to address pin A9. Addresses A1-A8, A10-A16 and all control pins are located at VIL. Address pin A0 is reserved in VIL for manufacturer codes and in VIH for device codes. Code is read on 8 data pins, O0–O7. Correct code access is only guaranteed at temperatures from 25°C to ±5°C.

Functional Description (Continued) Erase Characteristics The erase characteristics of the device are such that it begins to occur when exposed to shorter wavelength light greater than about 4000 Angstroms. It should be noted that fluorescent lamps and some types of fluorescent lamps have wavelengths between 3000 and 4000 Ohnes. The recommended erasing procedure for EPROM is exposure to a wavelength of 2537 Å. The combined dose (i.e. UV intensity x exposure time) erasure should be at least 15W sec/cm~2. The EPROM should be placed within 1" of the lamp during the erasing process. Some lamps have a filter on the tube that should be removed before erasing. The erasing system should be calibrated regularly. The distance from the lamp to the unit should be kept at 1 inch. Erase time increases with the square of the distance from the light (if the distance is doubled the erase time increases by a factor of 4). Lights weaken with age. When a lamp is replaced the distance changes or the lamp ages, the system should check to make sure that a full erase is in progress.

Incomplete erasing can lead to potentially misleading symptoms. Programmers, components and even system designs are wrongly suspected when incomplete erasure is the problem. System consideration of the power switching characteristics of EPROMs requires attention to device decoupling. The supply current ICC has three segments of interest to the system designer: the standby current level, the active current level, and the peak transient current generated by voltage transitions on the input pins. The magnitude of these transient current peaks depends on the device output capacitive load. Transient voltage spikes can be suppressed by appropriate selection of the associated VCC decoupling capacitor. Recommended at least 0.1µF at VCC and ground. This should be a high frequency capacitor inductor with a low natural frequency. Also, at least one 4.7µF block electrolytic capacitor should be used between VCC and GND for every eight devices. This bulk capacitor should be located near the power supply connected to the array. The purpose of bulk capacitors is to overcome PC board traces.

Mode Selection Table 1 lists the operating modes of the FM27C256. A 5V power supply is required in read mode. All inputs are TTL level except VPP and A9 for the device.