feature

2.7-V to 5.5-V analog power supply, low power: –10.6 MW ( 500 kHz, +VA=2.7V, +VBD=1.8V); 500 kHz sampling rate; excellent DC performance – ±1.5 typical LSB, ±2 LSB max; -±0.6 LSB typical, ±1 LSB max DNL; –16-bit NMC over temperature; ±0.5 mV max offset error at –2.7 V; ±1 mV; excellent AC performance at fI=10 kHz; 91dB SNR, 100dB SFDR, –96dB THD; built-in conversion clock (CCLK) × (+VA) I/O power supply –SPI/ DSP compatible serial 1.65V to 1.5V; SCLK up to 50 MHz.

Full Power Down Mode: Deep Power Down; Nap Power Off; Auto Shutdown.

Unipolar Input Range: 0 V to VREF.

Software reset; global switching (independent of CS); programmable state/polarity EOC/INT; ×4 QFN or 16-pin TSSOP package 16-pin 4; multi-chip daisy-chain mode; programmable tag bit output; communication auto/manual Channel selection mode.

application

Sensor interfaces; medical devices; magnetometers; industrial process control; data acquisition systems; automatic test equipment.

illustrate

The ADS8327 is a low power, 16-bit, 500 kSPS analog-to-digital converter with unipolar inputs. The device includes a 16-bit capacitance based SAR a/D converter and inherent sample and hold.

Based on the same core, the ADS8328 includes a 2-to-1 input multiplexer with programmable options for tag bit output. Both the ADS8327 and ADS8328 provide a high-speed, wide-voltage serial interface and are capable of chained operation when multiple converters are used.

These converters are available in 16-lead TSSOP or 4x4 QFN packages and are fully specified for operation over the industrial -40°C to +85°C temperature range.

Please note that important notices regarding the availability, standard warranties and use in critical applications and disclaimers of Texas Instruments semiconductor products appear at the end of this data sheet.

theory of operation

The ADS8327/28 is a high speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function.

The ADS8327/28 have an internal clock for running conversions, but can also be programmed to run conversions based on the external serial clock SCLK.

The ADS8327 has one analog input. Analog input is provided on two input pins: +IN and –IN. When a conversion begins, the differential inputs on these pins are sampled on an internal capacitor array. During conversion, both the +in and –in inputs are disconnected from any internal functions.

The ADS8328 has two inputs. Both inputs share the same common pin COM. The negative input is the same as the –IN pin of the ADS8327. The ADS8328 can be programmed for manual channel selection or automatic channel selection mode, which automatically scans between channels 0 and 1.

analog input

When the converter enters holdover mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. The voltage at the input is limited between AGND – 0.2v and AGND + 0.2v, allowing the input to reject the same small signal as the input. The +IN input has a range of -0.2 V to VREF+0.2 V. The input range (+IN- (-IN)) is limited to 0 V to VREF.

The (peak) input current through the analog input depends on many factors: sample rate, input voltage, and source impedance. The current into the ADS8327/28 charges the internal capacitor array during sampling. After the capacitor is fully charged, there is no more input current. The analog input voltage source must be able to charge the input capacitor (45pf) to a stable 16-bit level within the minimum acquisition time (238ns). When the converter enters holdover mode, the input impedance is greater than 1 GΩ.

Attention must be paid to the absolute analog input voltage. To maintain the linearity of the converter, the +IN and –IN inputs and ranges (+IN-(-IN)) should be within the specified range. Outside these ranges, the linearity of the converter may be out of specification. To reduce noise, a low bandwidth input signal should be used with a low pass filter. Care should be taken to ensure that the output impedances of the sources driving the +input and -input are matched. If this is not observed, the two inputs may have different settling times. This can lead to offset errors, gain errors, and linearity errors that vary with temperature and input voltage.

driver amplifier selection

The analog input of the converter needs to be driven with a low noise op amp, such as the THS4031 or OPA365 . It is recommended to install RC filters at the input pins to low pass the source noise. Two 20Ω resistors and a 470 pF capacitor are recommended. The input to the converter is a unipolar input voltage ranging from 0 V to VREF. The minimum -3dB bandwidth to drive an op amp can be calculated as:

When n is equal to 16, the resolution of the ADC (for ADS8327/28). When tACQ = 238ns (minimum capture time), the minimum bandwidth of the drive amplifier is 7.9mhz. If the application increases the acquisition time, the bandwidth can be relaxed. OPA365, OPA827 or THS4031 from Texas Instruments is recommended. The THS4031 used to drive the converter in a source follower configuration is shown in a typical input drive configuration, Figure 52. For the ADS8330, a 0Ω series resistor (or no resistor at all) should be used on the COM input.

Bipolar to Unipolar Driver

In systems where the input is bipolar, the THS4031 can be used with an additional DC bias applied to its + input to keep the input to the ADS8327/28 within its rated operating voltage range. This configuration is also recommended when the ADS8327/28 are used in signal processing applications that require good signal-to-noise ratio and THD performance. The DC bias can be derived from the REF3225 or REF3240 reference voltage ic. The input configuration shown in Figure 53 is capable of delivering better than 91 dB signal-to-noise ratio and -96 dB total harmonic distortion at an input frequency of 10 kHz. If a bandpass filter is used to filter the input, care should be taken to ensure that the signal swing at the input of the bandpass filter is small to minimize the distortion introduced by the filter. In this case, the gain of the circuit shown in Figure 53 can be increased to keep the input to the ADS8327/28 large to keep the signal-to-noise ratio of the system high. Note that in this configuration, the system gain from +input to the output of the THS4031 is a function of the AC signal gain. A resistor divider can be used to scale the output of the REF3225 or REF3240 to step down the voltage at the DC input to the THS4031 to keep the voltage at the converter input within its rated operating range.

refer to

The ADS8327/28 can operate with an external reference from 0.3V to 4.2V. To ensure good converter performance, a clean, low noise, well decoupled reference voltage needs to be available on this pin. A low noise bandgap reference like the REF3240 can be used to drive this pin. A 10µF ceramic decoupling capacitor is required between the REF+ and REF- pins of the converter. These capacitors should be placed as close as possible to the pins of the device. REF- should be connected to the analog ground plane over the shortest possible distance.

Inverter operation

The ADS8327/28 has an oscillator that is used as an internal clock to control the slew rate. The frequency of this clock is a minimum of 10.5 MHz. The oscillator is always on unless the device is in a deep power-down state, or the device is programmed to use SCLK as the conversion clock (CCLK). The minimum acquisition (sampling) time requires 3 CCLKs (equivalent to 238ns at 12.6mhz), and the conversion time requires 18 conversion clocks (CCLK) (about 1500 ns) to complete a conversion.

If desired, conversions can also be programmed to run based on the external serial clock SCLK. This allows system designers to implement system synchronization. The serial clock SCLK is first reduced to 1/2 its frequency before being used as the conversion clock (CCLK). For example, for a SCLK of 21mhz, it provides a clock of 10.5mhz for conversion. If a conversion needs to be started on a specific rising edge of SCLK when the external SCLK is programmed as the source of the conversion clock (CCLK) (and manual start conversion is selected), then the setup time between CONVST and this rising SCLK edge should be observed. This ensures that the conversion is done in 18 CCLKs (or 36 SCLKs). The minimum setup time is 20 ns to ensure synchronization between CONVST and SCLK. In many cases, a transition can start after one SCLK cycle (or CCLK), resulting in 19 CCLK (or 37 SCLK) transitions. Once the synchronization is relaxed, the 20 ns setup time is not required.

The duty cycle of SCLK is not critical as long as it meets the minimum high and low time requirement of 8ns. Since the ADS8327/28 are designed for high-speed applications, a higher serial clock (SCLK) must be provided to maintain high throughput through the serial interface, so the clock period of SCLK must not exceed 1 ms (used as the conversion clock (CCLK) )). The minimum clock frequency is also controlled by parasitic leakage of capacitive digital-to-analog (CDAC) capacitors inside the ADS8327/28.

Manual channel selection mode

The conversion cycle begins with the selection of the acquisition channel by writing the channel number to the Command Register (CMR). This cycle time can be as short as 4 serial clocks (SCLK).

Automatic channel selection mode

Channel selection can also be done automatically if the automatic channel selection mode is enabled. This is the default channel selection mode. The ADS8328 dual-channel converter has a built-in 2-to-1 multiplexer. If the device is programmed for automatic channel selection mode, the signals from channel 0 and channel 1 are acquired in a fixed order. In the next cycle, after configuring CFR_D11 to 1 for the command cycle for automatic channel selection mode, channel 0 is accessed first. This automatic access stops looping after a command loop with CFR_D11 set to '0'.

start conversion

The end of acquisition or sampling instance (EOS) is the same as when the conversion started. This is initiated by turning the CONVST pin low for at least 40 ns. The CONVST pin can be turned up after the minimum requirements are met. CONVST is independent of FS/CS, so a common CONVST can be used in applications that require multiple converters to sample/hold simultaneously. The ADS8327/28 switches from sample mode to hold mode on the falling edge of the CONVST signal. The ADS8327/28 require 18 conversion clock (CCLK) edges to complete the conversion. The conversion time is equivalent to 1500ns, and the internal clock is 12mhz. The minimum time between two consecutive CONVST signals is 21 CCLKs.

If programmed this way (CFR_D9=0), it is also possible to start a conversion without using CONVST. When the converter is configured to auto-trigger, the next conversion automatically starts three conversion clocks (CCLK) after the conversion ends. These three conversion clocks (CCLK) are used as acquisition time. In this case, the time to complete one acquisition and conversion cycle is 21 CCLKs.

(1) The automatic channel selection should be used with the automatic trigger and should also be enabled with the tag bit.

Status output EOC/INT

When the status pin is programmed as EOC and the polarity is set to active low, the pin operates as follows: When programmed as a manual trigger, the EOC output goes low immediately after CONVST goes low. EOC remains low during the entire conversion process and returns high at the end of the conversion. If automatic triggering is programmed, the EOC output of the three conversion clocks (CCLK) goes low after the previous rising edge of EOC.

This status pin is programmable. It can be used as an EOC output (CFR.D[7:6] = 1, 1), where the low time is equal to the conversion time. This status pin can be used as an integer (CFR.D[7:6] = 1, 1, 0), set low at the end of a conversion and high (cleared) on the next read cycle. The polarity of this pin, used for either function (EOC or INT), is programmable through CFR_D7.

Power down mode

The ADS8327/28 have comprehensive built-in power-down capabilities. There are three shutdown modes: deep shutdown mode, Nap shutdown mode and automatic Nap shutdown mode. All three power-down modes are enabled by setting the relevant CFR bits. The first two power-down modes are active when enabled. Wakeup command 1011b may resume device operation from power down mode. Auto-off mode works a little differently. When the converter is enabled in auto-nap shutdown mode, the end-of-conversion instance (EOC) puts the device into an auto-nap shutdown state. The start of sampling will resume converter operation. The contents of the configuration registers are not affected by any power-down modes. Any in-progress transitions will be aborted when a nap or deep power down is initiated.

Deep Power Down Mode

Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are powered down. External SCLK is blocked to the analog block. The analog block no longer has bias current and the internal oscillator is turned off. In this mode, the supply current drops from 5 mA to 6 mA in 100 ns. The wake-up time after a power outage is 1 ms. When Bit D2 in the configuration register is set to 0, the device is in a deep power-down state. Setting this bit to '1' or sending a wake-up command allows the converter to recover from a deep power-down state.

Nap mode

In nap mode, the ADS8327/28 turn off the biasing of the comparator and medium voltage buffer. In this mode, the supply current drops from 5 mA in normal mode to about 0.3 mA within 200 ns after the configuration cycle. Wake-up (recovery) time from nap shutdown mode is 3 CCLKs (238 ns, 12.6 MHz transition clock). Once the CFR_D3 bit in the control register is set to '0', the device will enter nap shutdown mode regardless of the transition state. Setting this bit to '1' or sending a wake-up command allows the converter to recover from a nap shutdown state.

Auto capture mode

Auto capture mode is almost the same as capture mode. The only difference is when the device is actually powered off and the method of waking up the device. Configuration register bit D4 is only used to enable/disable auto-nap mode. If auto-capture mode is enabled, the device turns off the bias after the conversion is complete, which means the end of the conversion will activate auto-capture shutdown mode. In normal mode, the supply current drops from 5mA to around 200mA. CONVST restores the device and turns on the bias again in 3 CCLKs (238ns, 12.6mhz transition clock). The device can also be woken up by disabling auto-nap mode when bit D4 of the configuration register is set to '1'. Any channel select command 0XXXb, wakeup command or set default mode command 1111b can also wake up the device from auto power off of the nap.

Notice

1. This wake-up command is word 1011b in the command word. This command sets bits D2 and D3 in the configuration register to 1, not D4. However, the wake command does remove the device from any of these shutdown states (deep/nap/auto nap power down).

2. Wake-up time is defined as the time between when the host processor attempts to wake up the converter and when the conversion starts.

Total acquisition + conversion cycle time:

Auto: = 21 CCLKs

Manual: ≥ 21 CCLKs

Manual + deep power down: ≥ 4SCLK + 100 ms + 3 CCLK + 18 CCLK +16 SCLK + 1 ms

Manual + power off the nap: ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK

Manual + automatic power off of the nap: ≥ 4 SCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK (using wake-up recovery)

Manual + Auto nap≥1 CCLK + 3 CCLK + 3 CCLK + 18 CCLK + 16 SCLK (recovered with CONVST)

Power outage:

digital interface

The serial clock is designed to accommodate the latest high-speed processors with SCLK frequencies up to 50MHz. Each cycle starts with the falling edge of FS/CS. The internal data register contents available to the EOC output register are displayed on the SDO output pin on the falling edge of FS/CS. This is MSB. Output data is valid on the falling edge of SCLK with td (SCLKF – delay) so that the host processor can read it on the falling edge. The serial data input is also read with the falling edge of SCLK. Stovalled) A complete serial I/O cycle begins and ends on the first falling edge of SCLK following the falling edge of FS/CS and ends 16 (see note) on the falling edge of SCLK. The serial interface is very flexible. It works with CPOL=0, CPHA=1 or CPOL=1, CPHA=0. This means that the falling edge of FS/CS may fall when SCLK is high. The same slack applies to the rising edge of FS/CS, where SCLK may be high or low, as long as the last SCLK falling edge occurs before the rising edge of FS/CS.

Notice

In some cases, one cycle is 4 SCLKs or up to 24 SCLKs, depending on the read mode combination.

internal register

The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for the configuration data register (CFR).

write converter

There are two different types of register writes, a 4-bit write to CMR and a 16-bit full write to CMR plus CFR. The command set is listed in Table 4. A simple command requires only 4 SCLKs, and writes take effect on the 4th falling edge of SCLK. A 16-bit write or read requires at least 16 SCLKs (see Table 7 for exceptions that require more than 16 SCLKs).

Configure Converters and Default Modes

The converter can be configured using command 1110b (write CFR) or command 1111b (default mode). Writing to the CFR requires a 4-bit command followed by 12-bit data. 4-bit commands take effect on the fourth falling edge of SCLK. CFR writes take effect on the 16th falling edge of SCLK.

The default mode command can be achieved by simply binding SDI to +VBD. Once the chip is selected, SCLK will record at least 4 1s. The default value of CFR is loaded into CFR on the fourth falling edge of SCLK.

The CFR defaults are all 1s (except for CFR_D1, which is ignored by the ADS8327 and always reads as 0). The same default values apply to CFR after power-on reset (POR) and switch reset.

read configuration register

The host processor can read the value programmed in the CFR by issuing command 1100b. The timing is similar to reading the conversion result, except that CONVST is not used and there is no activity on the EOC/INT pin. The CFR value read contains the first four MSBs of the converted data plus the valid 12-bit CFR content.

read conversion result

The conversion result is available at the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of CS or FS. The host processor can then shift data out via the SDO pin at any time, except in quiet areas. This is 20 ns before and 20 ns after the end of sampling (EOS). End of sampling (EOS) is defined as the falling edge of CONVST when using a manual trigger, or the end of the third conversion clock (CCLK) after EOC if an automatic trigger is used.

The falling edge of FS/CS should not be placed at the exact moment (at least one conversion clock (CCLK) delay) at the end of the conversion (by default, when EOC goes high), otherwise the data will be corrupted. If FS/CS is placed before the end of the conversion, the previous conversion result is read. If FS/CS is placed after the conversion ends, the current conversion result is read.

The result of the conversion is 16-bit data in straight binary format, as shown in Table 5. Typically 16 SCLKs are required, except when more than 16 SCLKs are required (see Table 7). The data output of the serial output (SDO) is left adjusted MSB first. Trailing bits are first padded with the flag bits (if enabled) plus all zeros. SDO remains low until FS/CS rises again.

SDO is active when FS/CS is low. The rising edge of FS/CS 3 indicates the SDO output.

Notice

When SDO is not in 3-state (when FS/CS is low and SCLK is running), part of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are provided. For example, a manual channel selection command cycle requires 4 SCLKs, so the SDO outputs 4 MSBs of the conversion result. The exception is that SDO outputs all 1s in the loop immediately after any reset (POR or software reset).

If SCLK is used as the conversion clock (CCLK), and continuous SCLK is used, it is not possible to clock all 16 SDO bits during the sample time (6 SCLK) due to quiet zone requirements. In this case, it is best to read the conversion results during the conversion (36 SCLKs or 48 SCLKs in auto-sleep mode).

The ADS8328 includes a feature TAG that can be used as a TAG to indicate which channel is the source of the conversion results. Adds an address bit after reading the LSB from SDO to indicate which channel the result came from if tagging mode is enabled. The address bits for channel 0 are 0 and the address bits for channel 1 are 1. The converter requires more sclk than the 16 required for a 4-bit command, plus 12 CFR or 16 data bits (because of the additional flag bits).

chain

The ADS8327/28 can operate as a single converter or in a system with multiple converters. When using multiple converters, system designers can take advantage of a simple high-speed SPI-compatible serial interface and connect them in series in a chain. A bit in the CFR is used to reconfigure the EOC/INT status pin as the secondary serial data input, the chain data input (CDI), for the conversion result of the upstream converter. This is a chained operation. A typical connection for three converters is shown in Figure 59.

When using multiple converters in chained mode, the first converter is configured in regular mode and the remaining converters downstream are configured in chained mode. When the converter is configured in chained mode, CDI input data goes directly into the output registers, so serial input data passes through the converter with a 16 SCLK (if tagging is disabled) or 24 SCLK delay, as long as CS is active. See Figure 60 for specific times. During this timing, the conversions in each converter are performed simultaneously.

When the converter is operating in chained mode, care must be taken to handle multiple CS signals. During the entire data transfer, the different chip select signals must be low (48 bits for the three converters in this example). The first 16-bit word after falling chip select is always the data from the chip that received the chip select signal.

Case 1: If the chip select is not toggled (CS remains low), the next 16 bits are the data from the upstream converter, and so on. As shown in Figure 60. If there is no upstream transformer in the chain, like transformer 1 in the example, the same data from the transformer will be repeated.

Case 2: As shown in Figure 61, if the chip select is toggled during a chain mode data transfer cycle, the same data from the converter is read repeatedly during all three discrete 16-bit cycles. This is not an ideal result.

Figure 62 shows a slightly different scenario where CONVST is not shared by the second converter. Converter 1 and Converter 3 have the same CONVST signal. In this case, converter#2 only passes the previous converted data downstream.

The number of SCLKs required for a serial read cycle depends on the combination of different read modes, flag bits, chain modes, and channel selection methods (ie, automatic channel selection). This is listed in Table 7.

With converters configured in chain mode, SCLK skew and datapath delays between converters can affect the maximum frequency of SCLK. Latency is also affected by supply voltage and load. When the device is configured in chain mode, it may be necessary to reduce the speed of SCLK.

reset

The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR D0. These two mechanisms do not hold up internally. When a reset is issued (software or POR), all register data are set to default values (all 1s) and SDO outputs (during the period after reset) are set to all 1s. The state machine is reset to the powered state.

When the device is powered on, when AVDD reaches 1.5v, the POR sets the device to default mode. When the device is powered down, the POR circuit requires AVDD to remain below 125mv for a duration of at least 350ms to ensure proper discharge of the internal capacitors and to correct the device's behavior when powered up again. If AVDD drops below 400 mV, but remains above 125 mV, the internal POR capacitor will not fully discharge and the device requires a software reset to perform correctly after AVDD is restored (shown in undefined area in Figure 65).

Typical connection

Parts Change Notice #20071101000

The ADS8327 and ADS8328 devices have undergone Silicon Replacement Notice (PCN) number 20071101000 under Texas Instruments Partial Replacement. Details on this part change can be obtained from Texas Instruments' Product Information Center or by contacting your local sales/distribution office. This PCN covers devices with date codes 82xx and above.