feature

1.6GHz differential clock input; 2 programmable dividers; divide by 1 to 32 range; phase selection for coarse delay adjustment; 1.6GHz LVPECL clock output; additional output jitter 225 fs rms; 800mhz/250mhz LVDS/CMOS clock output ;Additive output jitter 300 fs rms/290 fs rms; Latency up to 10 ns; Device configuration 4-level logic pins to save space, 32-lead LFCSP.

application

Low jitter, low phase noise clock distribution; clock high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs high-performance wireless transceivers; high-performance instruments; broadband infrastructure; ATE.

General Instructions

The AD9515 features two output clock distribution ICs whose design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with high phase noise and jitter requirements also benefit.

There are two independent clock outputs. One output is LVPECL, while the other output can be set to LVDS or CMOS level. LVPECL output works at 1.6ghz. The other output operates to 800mhz in LVDS mode and 250mhz in CMOS mode.

Each output has a programmable divider that can be set to divide by a selected set of integers between 1 and 32. The phase of one clock output relative to the other can be set by the divider phase selection function used as a coarse timing adjustment.

The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5ns, 5ns, and 10ns), each with 16 trim steps.

The AD9515 does not require an external controller for operation or setup. The device is programmed using 4 levels of logic through 11 pins (S0 to S10 ). The programming pins are internally biased to ⅓V. The VREF pin provides a level of ⅔V. V (3.3 V) and GND (0 V) provide the other two logic levels.

Ideal for data converter clocking applications where maximum converter performance is achieved by jitter on the encoded signal versus jitter.

The AD9515 uses a 32-lead LFCSP and is powered by a single 3.3V supply. The temperature range is -40°C to +85°C.

the term

Phase Jitter and Phase Noise

An ideal sine wave can be thought of as having a continuous, uniform phase progression, with each cycle from 0 degrees to 360 degrees in time. However, the actual signal shows some degree of variation over time. This phenomenon is called phase jitter. While there are many reasons for phase jitter, one of the main reasons is random noise, which has a Gaussian (normal) distribution in statistics.

This phase jitter causes the sine wave energy to spread out in the frequency domain, resulting in a continuous power spectrum. This power spectrum is usually reported as a series of values, in dBc/Hz, at a given offset of frequency from the sine wave (carrier). This value is the ratio (in dB) of the power contained within the 1hz bandwidth relative to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given.

It also makes sense to integrate the total power contained within a certain interval of offset frequencies (eg, 10 kHz to 10 MHz). This is called the integrated phase noise over the frequency offset interval, and can be easily related to the time jitter due to phase noise within the offset frequency interval.

Phase noise adversely affects the performance of adc, dac, and RF mixers. It reduces the achievable dynamic range of converters and mixers, although they are affected in different ways.

time jitter

Phase noise is a frequency domain phenomenon. In the time domain, time jitter also exhibits the same effect. When observing a sine wave, the time of successive zero crossings changes. For square waves, time jitter is seen as the displacement of an edge relative to its ideal (regular) appearance time. In both cases, the change from ideal time is time jitter. Since these changes are random in nature, the time jitter is specified in units of root mean square seconds (rms) or 1 sigma of a Gaussian distribution.

Time jitter that occurs on the sampling clock of the DAC or ADC reduces the signal-to-noise ratio and dynamic range of the converter. The sampling clock with the lowest possible jitter provides the highest performance for a given converter.

Additional phase noise

It is the amount of phase noise caused by the device or subsystem under test. Phase noise of any external oscillator or clock source has been subtracted. This makes it possible to predict how much a device will contribute to overall system phase noise when used with a variety of oscillators and clock sources, each contributing to the total phase noise. In many cases, the phase noise of one element controls the phase noise of the system.

Additional time jitter

It is the amount of time jitter caused by the device or subsystem under test. Time jitter of any external oscillator or clock source has been subtracted. This makes it possible to predict how much the device will contribute to the overall system time jitter when used with various oscillators and clock sources, each contributing to the overall time jitter. In many cases, the timing jitter of the external oscillator and clock source controls the timing jitter of the system.

Typical performance characteristics

Function description

overall

The AD9515 provides the ability to distribute its input clock on one or both outputs. OUT0 is an LVPECL output. OUT1 can be set to LVDS or CMOS logic levels. Each output has its own divider that can be set to a division ratio chosen from a list of integer values from 1 (bypass) to 32.

OUT1 includes an analog delay block that can be set to add 1.5ns, 5ns, or 10ns of additional delay full-scale, each with 16 steps of fine-tuning.

CLK, CLKB - Differential Clock Input

The CLK and CLKB pins are differential clock input pins. This input has frequencies up to 1600 MHz. When the slew rate is lower than 1v/ns, the jitter performance degrades. The input level should be between about 150 mV of P to no more than 2 V of PP. Any larger result may cause the protection diodes on the input pins to turn on.

The CLK equivalent input circuit is shown in Figure 23. This input is fully differential and self-biased. Signals should be AC coupled using capacitors. If a single-ended input must be used, it can only be adjusted to one side of the differential input by AC coupling. The other side of the input should be bypassed to a quiet AC ground with a capacitor.

Synchronize

boot sync

When the V supply is turned on, a power-on synchronization (POS) is issued to ensure that the outputs start synchronously. Power-up sync will only work if the V supply transitions the region from 2.2 V to 3.1 V within 35 ms. POS can appear within a maximum of 65 ms after V crosses 2.2 V. Only outputs that are not divided by 1 are synchronized.

Synchronize

If the AD9515's setup configuration is changed during operation, the outputs may become out of sync. The output can be resynced at any time. Synchronization occurs when the SYNCB pin is pulled low and released. The clock outputs (except for divide=1) are forced into a fixed state (determined by the divide and phase settings) and remain in a static state until the SYNCB pin returns high. After releasing the SYNCB pin, after four cycles of the clock signal of CLK, all outputs continue to synchronize the clock (except in the case of divide=1).

When an output has divide=1, the output is not affected by SYNCB.

The output of the AD9515 can be synchronized using the SYNCB pin. Synchronization aligns the phase of the clock output based on any phase offset set on the output divider.

Synchronization is initiated by pulling the SYNCB pin low for at least 5 ns. The input clock does not have to be present when the command is issued. Synchronization occurs after four input clock cycles.

Synchronization applies to clock outputs:

(1), not closed;

(2), if the divider is not divided = 1 (the divider is bypassed).

The output of setting the divider to divide=1 (the divider is bypassed) is always synchronized to the input clock and has a propagation delay.

For proper operation, the SYNCB pin must be unplugged. Do not leave the SYNCB pin floating.

R resistor set

The internal bias current of the AD9515 is set by the R resistor. This resistor should be as close as possible to the value given in the Specifications section (R=4.12 kΩ). This is a standard 1% resistor value and should be readily available. The bias current set by this resistor determines the logic levels and operating conditions of the modules inside the AD9515. The performance graphs given in the Specifications section assume this resistor value for R.

VREF

The voltage level provided by the VREF pin is ⅔V. This voltage is one of four logic levels used by the setup pins (S0 to S10). These pins set the operation of the AD9515. The VREF pins provide enough drive capability to drive as many mounting pins as possible on a single part. The VREF pin must not be used for other purposes.

Installer configuration

The specific operation of the AD9515 is set by the logic levels (S10 to S0) applied to the set pins. These pins use four-state logic. The logic levels used are V and GND, plus ⅓V and ⅔V. The ⅓V level is provided by an internal self-bias on each setup pin (S10 to S0). This is the level seen by the setup pin that is not connected (NC). The ⅔V level is provided by the VREF pin. All setup pins that require a ⅔V level must be connected to the VREF pin.

AD9515 operation is determined by the combination of logic levels on the setup pins. The setup configurations for the AD9515 are shown in Table 10 through Table 15. These four logical levels are called 0, ⅓, ⅔ and 1. These numbers represent the fraction of the V voltage that defines the logic level. See Setting Pin Thresholds in Table 6.

The meaning of some setting pins depends on the logic levels set on other pins. For example, the effect of the S9/S10 pin pair depends on the state of S8. S8 selects whether the phase value selected by S9/S10 affects OUT0 or OUT1. Furthermore, if OUT1 is selected to control its phase, the effect is further dependent on the state of S0. If S=0, the delay block of OUT1 is bypassed and the logic level on S9/S10 sets the phase value of the OUT1 divider. However, if S0≠0, the full-scale delay of OUT1 is set by the logic level on S0, and the delay block fine delay (fraction of full-scale) is set by S9/S10.

Also, if a non-zero phase value is selected by S2/S3/S4 (for OUT0) or S5/S6/S7 (for OUT1), that phase will override the phase value selected by S9/S10. This allows a phase delay to be selected on OUT0, while a time delay is selected on OUT1.

S1 selects the logic level of each output. OUT0 is LVPECL. The LVPECL output differential voltage (V) can be selected from two levels: 400 mV or 780 mV. OUT1 can be set to LVDS or CMOS level. outer diameter

OUT0 can be turned off (power off) by setting S2/S3/S4 to 0/1/0. OUT1 can be turned off by setting S5/S6/S7 to 0/1/0.

Do not set S2/S3/S4/S5/S6/S7 to 1/1/1/1/1/1.

Divider Phase Offset

The phase offset of OUT0 and OUT1 can be selected. This allows the relative phase of OUT0 and OUT1 to be set.

After a synchronization operation (see the Synchronization section), the phase offset word for each divider determines the number of input clock (CLK) cycles to wait before initiating the clock output edge. By giving each divider a different phase offset, the output delay can be set in increments of fast clock periods t.

Figure 29 shows four cases, each with the delimiter set to divide=4. By increasing the phase offset from 0 to 3, the output is offset from the original edge by a multiple of t.

E.g:

CLK=491.52MHz;

t=1/491.52=2.0345ns divided by =4: phase offset 0=0ns;

Phase offset 1 = 2.0345 ns;

phase offset 2 = 4.069 ns;

phase offset 3 = 6.104 ns;

The output can also be described as:

Phase offset 0=0'

Phase offset 1=90'

Phase offset 2=180'

Phase offset 3=270'

Setting Phase Offset to Phase=4 will result in the same relative phase as Phase=0° or 360°.

The resolution of the phase offset is set by the fast clock period (t) at CLK. The largest unique phase offset is less than the divide ratio up to a phase offset of 15.

The phase offset can be related to degrees by calculating the phase step size for a specific division ratio:

phase step = 360°/divide by ratio;

Using some of the same examples:

divide = 4;

phase step=360°/4=90°;

The only phase offsets in degrees are phase=0°, 90°, 180°, 270°.

divide by = 9;

phase step=360°/9=40°;

The only phase offsets are 0°, 40°, 80°, 120°, 160°, 200°, 240°, 280°, 320°.

delay block

OUT1 includes an analog delay element that gives a variable time delay (ΔT) in the clock signal passing through this output.

The amount of delay that can be used is determined by the output frequency. The amount of delay is limited to less than half the clock period. For example, with a 10 MHz clock, the delay can stretch to a maximum of 10 nanoseconds. However, for a 100 MHz clock, the maximum delay is less than 5 ns (or half the period).

The AD9515 allows the selection of three full-scale delays, 1.5 ns, 5 ns, and 10 ns, set by the delay full-scale (see Table 10). Each full-scale delay can be scaled by 16 trim values, which are set by the delay word (see Table 14 and Table 15).

Delay blocks add some jitter to the output. This means that the delay function should primarily be used to clock digital chips such as FPGAs, ASICs, DUCs, and DDCs, not to provide sampling clocks for data converters. For longer full scales, the jitter is higher because the delay block uses ramps and trip points to create variable delays. Longer slopes mean more noise has the potential to be introduced.

When the delay block is turned off (bypassed), it also de-energizes.

output

The AD9515 offers three different output level options:

LVPECL, LVDS and CMOS. OUT0/OUT0B provide LVPECL differential outputs. The LVPECL differential voltage swing (V) is selectable as 400 mV or 790 mV.

OUT1/OUT1B can be selected as LVDS differential output or a pair of CMOS single-ended outputs. If CMOS is selected, OUT1 is a non-inverted single-ended output, and OUT1B is an inverted single-ended output.

power supply

The AD9515 requires a V supply of 3.3 V ±5%. The table in the Specifications section gives the expected performance of the AD9515 with supply voltages within this range. In any case, the absolute maximum value ranges from 0.3 V to +3.6 V, relative to GND, over Pin VS.

The layout of power lines and printed circuit board ground planes should follow good engineering practice. The power supply should be bypassed on the PCB with sufficient capacitance (>10µF). The AD9515 should be bypassed with enough capacitors (0.1µF) to keep all supply pins as close to the part as possible. The layout of the AD9515 evaluation board (AD9515/PCB) is a good example.

exposed metal paddle

The exposed metal blade on the AD9515 package is an electrical connection as well as a thermal enhancement. For the device to work properly, the lever must be properly grounded (GND).

The exposed baffle of the AD9515 package must be soldered down. The AD9515 must dissipate heat through its exposed paddles. The PCB is used as a heat sink for the AD9515. PCB accessories must provide a good thermal path to larger thermal areas such as ground planes on the PCB. This requires a grid of vias from the top layer to the ground plane (see Figure 34). The AD9515 evaluation board (AD9515/PCB) provides a good example of how the parts should be connected to the PCB.

power management

In some cases, the AD9515 can be configured to use less power by turning off unused functions.

Power saving options include:

(1) When set to divide=1 (bypass), the divider is powered off.

(2) In the shutdown mode (S0=0), the adjustable delay block on OUT1 is powered off.

(3) Unneeded outputs can be powered off (see Table 12 and Table 13). This also reduces the power of the output divider.

application

The AD9515 output is used for the ADC clock.

application

Any high-speed analog-to-digital converter (ADC) is very sensitive to the quality of the sampling clock provided by the user. The ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Clock integrity requirements vary with analog input frequency and resolution, and are most stringent at higher analog input frequencies of ≥14-bit resolution. The theoretical signal-to-noise ratio of an ADC is limited by the ADC resolution and sampling clock jitter. Considering an ideal ADC of infinite resolution with negligible step size and quantization error, the available SNR can be approximated by the SNR.

where f is the highest analog frequency to be digitized.

tj is the rms jitter on the sampling clock.

Figure 35 shows the required sampling clock jitter as a function of analog frequency and effective number of bits (ENOB).

See Application Notes AN-756 and AN-501 above.

Many high-performance ADCs have differential clock inputs to simplify the task of providing the required low-jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sampling clock. Differential distribution has inherent common-mode rejection, which provides superior clock performance in noisy environments. The AD9515 features LVPECL and LVDS that provide differential clock outputs output, which enables the clocking solution to maximize converter SNR performance. When choosing the best clocking/converter solution, the input requirements of the ADC (differential or single-ended, logic level, termination) should be considered.

LVPECL clock distribution

The low voltage, positive emitter coupled logic (LVPECL) output of the AD9515 provides the lowest jitter clock signal available from the AD9515. LVPECL outputs (since they are open emitter) require a DC terminal to bias the output transistor. The simplified equivalent circuit in Figure 31 shows the LVPECL output stage.

In most applications, standard LVPECL remote termination is recommended, as shown in Figure 36. The resistor network is designed to match the transmission line impedance (50Ω) and switching threshold (V−1.3 V).

LVDS clock distribution

The AD9515 provides a clock output (OUT2) with a choice of CMOS or LVDS levels. Low Voltage Differential Signaling (LVDS) is a differential output option for OUT2. LVDS uses a current mode output stage. The current is 3.5mA, resulting in an output swing of 350mV across a 100Ω resistor. LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications.

The recommended termination circuit for LVDS outputs is shown in Figure 38.

For more information on LVDs, see Application Note AN-586 on .

CMOS clock distribution

The AD9515 provides one output (OUT1) with a choice of CMOS or LVDS levels. When CMOS is selected, this output provides a drive that requires CMOS-level logic at its clock input.

The following general guidelines should be used when using single-ended CMOS clocks.

If possible, peer-to-peer networks should be designed so that a driver has only one receiver on the network. This allows for a simple termination scheme and minimizes ringing due to possible mismatched impedances on the network. Series termination at the power supply is often required to provide transmission line matching and/or reduce current transients at the driver. Resistor values depend on board design and timing requirements (10Ω to 100Ω are typically used). The output of CMOS is also limited by capacitive loading or trace length. Typically, trace lengths less than 3 inches are recommended to maintain signal rise/fall times and signal integrity.

Termination at the far end of the PCB trace is the second option. As shown in Figure 40, the CMOS output current of the AD9515 is not sufficient to provide the full voltage swing of the low-impedance resistive remote termination. The far-end termination network should match the PCB trace impedance and provide the required switch point. In some applications, the reduced signal swing can still meet the receiver input requirements. This is useful when driving long trace lengths on less critical networks.

Due to the limitations of single-ended CMOS clocking, differential outputs should be considered when driving high-speed signals over long tracks. The AD9515 provides LVPECL and LVDS outputs that are more suitable for driving long tracks, where the inherent noise immunity of differential signals provides superior performance for clock translators.

Set pins (S0 to S10)

Setup pins that require a logic level of ⅓V (internal self-bias) should be tied together and bypassed to ground with a capacitor.

Setup pins that require a logic level of ⅔V should be tied together with the VREF pin and bypassed to ground with a capacitor.

Power and Grounding Considerations and Power Supply Rejection

Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the realization and structure of the PCB are as important as the circuit design. Proper RF techniques must be used for equipment selection, placement, and wiring, as well as power bypassing and grounding, to ensure optimal performance.

Phase Noise and Jitter Measurement Setup

where: tj_RMS is the RMS time jitter; SNR is the signal-to-noise ratio; SND is the source noise density in nV/√Hz; BW is the SND filter bandwidth VA is the analog source voltage fA is the analog frequency; the theta term is the quantization error, Thermal error and DNL error.

Dimensions