feature

Direct interface to TI-MICROWIRE compatible COPS series processors; simple interface to all microprocessors, or "standalone" operation; scaled operation or use of 5 VDC voltage reference; no zero or full scale required; 2 with address logic , 4 or 8 channel multiplexer options; shunt regulator allows operation from high voltage supplies; 0V to 5V input range with single 5V supply; remote operation with serial digital data link; TTL/MOS input/output compatible ; 0.3 in. Standard width, 8-pin, 14-pin, or 20-pin PDIP assembly; 20-pin PLCC package (ADC0838-N only); SOIC package.

Main Specifications

Resolution: 8 bits; Unadjusted Total Error: ±1/2 LSB and ±1 LSB; Single Supply: 5 VDC; Low Power: 15 mW; Conversion Time: 32 μs.

illustrate

The ADC0831 series are 8-bit serial A/D converters with serial I/O configurable input multiplexers with up to 8 channels. Serial I/Os are configured to interface with the TI Microwire Serial Data Exchange standard to the COPS family of processors, and can interface with standard shift registers or μPs. 2, 4 or 8 channel multiplexers are software configurable for single-ended or differential inputs and channel assignment. Differential analog voltage inputs allow for increased common mode rejection and analog compensation for zero input voltage values. Additionally, the voltage reference input can be adjusted to allow encoding of any analog voltage range resolution smaller than 8 bits.

typical application

Please note that important notices regarding the availability, standard warranties and use in critical applications and disclaimers of Texas Instruments semiconductor products appear at the end of this data sheet.

Function description

Multiplexer addressing

The design of these converters utilizes a sampled data comparator structure that provides differential analog inputs converted by successive approximation routines.

The actual converted voltage is always the difference between the specified "+" input terminal and "-" input terminal. The polarity of each input terminal of the pair being switched indicates the most positive line expected by the converter. If the assigned "+" input is less than the "-" input, the converter will respond with an all-zero output code.

A unique input multiplexing scheme has been used to provide multiple analog channels with software configurable single-ended, differential, or a new pseudo-differential option that will convert the difference between any analog input voltage and a common terminal . This type of input flexibility is significantly simplified by the analog signal conditioning required in transducer-based data acquisition systems. One converter package can now handle ground-referenced and true differential inputs as well as signals with arbitrary reference voltages.

A specific input configuration is assigned during the MUX addressing sequence before starting a conversion. The MUX address selects which analog input to enable, and whether that input is single-ended or differential. In the differential case, it also specifies the polarity of the channel. Differential inputs are limited to adjacent channel pairs. For example, channel 0 and channel 1 may be selected as different pairs, but channel 0 or channel 1 cannot behave differently from any other channel. In addition to selecting the differential mode, the symbol can also be selected. Channel 0 can be selected as a positive input, channel 1 can be selected as a negative input, and vice versa. This programmability is best illustrated by the MUX addressing codes for the various product options shown in the table below.

The MUX address is transferred into the converter via the DI line. Since the ADC0831-N contains only one differential input channel with fixed polarity assignment, addressing is not required.

The common input line on the ADC0838-N can be used as a pseudo differential input. In this mode, the voltage on this pin is treated as a "-" input for any other input channel. This voltage does not have to be analog ground; it can be any reference voltage common to all inputs. This feature is most useful in single-supply applications, where analog circuits may be biased to a potential other than ground and the output signal is referred to as that potential.

Since the input configuration is software controlled, it can be modified on each conversion as needed. One channel can be treated as a single-ended ground-referenced input for one conversion; it can then be reconfigured to be part of another converted differential channel. Figure 22 illustrates the input flexibility that can be achieved.

The analog input voltage per channel can go from 50 mV below ground to 50 mV above VCC (typically 5 volts) without loss of conversion accuracy.

digital interface

One of the most important features of these converters is their serial data link to the control processor. Using the serial communication format provides two very important system improvements; it allows more functionality to be included in the converter package without increasing the package size, and it eliminates low Transmission of high-level analog signals; transmission of high-noise-immune digital data back to the host processor.

To understand the operation of these converters, it is best to refer to the timing and functional block diagrams and follow the complete conversion sequence. For clarity, there is a separate diagram for each device.

1. First, pull the CS (chip select) line low to start the conversion. This line must remain low throughout the conversion process. The converter is now waiting for the start bit and its MUX assignment word.

2. The processor then generates the clock (if not continuously provided) and outputs it to the A/D clock input.

3. On each rising edge of the clock, the state of the data in the (DI) row is clocked into the MUX address shift register. The start bit is the first logical "1" that occurs on this line (all leading zeros are ignored). After the start bit, the converter expects the next 2 to 4 bits to be the MUX assignment word.

4. When the starting position is shifted to the starting position of the MUX register, the input channel is allocated and the conversion is about to start. An interval of one and a half clock cycles is automatically inserted (in the absence of anything happening) to allow the selected MUX channel to stabilize. At this point, the SAR status line goes high, indicating that a conversion is in progress, and the DI line is disabled (no longer accepting data).

5. The data out (DO) line is now out of tri-state and provides leading zeros for this one clock cycle of the MUX.

6. When a conversion begins, the output of the SAR comparator is displayed at the DO line on each falling edge of the clock, indicating whether the analog input is greater (high) or less (low) than each successive voltage from the internal resistor ladder. This data is the result of the conversion being shifted out (MSB first) and can be read immediately by the processor.

7. After 8 clock cycles, the conversion is complete. The SAR status line returns low for this later half clock cycle.

8. If the programmer prefers, the data can be provided in LSB first format [this utilizes the shift enable (Eth) control line]. All 8 bits of the result are stored in the output shift register. Excluding SE control lines, data LSB first, automatically shifted out of DO lines after MSB first data flow. The DO line then goes low and remains low until CS returns high. On the ADC0838-N, the SE line is pulled out, and if held high, the LSB value remains valid on the DO line. When SE is forcibly lowered, data is clocked by LSB first. The ADC0831-N is an exception because its data is output only in MSB first format.

9. When the CS line is high, all internal registers are cleared. If another transition is required, CS must do a high-to-low transition followed by the address information.

The DI and DO lines can be tied together and controlled via a bidirectional processor I/O bit of one line. This is possible because the DI input is only "observed" during the MUX addressing interval, while the DO line is still in a high impedance state.

reference factor

The voltage applied to the reference input of these converters defines the voltage range (the difference between VIN(MAX) and VIN(MIN)) of the analog input to which the 256 possible output codes apply. This device can be used in both ratiometric measurement applications as well as systems requiring absolute accuracy. The reference pin must be connected to a voltage source capable of driving the reference input resistance, typically 3.5 kΩ. This pin is the top of the resistor divider string used for successive approximation conversions.

In a ratiometric measurement system, the analog input voltage is proportional to the a/D reference voltage. This voltage is usually the system power supply, so the VREF pin can be tied to VCC (done inside the ADC0832N). This technique relaxes the stability requirements of the system reference when the analog input and A/D reference move simultaneously, maintaining the same output code for a given input condition.

For absolute accuracy, the reference pin can be biased with a time and temperature stable voltage source when the analog input varies between very specific voltage limits. The LM385 and LM336 reference diodes are good low current devices to use with these converters.

The maximum reference value is limited to the VCC supply voltage. However, the minimum value can be very small (see Typical Performance Characteristics) to allow direct conversion of the sensor output, providing an output span of less than 5V. Due to the increased sensitivity of the converter (1lsb is equal to VREF/256), special attention must be paid to noise pickup, circuit layout, and system error voltage sources when operating with a reduced span.

analog input

The most important feature of these converters is that they can be located at an analog signal source and communicate with a control processor with a high noise immunity serial bit stream over a few wires. This in itself greatly reduces the circuitry to maintain the accuracy of analog signals that are otherwise most susceptible to noise pickup. However, for analog inputs, if the input is noisy at the beginning, or possibly on a large common-mode voltage, there are several words in sequence.

The differential inputs of these converters actually reduce the effects of common-mode input noise, which is a signal that is common to both the selected "+" and "-" inputs for one converter (60 Hertz is the most typical). The time interval between sampling the "+" input and the "-" input is 1/2 the clock period. During this short time interval, changes in the common-mode voltage can cause conversion errors. For a sinusoidal common-mode signal, this error is:

Where: fCM is the frequency of the common mode signal; VPEAK is its peak voltage value; fCLK is the A/D clock frequency (1).

For a 60 Hz common mode signal to produce an LLSB error (5 mV), the converter is operating at 250 kHz and it must peak at 663V, which would be more than allowed because it exceeds the maximum analog input limit.

Due to the sampling nature of the analog input, during the actual conversion, short spikes of current enter the "+" input and exit the "-" input. When the internal comparator is triggered at the end of the clock cycle, these currents decay rapidly without causing errors. A bypass capacitor at the input will average these currents and allow effective DC current to flow through the output resistance of the analog source. Bypass capacitors should not be used if the supply resistance is greater than 1 kΩ.

This source resistance limitation is also important for the DC leakage current of the input multiplexer. Worst-case leakage current ±1µA over temperature will result in a 1mV input error with a 1kΩ source resistance. If a high-impedance signal source is required, an op amp RC active low-pass filter can provide impedance buffering and noise filtering.

optional adjustment

zero error

The zero point of the A/D does not need to be adjusted. Zero offset is possible if the minimum analog input voltage value VIN(MIN) is not grounded. By biasing any VIN (negative) input at that VIN (min) value, the converter can output a 0000 0000 numeric code for this min input voltage. This takes advantage of the differential mode operation of the A/D.

The zero error of the A/D converter is related to the position of the first riser of the transfer function and can be measured by grounding the VIN (-) input and applying a small positive voltage to the VIN (VIN) input. Zero error is the difference between the actual DC input voltage and the ideal 1/2 LSB value (1/2 LSB = 9.8 mV for VREF=5.000 VDC) required to simply convert the output digital code from 0000 to 0000 0001.

full scale

Full-scale adjustment can be done by applying a differential input voltage (down 1.5 LSB from the desired analog full-scale voltage range) and then adjusting the size of the VREF input (or VCC of the ADC0832) for the digital output codes from 1111110 to 1111111.

Adjustment of any analog input voltage range

If the A/D's analog zero voltage is moved away from ground (for example, to accommodate an ungrounded analog input signal), the new zero reference should first be adjusted properly. Apply a VIN (+) equal to the desired zero reference voltage plus 1/2 LSB (where 1 LSB = analog span / 256 is used to calculate the LSB of the desired analog span) at the selected "+" input voltage, then the zero reference voltage at the corresponding "-" input should be adjusted to obtain a code transition of 00HEX to 01HEX.

A voltage shall be applied to the VIN (-) input [with the appropriate VIN (-) voltage applied], given by:

Where: VMAX=high end of analog input range; VMIN=low end of analog range (offset zero). (All ground references.)

The VREF (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the adjustment process.

power supply

A unique feature of the ADC0838-N and ADC0834-N is the inclusion of a Zener diode connected from the V+ terminal to ground and also through a silicon diode to the VCC terminal (this is the actual converter power supply) as shown in Figure 24 shown.

This zener acts as a shunt voltage regulator to eliminate the need for any additional regulation components. This is ideal if the converter is to be kept away from the system power supply. Figures 25 and 27 illustrate two useful applications of this on-board Zener when external transistors can be provided.

An important use of the interconnect diode between V+ and VCC is shown in Figure 26 and Figure 28. Here, this diode is used as a rectifier to allow the converter's VCC supply to be derived from the clock. The low current requirements of the A/D and the relatively high clock frequencies used (typically in the 10k–400kHz range) allow the use of small value filter capacitors as shown to keep the ripple on the VCC line well below 1/ 4 LSB range. A parallel Zener regulator can also be used in this mode. This requires the clock voltage to swing beyond VZ. A zener current limit is required, either built into the clock generator, or a resistor from the CLK pin to the V+ pin can be used.

(1) The internal Zener diode (6.3 to 8.5V) is grounded from V+ and VCC is grounded. The Zener under V+ can work as a shunt regulator and is connected to VCC through a conventional diode. Since the zener voltage is equal to the breakdown voltage of the A/D, the diode ensures that VCC is below the breakdown voltage when the device is powered from V+. Therefore, functionality of V+ operation is ensured even though the resultant voltage at VCC may exceed the specified absolute maximum value of 6.5V. A resistor is recommended to limit the maximum current to V+. (see Figure 24 in the functional description)

application: