feature

256 Kbit Ferroelectric Random Access Memory (F-RAM) 10064 ; logically organized as 32K x 8 ❐ High Endurance 100 Trillion (1014) Read/Write ❐ 151 Years Data Retention Period (see Data Retention and Endurance Table) ❐NoDelay 8482 ;Writing ❐Advanced high reliability ferroelectric process High integration device can replace multiple parts ❐Serial non-volatile memory ❐Real time clock (RTC) with alarm ❐Low VDD detection driver reset ❐Watchdog window Timer ❐ Early Power Outage Warning/NMI ❐ 16-bit non-volatile event counter ❐ Serial number with write lock for security Centuries in BCD format ❐ Tracks years spanning 2099 ❐ Uses standard 32.768 kHz crystal (6 pF/12.5 pF) ❐ Software calibration ❐ Supports battery backup or capacitor processor companion ❐ Active low for VDD and watchdog Reset output ❐ Programmable low VDD reset threshold ❐ Manual reset filtering and denoising ❐ Programmable watchdog window timer ❐ Non-volatile event counter to track system intrusion or other events ❐ 64-bit programmable serial number with locking Fast Serial Peripheral Interface (SPI) ❐ Frequency up to 16 MHz ❐ RTC, supervisor controlled via SPI interface ) Low power consumption ❐ 1.1 mA active current at 1 MHz ❐ 150 μA standby current Operating voltage: VDD=2.7 V to 3.6 V Industrial temperature: –40°C to +85°C 14-pin Small Outline Integrated Circuit (SOIC) Package meets Restriction of Hazardous Substances (RoHS) Underwriters Laboratories (UL) approved

Functional Overview

The FM33256B device combines F-RAM memory with features typically required in processor-based systems. Key features include non-volatile memory, real-time clock, low VDD reset, watchdog timer, non-volatile event counter, lockable 64-bit serial number area and general availability for power-fail (NMI) interrupts or any other Purpose. FM33256B is a 256kbit non-volatile memory using advanced ferroelectric technology. Ferroelectric random access memory or F-RAM is non-volatile and performs read and write operations like a ram. It provides 151 years of reliable data retention while eliminating the complexity, overhead and reliability issues caused by other non-volatile memories at the system level. The FM33256B is capable of supporting 1014 read/write cycles, or 100 million times more write cycles than EEPROM. Real Time Clock (RTC) in BCD format. It can be permanently powered from an external backup voltage source, battery or capacitor. This timer uses a common external 32.768khz crystal and provides a calibration mode that allows software to adjust the timing accurately. Processor Companion includes commonly required CPU support features. Supervisory functions include a reset output controlled by a low VDD condition or a watchdog-controlled signal timeout. When VDD is below a programmable threshold and remains active for 100 ms (max) when VDD is above the trigger point. Programmable watchdog timer from 60ms to 1.8s. The timer can also be programmed for delayed start, acting as a window timer. The watchdog timer is optional, but if enabled, it will assert if the host is not within the time window. The flag bit indicates the source of the reset. The comparators on the PFI connect the external input pins to the onboard 1.5V reference voltage. This is useful for generating power-fail interrupts (NMI), but can be used for any purpose. This series also includes a programmable 64-bit serial number that can be locked so that it cannot be changed. Additionally, it provides event counters that track the number of rising or falling edges detected on dedicated input pins. The counter can be programmed to be non-volatile under VDD power or use only VBAK to back the battery. If VBAK is connected to a battery or capacitor then even without a video display.

Overview

The FM33256B device combines serial non-volatile RAM with a real-time clock (RTC) and a processor partner. The Companion is a highly integrated peripheral that includes a processor manager, analog comparators, non-volatile counters, and serial numbers. The FM33256B integrates complementary but distinct functions under these common interfaces in one package. The product organizes devices in two logical groups. The first is memory and the second is companion including all remaining functions. From a system perspective they appear to be opcodes on the serial bus of two separate devices. The memory is organized as a self-contained non-volatile SPI memory using standard opcodes. The real-time clock and manager functions are accessed under their own opcodes. This clock and monitor function consists of 30 special function registers. The RTC alarm and some control registers are maintained by a power supply on the VBAK pin, allowing them to be powered from a battery or backup capacitor when VDD is below a set threshold. Each functional block is described below. Memory structure FM33256B provides 256kbit memory. The device uses two-byte addressing for the memory portion of the chip. This makes the device software its own independent memory copy, like the FM25W256. The memory array is logically organized as 32768 x 8 bits and uses an industry standard Serial Peripheral Access Interface (SPI) bus. The memory uses F-RAM technology. Therefore, it can be thought of as RAM, and at the speed of the SPI bus, there is no delay in write operations. It also provides effective unlimited write endurance non-volatile memory technology. Describes the SPI protocol that memory arrays can be write protected by software.

Two bits (BP1, BP0) control the protection settings in the status register. Depending on the settings, protected addresses cannot be written. Status Registers and Write Protection In Processor Companion In addition to non-volatile RAM, the FM33256B includes a real-time clock companion with an alarm clock and a highly integrated processor. The accompaniment includes a low VDD reset, a programmable watchdog timer, 16-bit nonvolatile event counter, comparators for early power failure detection or other uses and a 64-bit serial number. Processing Supervisor The supervisor provides two basic functions of the host processor: power failure detection and a watchdog timer to evade software lockout conditions. The FM33256B has a reset pin (RST) to drive the processor reset input fault during power up, power up and software lockout. It is an open drain output with a weak internal pull up to VDD. This allows others to reset the power line or connect to the first pin. When VDD is higher than the programming trigger point, the RST output is weakly pulled to VDD. If VDD falls below the reset trip point voltage level (VTP), the RST pin will be depressed. It will remain low until VDD drops too low for VRST level circuit operation. When VDD rises above VTP again, RST continues to drive low for at least 30 ms (tRPU) to ensure a reliable system reset at a reliable VDD level. When tRPU is satisfied, the first pin will return to the weakly advanced state. When RST is asserted, serial bus activity is locked out even if a transaction occurs while VDD falls below VTP. A memory operation that starts when VDD is higher than VTP is done internally. Table 1 below shows how bits VTP (1:0) control a low VDD reset. They are in bits 1 and 0 of register 18h. When VDD is below the selected VTP, the reset pin will be driven low and the SPI interface and F-RAM array will be locked out. Figure illustrates the response to low video displays.

The watchdog timer can also be used to drive the active reset signal. The watchdog is a free-running programmable timer. This time-out is software programmable from 60 ms to 1.8 seconds in 60 ms increments by a 5-bit non-volatile setting (register 0Ch).

The watchdog also includes a window timer function to allow delayed start. The start time and end time define the windows and each window can be set individually. The start time has a resolution of 25ms and a range of 0ms to 775ms.

The watchdog end time value is located in register 0Ch, bits 4:0, and the watchdog enable is bit 7. The watchdog writes pattern 1010b to the lower nibble of register 0Ah. Writing the correct mode will also cause the timer to load with new timeout values. Writing other modes to this address will not affect its operation. Note that the watchdog timer is free running. When enabling it earlier, the user should restart the timer as described above. This ensures that when possible. When VDD falls below VTP, the monitor is disabled. Note that setting the EndTime timeout setting to all zeros (00000b) disables the timer to save power. The following list summarizes watchdog bites

The program start time value is the guaranteed maximum value. While the EndTime value is the guaranteed minimum time, both vary with temperature and VDD voltage. The watchdog has two additional controls associated with its operation. The nonvolatile enable bit WDE allows RST to time out without the watchdog being restarted. If a reset occurs, the timer will restart on the rising edge of the reset pulse. If WDE is not enabled, the watchdog timer is still running, but has no effect on RST. The second control is to restart the timer, thus preventing a reset. The timer should be changing the timeout value. This procedure must be followed to properly load the watchdog register:

The restart command in step 3 must be issued before tDOG2, which is programmed in step 2. The window timer starts counting when a restart command is issued. Manual reset RST is a bidirectional signal that allows the FM33256B to perform a filtered manual reset switch. The RST input detects an external low state and responds by driving the RST signal low for 100 ms (max). This effectively filters and eliminates the reset switch. After this timeout (tRPU), the user can continue to pull down the first pin, but the SPI commands will not be locked out.

Note that the internal weak pull-up eliminates external components. Reset Flag In a reset condition, a flag bit will be set to indicate the source of the reset. A low VDD reset is indicated by the POR flag, register 09h, bit 5. There are two watchdog reset flags - one for early fault (EWDF) and late fault (LWDF) in register 09h bits 7 and 6. A manual reset will result in no flag being set, so no flag is a manual reset. Note that bits are set in response to a reset source, but they must be cleared by the user. The registers can be read and both sources indicate whether they are cleared by the user. Power Fail Comparator The analog comparator compares the PFI input pin to the onboard pin 1.5 volt reference. When the PFI input voltage falls below this threshold, the comparator will drive the PFO pin to a low state. The comparator has 100 mV of hysteresis (rising voltage only) to reduce noise sensitivity. The most common application comparators will create an early warning power failure interrupt (NMI). This can be done by connecting the PFI pin to the upstream supply through a resistor divider. The application circuit is shown below. Comparators are general purpose devices and their applications are not limited to NMI functionality.

If the power-fail comparator is not used, the PFI pin should be tied to VDD or VSS. Note that the PFO output will be driven to VDD or VSS. Event Counter The FM33256B provides the user with a non-volatile 16-bit event counter. The input pin CNT has a programmable edge detector. CCTV pins clock the counter. The counters are located in registers 0E-0Fh. The counter will increment its count value when the programmed edge polarity occurs. The register value is read by setting the RC bit (register 0Dh, bit 3) to '1'. This requires a snapshot of the counter bytes that allows stable values, even if the count occurs during the read. A register value can be written by first setting the WC bit (register 0Dh, bit 2) to '1'. The user can then clear or preset the counter by writing to registers 0E-0Fh. When the WC bit is set, counting is blocked, so the user must clear the bit to allow counting. The reverse polarity control bit is CP (Register 0Dh, Bit 0). when? When CP is "0", the counter is incremented on the falling edge of CNT, and when CP is set to "1", the counter is at Lt. The polarity bit CP is non-volatile.

When the counter reaches its limit, it does not return to zero for a total of 65535 (FFFFh). Care must be taken before rolling over and subsequent counter resets must be performed to continue counting. There is also a control bit that allows the user to define a counter as non-volatile or battery-backed. The counter is battery backup when the NVC bit (register 0Dh, bit 7) is logic 1 and when the NVC bit is logic 0. Setting the counter battery power mode allows counter operation under VBAK (as well as VDD) power supply. The minimum operating voltage for battery powered mode is 2.0 V. When set to "Non-Volatile" mode, the counter is only applying VDD and above the VTP voltage. The event counter can be programmed to detect tampering events, such as the opening of the system's enclosure or access door. A normally closed switch is connected to the CNT pin and another pin that contacts the chassis, usually ground. The typical solution uses a pull-up resistor on the CNT pin and will keep the battery current flowing continuously. The FM33256B chip allows the user to invoke polled mode, sampling the pins occasionally to minimize battery consumption. It internally tries to pull up the CNT pin and if the open circuit is pulled to the VIH level, it trips the edge detector and increments the event counter value. Setting the polling bit (register 0Dh, bit 1) puts the CNT pin into mode. This mode allows the event counter to detect rising edge tamper events, but the user is limited to battery powered mode (NVC='0') and using rising edge detection (CP='1'). The CNT pin is polled every 125 ms with an additional average IBAK current of less than 20 nA. The voting timer circuit runs from the RTC, so the oscillator must make it work.

In polling mode, the internal pull-up circuit can provide limited liquidity. The maximum capacitance (switch) allowed open circuit on the CNT pin is 100 pF. The serial number provides the memory location for writing the 64-bit serial number. It is a writable block of non-volatile memory that can be accessed by the user once the serial number is set. The 8-byte data and lock bits are passed through the RTC and processor supporting registers. So the serial number area is separate, unlike a memory array. The serial number registers can be written to indefinitely, so these locations are general purpose memory. However once the lock bit is set, the value cannot be changed, and the lock cannot be removed. Once locked, the serial number register can still be read by the system. The serial number is located in registers 10h to 17h. The lock bit is SNL (register 18h, bit 7). Setting the SNL bit to '1' disables writing to the serial number register, and the SNL bit cannot be illuminated.

Trickle Charger To facilitate capacitor backup, the VBAK pin can optionally provide a trickle charge current. When the VBC bit (register 18h, bit 3) is set to '1', the VBAK pin will source approximately 80µA. until VBAK reaches VDD. Capacitors are charged to VDD without external diode and resistor chargers. There is also one by the FC bit (register 18h, bit 2). In this mode, the trickle charger current is set to about 1 mA, allowing larger backup capacitors to charge faster. When not using the backup power supply, the VBAK pin should be tied to VSS and the VBC bit should be cleared. Note: Systems using Lithium batteries should clear the VBC bit to '0' to prevent battery charging. The VBAK circuit includes an internal 1 KΩ series resistor as a safety element. The trickle charger is UL certified. Calibration When the calibration bit in register 00h is set to '1', the clock enters calibration mode. The FM33256B digitally calibrates the crystal oscillator frequency. The digital calibration scheme applies digital corrections based on the calibration settings, CAL and CAL (4:0). In calibration mode (CAL='1'), the ACS pin drives a square wave at 512 Hz (nominal) and the alarm is temporarily unavailable. Any measurement deviation from 512 Hz translates to timing errors. The user measures the frequency and writes the appropriate correction value to the calibration register. This table lists the correction codes. For convenience, the table also shows frequency error (ppm). Positive ppm errors require a negative adjustment to eliminate pulses.

Negative ppm errors require a positive correction pulse. A positive ppm adjustment sets the CALS (sign) bit to "1", while a negative ppm adjustment has a CAL value of "0". When calibrated afterwards, the clock has a maximum error of ±2.17 ppm or ±0.09 minutes per month at the calibration temperature. The user will not be able to see the effect of the calibration settings on the 512 Hz output. Addition and subtraction of digital pulses occurs after the 512 Hz output. Calibration settings are stored in F-RAM, so there is no loss of backup source failure. It is in register 01h with bits CAL (4:0). when the calibration bit is set to a '1'. To exit calibration mode, the user must clear CAL. Logic "0" bit. When the calibration bit is "0", the ACS pin will resume the function according to Table 2. Crystal type crystal oscillators are designed to use a 6 pF/12.5 pF crystal and require no external components such as loading capacitors. The FM33256B device has built-in loading capacitors optimized for 6 pF crystals, but works well for 12.5 pF crystals. For any crystal, no additional external load capacitors are not required nor recommended. If a 32.768 kHz crystal is not used, an external oscillator can be connected to the FM33256B. Layout Recommendations X1 and X2 transistor pins use high impedance circuits. The oscillator connected to these pins may be disrupted by noise or additional loading. To reduce RTC clock error switching noise from the signal, a guard ring pad and guard ring ground should be placed around it. The high-speed SPI trace should be brought out on the X1/X2 pads. The X1 and X2 track lengths should be less than 5 mm. The best ground plane to use is the backside or inner board layer. See layout example. Red is the top layer and green is the bottom layer.