feature

Ultra-low noise preamplifier; voltage noise = 0.74 nV/√Hz; current noise = 2.5pa/√Hz; 3dB bandwidth: 120MHz; low power: 125mW/channel; wide gain range with programmable postamp; –4.5dB to +43.5dB; +7.5dB to +55.5dB; low output-referred noise: 48 nV/√Hz typical; active input impedance matching; optimized for 10/12-bit ADCs; selectable output clamp levels; single 5 V power supply operation; provides space-saving chip-scale packaging.

application

Ultrasonic and sonar time gain control; high-performance AGC system; I/Q signal processing; high-speed dual analog-to-digital converter driver.

General Instructions

The AD8331 /AD8332 are single and dual ultralow noise, linear, decibel, variable gain amplifiers. Although optimized for ultrasonic systems, they can be used as gain elements for low noise variable frequencies up to 120 MHz. Each channel consists of an ultra-low noise preamplifier (LNA), X-AMP; VGA, with a gain range of 48dB and a gain-selectable post-amplifier with adjustable output limit. LNA gain is 19dB, single-ended input and differential output capability accurately programmable active input impedance matching select external feedback resistors. Active impedance control to optimize the noise performance of the application benefits from input matching.

The 48dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained over the entire range. The gain control interface provides an accurate linear decibel control voltage of 50 dB/V between 40 mV and 1 V. Factory trimming ensures excellent performance part-to-part and channel-to-channel gain matching. Differentiated signal paths result in excellent second- and third-order distortion performance and low crosstalk.

The low output-referred noise of the VGA is beneficial for driving high-speed differential ADCs. The gain of the post amplifier is pin selectable to 3.5dB or 15.5dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. This output can be limited to a user-selected clamp level, preventing the input of subsequent ADCs from being overloaded. External resistors adjust the clamping level. The operating temperature range is -40°C to +85°. The AD8331 is available in a 20-lead QSOP package, and the AD8332 in 28-lead TSSOP and 32-lead LFCSP packages. them

A 5V power supply is required and the static power consumption is 125 mW/ch. A power down (enable) pin is provided.

theory of operation

Overview

The following discussion applies to all part numbers. Figure 56 and Figure 1 are functional block diagrams of the AD8331 and AD8332, respectively.

Each channel contains an LNA that provides user-adjustable input impedance termination, a differential X-AMP VGA, and a programmable gain post-amplifier with adjustable output voltage limit. Figure 57 shows a simplified block diagram.

The linear in-dB gain control interface is trimmed for slope and absolute accuracy. The total gain range is 48dB, extending from -4.5dB to +43.5dB or from +7.5dB to +55.5dB, depending on the setting of the HILO pin. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V, resulting in the following gain expression:

The gain characteristics are shown in Figure 58.

When mode is set to high (if available):

The LNA converts the single-ended input to a differential output with a voltage gain of 19 dB. When only one output is used, the gain is 13db. The inverter output is used for active input impedance termination. Each LNA output is capacitively coupled to the VGA input. The VGA consists of a 48dB range attenuator and a 21dB gain amplifier for a net gain range of -27dB to +21dB. X-AMP gain interpolation technology has the advantages of small gain error, uniform bandwidth, and small differential signal path distortion.

The final stage is a logic programmable amplifier with a gain of 3.5db or 15.5db. The LO and HI gain modes are optimized for 12-bit and 10-bit A/D converter applications based on output-referred noise and absolute gain range. The output voltage limit is user programmable.

Low Noise Amplifier (LNA)

Good noise performance relies on a proprietary ultra-low noise preamplifier at the beginning of the signal chain, which minimizes noise contribution in the following VGAs. Active impedance control optimizes the application of noise performance for input matching.

Figure 59 shows a simplified schematic of the LNA. INH is capacitively coupled to the source. The on-chip bias generator concentrates the output DC level at 2.5v and the input voltage at 3.25v. A capacitor C of the same value as the input coupling capacitor C is connected to ground from the LMD pin.

The LNA supports differential output voltages up to 5 VP p with a positive and negative offset of approximately ±1.25 V and a common-mode voltage of 2.5 V. Since the differential gain magnitude is 9, the maximum input signal before saturation is ±275 mV or 550 mV p·P. Overload protection ensures fast recovery time for large input voltages. Very large inputs can be handled without interacting with ESD protection because the inputs are capacitively coupled to the bias voltage close to the mid-supply.

Low value feedback resistors and the current drive capability of the output stage allow the LNA to achieve low input voltage noise of 0.74nv/√Hz. This is achieved with a modest current consumption of 10 mA (50 mW) per channel. The precise gain of on-chip resistor matching is 4.5 (9 differential) per side, which is critical for precise impedance control. The use of fully differential topology and negative feedback minimizes distortion. Low HD2 is especially important in second harmonic ultrasound imaging applications. Differential signaling achieves less swing at each output, further reducing third-order distortion.

The LNA supports active impedance matching from pin LON to pin INH through an external shunt feedback resistor. The input resistance, R, is given by Equation 5, where A is the single-ended gain of 4.5 and 6kΩ is the unterminated input impedance.

C needs to be in series with R because the DC levels of pins LON and INH are not equal. The expressions for selecting R with R and selecting R with C can be found in the "Applications" section. C and ferrite beads improve high frequency stability when loop gain drops and prevent peaking. The frequency response plots of the LNA are shown in Figure 19 and Figure 20. For matched input impedances of 50 to 200 μm, the bandwidth is about 130 MHz, dropping at higher source impedances. The terminal bandwidth (r=0) is about 80 MHz.

In addition to the VGA's 100Ω input impedance (200Ω differential), each output can drive external loads as low as 100Ω. Capacitive loads up to 10 pF are allowed. All loads should be AC coupled. Typically, the PIN ROP output is used as a single-ended driver for auxiliary circuits, such as the driver for Doppler-mode ultrasound imaging and the PIN Lon driver R. Additionally, in addition to active feedback termination, differential external circuits can be driven from both outputs. In both cases, the important stability considerations discussed in the application section should be carefully observed.

The impedance of each LNA output is 5Ω. The open-circuit gain is reduced by 0.4dB when driving a VGA, and by 0.8dB when a 100Ω load is attached to the output. The differential gain of the LNA is improved by 6db. If the load on both sides is less than 200Ω, it is recommended to use a compensating load on the opposite output.

low noise

Input-referenced voltage noise has a significant limit on system performance. The short-circuit input voltage noise of the LNA is 0.74 nV/Hz Hz or 0.82 nV/Hz Hz (maximum gain), including VGA noise. Open circuit current noise is 2.5pa/√Hz. These measurements, taken without the feedback resistor, provide the basis for calculating the input noise and noise figure performance for the configuration in Figure 60. Figures 61 and 62 are simulations extracted from these results, with a 4.1 dB NF measurement of the input actively matched to a 50Ω source. Unterminated (R=∞) operation has the lowest equivalent input noise and noise figure. Figure 61 shows the noise figure versus source resistance, rising at low R, where the LNA voltage noise is larger than the source noise, and rising again at high R due to current noise. All curves include VGA input reference voltage noise of 2.7nV/√Hz.

The main purpose of input impedance matching is to improve the transient response of the system. When the resistor is terminated, the input noise increases due to the thermal noise of the matching resistor and the contribution of the LNA input voltage noise generator. However, in the case of active impedance matching, the contributions of both are 1/(1+LNA gain) less than that of the resistive termination. Figure 61 shows their relative noise figure (NF) performance. In this diagram, the input impedance is swept across by R to maintain matching at each point. The noise figures for the 50Ω source impedance are 7.1db, 4.1db, and 2.5db for resistive, active, and unterminated configurations, respectively. The noise figures for 200Ω are 4.6dB, 2.0dB, and 1.0dB, respectively. Company S

Figure 62 is a graph of NF versus R for various values of R, which is helpful for design. An NF platform that actively matches the input mitigates source impedance variations. For comparison, a preamp with a gain of 19 dB and a noise spectral density of 1 nV/y Hz, combined with a VGA of 3.75 nV/y Hz, will produce a noise figure degradation of about 1.5 dB (for most input impedances), Significantly worse performance than AD8332.

The equivalent input noise of the LNA is the same for single-ended and differential output applications. In the absence of VGA noise, the LNA noise figure improves to 3.5db at 50Ω, but this does not include noise contributions from other external circuits connected to the LOP. When driving external circuits on separate boards, series output resistors are generally recommended for stabilization purposes (see the Applications section). In low noise applications, ferrite beads are more ideal.

Variable Gain Amplifier

Differential X-AMP VGAs provide precise input attenuation and interpolation. It features low input-referred noise of 2.7nv/√Hz and good gain linearity. A simplified block diagram is shown in Figure 63.

X-AMP VGA

The input to the VGA is a differential R-2R attenuator ladder network with 6dB per stage and a net input impedance of 200Ω differential. The ladder diagram is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. The LNA output is AC coupled to reduce offset and isolate its common mode voltage. The VGA input is biased to VCM via the center-tapped connection of the ladder, which is typically set to 2.5 V and bypassed externally to provide a clean AC ground.

The signal level of the continuous stage in the input attenuator is reduced from 0 dB to -48 dB in 6 dB steps. The input stage of the X-AMP is distributed along a staircase, and a bias interpolator controlled by the gain interface determines the input tap point. At overlapping bias currents, the signals from successive taps are combined to provide a smooth attenuation range from 0dB to -48dB. The circuit technology has good linear in-dB gain law consistency and low distortion, deviates from the ideal value of ± 0.2db or less. The gain slope is monotonic with respect to the control voltage and stable over process, temperature, and power supply.

The X-AMP input is part of a 12 gain feedback amplifier which completes the VGA. Its bandwidth is 150 MHz. The input stage is designed to reduce feedthrough to the output and ensure good frequency response uniformity over the gain setting (see Figures 8 and 9).

Gain control

The position of the VGA attenuator is controlled by a single-ended analog control voltage, V, with an input range of 40 mV to 1.0 V. The gain control is scaled to 50 dB/V (20 mV/dB). V values outside the control range saturate to the minimum or maximum gain value. Both channels of the AD8332 are controlled by a gain interface to maintain matching. The gain can be calculated using Equations 1 and 2.

Gain accuracy is excellent, as both the scaling factor and absolute gain are factory trimmed. The total accuracy relative to the theoretical gain expression is ±1db for variations in temperature, process, supply voltage, interpolator gain ripple, trimming error, and tester limits. For a given set of conditions, the gain error relative to the line of best fit is typically ±0.2db. The gain matching between channels is better than 0.1dB (see Figure 7, which shows the gain error at the center of the control range). When V<0.1 or >0.95, the gain error is slightly larger.

The gain slope can be reversed as shown in Figure 58 (available in most versions). The gain slope is -50dB/V across the gain control range from maximum to minimum gain. This slope is useful in applications such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the mode pin HI.

Gain control response time is less than 750ns, within 10% of the final value of the change from minimum gain to maximum gain.

VGA noise

In a typical application, a VGA compresses a wide dynamic range input signal into the ADC's input range. While the input-referred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be handled at any one particular gain control voltage. This limit is set according to the quantization noise floor of the ADC.

In Figures 21 and 23, the output and input noise (called a function of V) are plotted for shorted input conditions. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. get

The output-referred noise is flat over most of the gain range because it is dominated by the VGA's fixed output-referred noise. 48 nV/√Hz in low gain mode and 178 nV/√Hz in high gain mode. At the high end of the gain control range, the noise of the LNA and source dominates. The input-referred noise reaches its maximum gain control voltage near its maximum value, where the input's contribution to the VGA becomes very small.

At lower gains, input-referred noise, and therefore noise figure, increases with decreasing gain. However, the instantaneous dynamic range of the system is not lost because the input capacity increases with it. The contribution of the ADC noise floor also has the same dependency. The important relationship is the size of the VGA output noise floor relative to the ADC.

These devices are ideal for driving low voltage ADCs due to their low output referred noise levels. The noise floor of the converter drops by 12 dB per 2-bit resolution, and at lower input full-scale voltages and higher sampling rates. ADC quantization noise is discussed in the Applications section.

The previous noise performance discussion applies to differential VGA output signals. While the LNA noise performance is the same in single-ended and differential applications, the VGA performance is different. When used single-ended, the VGA's noise is significantly higher because the contribution of its bias noise is designed to cancel out in the differential signal. Transformers can be used in single-ended applications when low noise is required.

Gain control noise is a problem in very low noise applications. Thermal noise in the gain control interface can adjust the channel gain. The resulting noise is proportional to the output signal level and is usually only noticeable when large signals are present. Its effect is only observable in low gain mode, where the noise floor is significantly lower. The gain interface includes an on-chip noise filter that significantly reduces this effect at frequencies above 5mhz. Care should be taken to minimize noise impact at the gain input. An external RC filter can be used to remove V source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.

Common Mode Bias

An internal bias network is connected to an intermediate supply voltage to establish a common-mode voltage in the VGA and postamp. An external bypass buffer maintains the voltage. The bypass capacitor forms an important AC ground connection because there are many important connections inside the VCM network, including the center tap of the VGA differential input attenuator, the feedback network of the VGA fixed-gain amplifier, and the feedback network of the post-amplifier at both gain settings . For best results, use 1 nF and 0.1 μF capacitors in parallel, with 1 nF closest to pin VCM. Provide separate VCM pins for each channel. For DC coupling to a 3V ADC, adjust the output common-mode voltage to 1.5V by biasing the VCM pin.

post amp

The last stage has a selectable gain of 3.5db or 15.5db, set by logic pin HILO. These correspond to linear gains of 1.5 or 6. A simplified block diagram of the post-amplifier is shown in Figure 64.

A separate feedback attenuator enables two gain settings. They are chosen with appropriately scaled input stages to maintain a constant 3db bandwidth between the two gain modes (~150mhz). The slew rate is 1200 V/µs in high gain mode and 300 V/µs in low gain mode. The feedback networks for the high-gain and low-gain modes are fine-tuned at the factory to adjust the absolute gain of each channel.

noise

The topology of the post-amplifier provides constant input error noise with two gain settings and variable output. Output-referred noise (with gain) increases by 4 in high gain mode. This setting is recommended when driving converters with higher noise floors. The additional gain appropriately increases the output signal level and noise floor. The LO gain mode optimizes the output dynamic range when driving circuits with lower input noise.

Although the ADC's quantization noise floor depends on many factors, the 48 nV/√Hz and 178 nV/√Hz levels are well suited for the average requirements of most 12-bit and 10-bit converters, respectively. Another technique described in the application section can extend the noise floor lower for possible use with 14-bit ADCs.

output clamp

The output is internally limited to a 4.5 V pp differential level when operating from a 2.5 V common-mode voltage. The postamp implements an optional output clamp that is connected to ground from R via a resistor. The table lists recommended resistor values.

The output clamp can be used for ADC input overload protection if desired, or for post-amplifier overload protection when operating at lower common-mode levels such as 1.5 V. The user should be aware that as the output level approaches the clamp level, the distortion products will increase and should adjust the clamp resistor accordingly. Also, see the Applications section.

In LO or HI mode, the clamp level is accurate to about ±5%. Figure 65 illustrates the output characteristics for some R values.

application

LNA – External Components

The LMD pin (connected to the bias circuit) must be bypassed to ground and the signal source capacitively coupled to the INH pin with a 2.2 nF to 0.1 μF capacitor (see Figure 66).

The unterminated input impedance of the LNA is 6 kΩ. The user can synthesize any LNA input resistance between 50Ω and 6 kΩ. R is calculated according to Equation 6 or selected from the table.

When using active input termination, a 0.1 μF capacitor (C) is required to isolate the input and output bias voltages of the LNA.

Parallel input capacitor C reduces gain peaking at higher frequencies where active termination matching is lost due to the high frequency gain attenuation of the LNA. Recommended values are shown in the table; for unterminated applications, reduce the capacitor value by half.

When a long trace at pin INH is unavoidable, or if two LNA outputs drive external circuits, a small ferrite bead (FB) in series with pin INH maintains circuit stability with negligible effect on noise. Magnetic beads shown are 75Ω at 100 MHz (Murata BLM21 or equivalent). Other values may prove useful.

Figure 67 shows the interconnection details of the LNA output. Since the DC levels at the LNA output and VGA input are different, capacitive coupling between the two is required to eliminate the LNA offset. The recommended capacitor value is 0.1µF. The gain loss between the LNA output and the VGA input is 0.4 dB due to the 5Ω output resistance. Additional loads at the LOP and LON outputs will affect the LNA gain.

Both LNA outputs can be used to drive external circuits.

In situations where a single-ended LNA output is required, the LOP should be used. The user should be aware of the stray capacitive loading of the LNA output, especially the LON. The LNA can drive 100Ω in parallel with 10 pF. If the LNA output is routed to a remote PC board, it will withstand up to 100 pF of load capacitance by adding 49.9Ω series resistors or 75Ω/100 MHz ferrite beads.

Gain input

Pin gain is common to both channels of the AD8332. The input impedance is nominally 10 MΩ, and a bypass capacitor of 100 pF to 1 nF is recommended.

Parallel devices can be driven by a common voltage source or a DAC. Decoupling should account for any bandwidth factors of the drive waveform, using total distributed capacitance.

If gain control noise in low gain mode becomes a factor, maintaining ≤15 nV/√Hz noise at the gain pins will ensure satisfactory noise performance. Internal noise at the gain pin is less than 15 nV/√Hz. Gain control noise is negligible in high gain mode.

VCM input

The common mode voltage of pins VCM, VOL and VOH defaults to 2.5 Vdc. For output AC coupled applications, the VCM pin will not be terminated; however, it must still bypass the AC ground close to the internal circuitry. The VGA output can be dc connected to a differential load such as an ADC. Common mode output voltage levels between 1.5v and 3.5v can be achieved at pins VOH and VOL by applying the desired voltage at pin VCM. DC-coupled operation is not recommended when driving the load on a separate PC board.

The voltage on the VCM pin is provided by an internal buffer with an output impedance of 30Ω and a default output current of ±2mA (see Figure 68). If the VCM pin is driven by an external power supply, its output impedance should be less than 30Ω and its current drive capability should be greater than 2mA. If the VCM pins of several devices are connected in parallel, the external buffer should be able to overcome their collective output current. When using common mode voltages other than 2.5v, a voltage limiting resistor R is required to prevent overloading.

Logic inputs ENB, MODE and HILO

All enable pins have a nominal 25kΩ input impedance and can be pulled to 5V (a pull-up resistor is recommended) or driven by any 3V or 5V logic family. The enable pin performs a power-down function, when disabled, the VGA output is near ground. Multiple devices can be driven from a common source. Refer to the Pin Functions table for the circuit functions controlled by the enable pins.

Pin HILO is compatible with 3v or 5v CMOS logic families. It is either grounded or pulled up to 5V depending on the desired gain range and output noise.

Optional output voltage limit

The RCLMP pin provides the user with a way to limit the output voltage swing when used with loads that do not prevent the input from overdriving a specified load. The peak-to-peak limit voltage is adjusted by a resistor to ground, and several voltage levels and corresponding resistor values are listed in the table. When not connected, the default limit level is 4.5 V pp.

Note that the third harmonic distortion will increase as the waveform amplitude approaches clipping. For minimal distortion, the clamp level should be set higher than the converter input range. For the 1v pp linear output range, the recommended clamp level is 1.5vp-p; for the 2vp-p range, the recommended clamp level is 2.7vp-p; for 0.5vp-p operation, the recommended clamp level is 1vp-p. The best solution will be determined experimentally. Figure 69 shows the third harmonic distortion as a function of the limit level of the 2v pp output signal. A wider limit level is required in high gain mode.

Output Filtering and Series Resistor Requirements

To ensure stability at the high end of the gain control range, it is recommended to use a series resistor or ferrite bead for the output when driving large capacitive loads or circuits on other boards. These components can be part of an external noise filter.

100Ω for low gain mode and 100Ω for high gain mode (see Figure 66) and placed near pins VOH and VOL. Low value resistors allow for nearby loads or applications where the gain is less than 40 dB. It is best to choose a lower value empirically.

Anti-aliasing noise filters are often used with ADCs. Filter requirements depend on the application.

When the ADC is on a separate board, most filter components should be placed nearby to suppress noise picked up between boards and to mitigate charge backoff at the ADC input. Any series resistors that exceed output stability requirements should be placed on the ADC board. Figure 70 shows a second-order low-pass filter with a bandwidth of 20 MHz. The capacitors are chosen along with the ADC's 10pf input capacitance.

drive the ADC

The output drivers will accommodate a wide range of ADCs. The noise floor requirement for a VGA depends on many application factors, including bit resolution, sample rate, full-scale voltage, and the bandwidth of the noise/antialiasing filter. The output noise floor and gain range can be adjusted by selecting high or low gain mode.

The relative noise and distortion performance of the two gain modes can be compared in Figure 21 and Figures 27-37. The 48 nV/√Hz noise floor of the LO gain mode is suitable for converters with higher sampling rates or resolutions (eg, 12-bit). Both gain modes can accommodate ADC full-scale voltages up to 4v pp. Since the distortion performance remains favorable for output voltages up to 4vp-p (see Figure 32), the output-referred noise can be further reduced by using a resistive attenuator (or transformer) at the output. The circuit in Figure 71 has an output full-scale range of 2v pp, a gain range of -10.5db to +37.5db, and an output noise floor of 24nv/√Hz, making it suitable for some 14-bit ADC applications.

overload

When the gain is set unexpectedly high, these devices respond gracefully to large signals that overload their input stages and normal signals that overload the VGA. Each stage is designed for clean limited overload waveforms and fast recovery when gain settings or input amplitudes are reduced.

Signals greater than ±275mv at the LNA input are clipped to 5v pp differential before being fed into the VGA. Figure 44 shows the response to a 1v pp input burst. Symmetric overload waveforms are important in applications such as continuous wave Doppler ultrasound, where the spectrum of the LNA output during overload is critical. The input stage is also designed to accommodate signals up to ±2.5V without triggering the slow-set ESD input protection diodes.

Both stages of VGA are prone to overload. Postamp limits are more common, and the result is the clean limit output characteristic shown in Figure 45. Under more extreme conditions, the X-AMP will overload, causing the glitches evident in Figure 46. Recovery is fast in all cases. The graph in Figure 72 summarizes the input signal and gain combinations that result in different types of overload.

The aforementioned clamp interface controls the maximum output swing and its overload response. When there is no R resistor, this level defaults to close to 4.5V pp differential to protect the output centered at 2.5V common mode. When other common mode levels are set through the VCM pin, the value of R should be chosen to ensure normal overload. For 1.5 V or 3.5 V common mode levels, the recommended value is 8.3 kΩ or less (for high gain mode, the recommended value is 7.2 kΩ). This will limit the output swing to slightly above 2 V pp difference.

Optional input overload protection.

Applications that apply high transients to the LNA input can benefit from the use of clamping diodes. A pair of back-to-back Schottky diodes can reduce these transients to manageable levels. Figure 73 illustrates how to connect such a diode protection scheme.

When choosing overload protection, the most important parameters are forward and reverse voltages and t (or τ). The Infineon BAS40 series shown in Figure 73 has a τ of 100 ps at 1 mA and a V of 310 mV. Many variants of these specifications can be found in the Supplier Directory.

Layout, Grounding and Bypassing

Due to their excellent high frequency characteristics, these devices are very sensitive to their PCB environment. Achieving the expected performance requires attention to details that are critical to a good high-speed board design.

A multilayer board with power and ground planes is recommended, and unused areas in the signal layer should be filled with ground. Multiple power and ground pins provide reliable power distribution to the device and must all be connected. Each power supply pin should have multiple high frequency ceramic chip capacitor values to maintain a low impedance ground path over a wide frequency range. Capacitor values should be 0.01µF to 0.1µF in parallel with 100 pF to 1 nF and as close to the pins as possible. Ferrite beads should be used to separate the LNA power pins from the VGA. Along with decoupling capacitors, ferrite beads help eliminate unwanted high frequencies without reducing headroom, as do small value resistors.

Several important LNA areas require special care. The LON and LOP output traces must be as short as possible before connecting to coupling capacitors connected to pins VIN and VIP. The R must also be placed near the long pins. The resistors must be placed as close as possible to the VGA output pins VOL and VOH to mitigate the loading effects of the connection traces. Values are discussed in the section titled Output Filtering and Series Resistor Requirements.

Signal traces must be short and direct to avoid parasitic effects. When there are complementary signals, a symmetrical arrangement should be used to maintain waveform balance. PCB traces should remain adjacent when running differential signals over long distances.

Multiple input matching

Matching of multiple sources of different impedances can be accomplished as shown in the circuit of Figure 75. Relays and low supply voltage analog switches can be used to select between multiple supplies and their associated feedback resistors. An ADG736 dual SPDT switch is shown in this example; however, multiple switches can be used and the user can refer to the analog device selection guide for switches and multiplexers.

Disable LNA

Where accessible, grounding the LNA enable pin will power down the LNA, reducing the current by about half. In this mode, the LNA input and output pins may remain unconnected, but power must be connected to all supply pins for the disable circuit to work. Figure 74 illustrates these connections using the AD8331 as an example.

Measurement Considerations

Typical measurement configuration and correct interface values measured at 50Ω.

Use Figure 53 for short-circuit input noise measurements. The input-referred noise level is determined by dividing the output noise by the numerical gain between points A and B, taking into account the noise floor of the spectrum analyzer. Since the 50Ω load is directly driven, the gain should be measured at each frequency of interest and at low signal levels. The generator was removed for noise measurements.

Ultrasound TGC Application

The AD8332 is ideal for medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications because it provides an echolocation method of reflected ultrasound energy.

Schematic of a dual fully differential system using the AD8332 and AD9238 12-bit high-speed ADCs (conversion speeds up to 65 MSPS). In this example, the VGA output is dc-coupled, using the ADC's reference output and a level shifter to center the common-mode output voltage to match the converter's output voltage. Refer to the converter's data sheet to determine if an external CMV bias is required. AC coupling is recommended if the CMV of the VGA and ADC are significantly different.

Using the circuit shown and a high-speed ADC FIFO evaluation kit connected to a laptop, an FFT can be performed on the AD8332. The onboard clock is 20MHz with minimal low-pass filtering, both channels are driven by a 1MHz filtered sine wave, THD is -75dB, noise floor is -93dB, and HD2 is -83dB.