feature

8Mbit Ferroelectric Nonvolatile Memory

Organised as 512Kx16

Use /UB, /LB is configured as 1Mx8

High Endurance 100 Trillion (1014) Read/Write

NoDelay 8482 ; write

Page Mode Operation to 33MHz

Advanced High Reliability Ferroelectric Process SRAM Compatible

JEDEC 512Kx16 SRAM pins

60 ns access time, 115 ns cycle time

Advanced Features

Low VDD display protects memory from

accidental write

Better than battery-backed SRAM modules

No battery issues

overall reliability

True surface mount solution with no rework steps

Excellent moisture-proof, shock-proof and shock-proof performance

low power operation

2.7V–3.6V power supply

14 mA active current

Industry standard configuration

Industrial temperature -40°C to +85°C

8-pin "green" RoHS FBGA package

illustrate

Non-volatile memory reads and writes like a standard SRAM. To ferroelectric RAM is non-volatile, which means that data is re-entered after being entered. Power has been cleared. IT provides data retention for over 10 years, eliminating reliability issues, functional flaws and the complexity of system design Battery Backup SRAM ("BBSRAM") Fast write times and extremely high write endurance make F-RAM superior to other types of memory. Similar to other random access memory devices in system operation, it can be used as a Drop-in replacement for standard SRAM. Read and read word cycles can be triggered by the chip to simply change addresses. F-RAM memory, due to its unique ferroelectric non-volatile memory process, these characteristics make non-volatile memory ideal for applications requiring frequent or fast writes to Form of an SRAM. Includes a low voltage monitor when VDD is Block accesses to the memory array drop below critical thresholds. Memory is protected against inappropriate accesses and data corruption under such conditions. The FM23MLD16 F-RAM is available in a 48-ball surface mount package. Device specifications are available over the industrial temperature range. Guaranteed from -40°C to +85°C.

notes:

1) H=logic high, L=logic low, V=valid data, X=don't care.

2) For a write cycle, the data input is latched on the rising edge of /CE1 or /WE on the falling edge of CE2, whichever comes first.

3) / The write cycle we control starts with the read cycle and then latches (18:3).

4) During page mode operation, address A (2:0) must remain stable for at least 15 ns.

Overview

The FM23MLD16 is a full word F-RAM memory logically organized as 524288 x 16 and accessed using an industry standard parallel interface. All data written on the part is immediately non-volatile with no delay. The device provides page mode operation to provide facing pages (rows). Access to other pages will be triggered by toggling the chip enable pins or simply by changing the upper layer address A (18:2). Memory manipulation users access 524,288 memory locations, each with 16 data bits through the parallel interface. F-RAM memory is organized into two dies, each with 64K rows. Each row has 4 column positions, allowing access operations in fast page mode. Once the first address has been latched by the falling edge of /CE1 (when CE2 is high) or the rising edge of CE2 (when /CE1 is low), subsequent column locations may be accessible without toggling the chip enable. The precharge operation starts when either chip enable pin is pulled out. A write occurs immediately at the end of the access. The /WE pin operation must be toggled on every write. Write data is stored in the non-volatile immediate memory array, a unique feature written to F-RAM called NoDelayTM.

READ OPERATIONS A read operation begins with the falling edge of /CE1 (when CE2 is high) or the rising edge of CE2 (when /CE1 is low). An access initiated by /CE results in an address to be locked and starts a memory read loop if we're excited. Data is available on the bus after the access time is satisfied. Once the address is locked and the access is complete, a new access to a random location (different row) may begin while both chip enable are still active. The minimum cycle time for this random address is tRC. Note that unlike SRAM, the FM23MLD16's /initialization access time is faster than the address cycle time. When /OE, the FM23MLD16 will drive the data bus with at least one byte enable (/UB, /LB) that is asserted low. When /UB is low, when /LB is low. If the assertion /OE is satisfied after the memory access time, the data bus will use valid data. If /OE is asserted before the memory access is complete, the data bus will not be driven until valid data is available. This feature will minimize the provision of current in the system by eliminating transients caused by invalid data driven onto the bus. When /OE is de-configured high, the data bus will remain in the high Z state.

write operation

Writes occur at the same time as reads in the FM23MLD16. The FM23MLD16 supports both /CE- and /WE-controlled write cycles. In both cases, address A (18:2) is latched on /CE1 (when CE2 is high) or on the rising edge of CE2 (when /CE1 is low). In a/CE control write, the /WE signal is asserted before starting a memory loop. That is, /we is low when the device is activated by the chip. In this case, the device is written to. The FM23MLD16 will not drive the data bus regardless of the state of /OE as long as /WE is low. Deselect when device is enabled via chip. In a/ we control writes, when the device is activated via chip enable. Our signal dropped after a while. Therefore, the STORE cycle starts as a read. If /OE is low, the data bus will be driven, however, once /WE is asserted low, it will be hi-Z. The /CE- and /U-controlled write timing conditions are as shown in the Electrical Specifications section. The write cycle timing in Figure 2, shows the data bus as a hi-Z condition when the chip is written before the specified mount time. Even though this is a medium voltage it looks like it is recommended that all DQ pins meet minimum VIH/VIL operating levels. Write access to the array starts after / we are in the remember cycle. Writing access is at /WE, /CE1 or CE2, whichever comes first. A valid write operation requires the user to meet the access time specification before releasing the asset /WE, /CE1 or CE2. The data setup time means that the data cannot be changed until the end of the write access (/CE1 or CE2 for rising). Unlike other true non-volatile memory technologies, F-RAM has no write latency. The write access time to the underlying memory is the same from the start of the read, the user goes through the bus. The entire memory operates in a bus loop. Data polling, an eeprom used to determine if a write is complete is not necessary.

Page Mode Operation

FM23MLD16 provides users with quick access to any data in a row element. There are 4 column address locations per row. Address input A (1:0) defines the column address to be accessed. Paths can start from any column address and other columns can access location CE pins without switching. For fast access reads, the column address input can change (1:0) to the new value once the first data byte is driven onto the bus. New data bytes are driven to the DQ pin no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. When the device is selected (both chip enables asserted), subsequent write pulses provide page mode write access using the new column address. Precharge Operation The precharge operation is to memorize the state being made for the new channel. Pre-charging is enabled by the user in at least one chip-enable signal state. It must be kept at least for the minimum precharge time tPC.

SRAM Insert Replacement FM23MLD16 is designed as a replacement for standard asynchronous SRAM. This device does not need to toggle the new address of the CE pin for each device. Both CE pins may remain active indefinitely. When both CE pins are active the device automatically detects an address change and a new channel has started. This feature allows the chip enable pin to be activated (/CE1 to ground, CE2 to VDD) just like SRAM. It also allows page mode operation at speeds up to 33MHz. A typical application is shown in Figure 2. It shows the pull-up resistor /CE1, keeping the pin high during a power cycle, assuming the MCU/MPU pin is tri-stated in a reset condition. The pull-up resistors should be valued to ensure that the /CE1 pin rail VDD is still a high enough value not to be a problem when /CE1 is low. Although not required, it is recommended to connect CE2 to VDD if the controller provides a valid low chip enable.

For application consumption that requires the lowest power consumption, the /CE1 signal should only be active during memory accesses. The FM23MLD16 draws when /CE1 is low even if the address control signal is static. When /CE1 is high the device does not exceed the current ISB for the maximum standby time. Note that if /CE1 is grounded and CE2 is connected to VDD, the user must be sure that /we have no low power or power down events. Data corruption occurs if the chip is enabled and/ during our low power cycle. The figure shows the MCU/MPU pins tri-stated in a reset condition with a pull-up resistor holding the pin high during a power cycle. The pull-up resistor value should be chosen to ensure that the /WE pin tracks VDD, but the value is high enough that the current drawn when /WE is low is not an issue. A 10Kohm resistor consumes 330uAVDD=3.3V when /WE is low.

The /UB and /LB byte select pins are valid for both read and write cycles. They can be used to allow devices connected as 1Mx8 memory. Upper lower data bytes can be bound together controlled by byte selection. A single byte enable or the next higher address line A (19) may be available from the system processor.

PCB layout recommendations should place 0.1uF decoupling capacitors near each power/ground pair (solder balls 1D/1E and 6D/6E). The ground side of the capacitor should be a ground plane or a low impedance path back to the VSS pins. It is best to use chip low ESR high performance capacitor frequency characteristics. If the controller drives the address and the chip is enabled from the same time edge, it is best to keep the address routes short and of equal length. A simple RC circuit can be inserted into the chip enable path to set the time tAS for the address of the FM23MLD16. As a general rule, the layout designer may want to add series termination resistors at the controller output with fast transitions or path lengths. This is only necessary if the edge rate is lower than or equal to the round-trip tracking delay. Signal overshoot and loopback can be large enough to cause erratic device behavior. It is best to add a resistor (30–60 ohm) near the 50 ohm output driver (controller) to reduce this transmission line effect.

Stresses listed above the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operating specification of the device under these or any other conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

notes

1. VDD=3.6V, CE pin cycles at minimum cycle time. All inputs toggle at CMOS levels (0.2V or VDD-0.2V) and all DQ pins are removed.

2.VDD=3.6V, /CE1 (under VDD) or CE2 (under VSS), all other pins are static and at CMOS level (0.2V or VDD-0.2V).

3. If VDD