feature

125 MSPS guaranteed sample rate ( AD9445BSV-125 ); 78.3 dBFS SNR/92 dBFS SFDR, 30 MHz input (3.2 V pp); 74.8 dBFS SNR/95 dBFS SFDR, 30 MHz input (2.0 V pp); 77.0 dBFS SNR/87 dBFS SFDR, 170 MHz input (3.2 V pp); 74.6 dBFS SNR/95 dBFS SFDR, 170 MHz input (2.0 V pp); 73.0 dBFS SNR/88 dBFS SFDR, 300 MHz input (2.0 V pp); 102 dBFS 2-tone SFDR, 30 MHz and 31 MHz; 92 dBFS 2-tone SFDR, 170 MHz and 171 MHz; 60 fsec rms jitter; good linearity; DNL=±0.25 LSB typical; INL= ±0.8 LSB typical; 2.0 V pp to 4.0 V pp differential full-scale input; buffered analog input; LVDS output (ANSI-644 compatible) or CMOS output; data format selection (offset binary or twos complement); output Clocks available; 3.3 V and 5 V supply operation.

application

Multi-carrier multi-mode cellular receiver; antenna array positioning; power amplifier linearization; broadband wireless; radar; infrared imaging; medical imaging; communication instrumentation.

General Instructions

The AD9445 is a 14-bit monolithic sampling analog-to-digital converter with an on-chip IF sampling track and hold converter (ADC) circuit. It is optimized for performance, small size and ease of use. The product operates at conversion rates up to 125 MSPS and is designed for multi-carrier, multi-mode receivers such as those found in cellular infrastructure equipment. The ADC requires 3.3 V and 5.0 V supplies and a dropout input clock for low voltage full performance operation. Many applications do not require external references or driver components. The data output is CMOS or LVD compatible (ANSI-644 compatible), including reducing the total current required for short tracking distances.

Optional functions allow users to implement various optional operating conditions, including input range, data format selection, IF sampling mode, and output data mode. The AD9445 is available in a lead-free, 100-lead, surface mount, and specified plastic package (100-lead TQFP/EP) over an industrial temperature range of -40°C to +85°C.

Product Highlights

1. High performance: Excellent SFDR performance sampling applications such as multi-carrier, multi-mode 3G, and 4G cellular base station receivers.

2. Ease of use: On-chip reference and high input impedance track and hold adjustable analog input range and output clock simplify data capture.

3. Packaged in lead-free 100 lead TQFP/EP.

4. The clock duty cycle stabilizer (DCS) maintains the performance of the entire ADC over a wide range of clock pulse widths.

5. The OR (Out of Range) output indicates when the signal is outside the selected input range.

6. The RF enable pin allows the user to configure the device for optimal SFDR (AD9445-125) or 240 MHz (AD9445-105) when the sampling frequency of the device is higher than 210MHz.

the term

Analog bandwidth (full power bandwidth)

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3db.

Aperture Delay (tA)

Delay between the 50% point of the rising edge of the clock and the instant the analog input is sampled.

Aperture uncertainty (jitter, tJ)

Sample-to-sample variation of aperture delay.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that a clock pulse remains in a logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should remain low. These specifications define acceptable clock duty cycles for a given clock rate.

Differential Nonlinearity (DNL, no missing code)

An ideal ADC shows code transitions that are exactly 1lsb apart. DNL is the deviation from this ideal value. Guaranteed no missing codes at 14-bit resolution means that all 16384 codes must be present in all working ranges.

Effective Number of Bits (ENOB)

At a given input frequency, the effective number of bits of a sine wave input can be calculated directly from its measured SINAD using the following formula:

gain error

The first code transition should be 1/2 LSB above negative full scale of the analog value. The last conversion should occur at the analog value 1.5 LSB below positive full scale. Gain error is the deviation between the actual difference between the first and last transcoding and the ideal difference between the first and last transcoding.

Integral Nonlinearity (INL)

The deviation of each individual code between the lines drawn from negative full scale to positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as 1.5 LSBs past the last code transition. Measure the deviation from the middle of each specific code to a true straight line.

maximum conversion rate

The clock frequency at which the parametric test is performed.

Minimum conversion rate

The signal-to-noise ratio of the lowest analog signal frequency is below the guaranteed limit by no more than 3 dB of the clock rate.

offset error

When the analog value is lower than VIN+=VIN-, a large carry transition should occur. Offset error is defined as the deviation of the actual transition point from this point.

Out of range recovery time

The time required for the ADC to regain the analog input after transitioning from 10% above positive full scale to 10% above negative full scale or from 10% below negative full scale to 10% below positive full scale.

Output Propagation Delay (tPD)

The delay between the rising edge of the clock and the time when all bits are within valid logic levels.

power supply rejection ratio

The full change from the minimum supply value to the maximum supply value.

Signal to Noise and Distortion (SINAD)

rms The ratio of the input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics, but excluding DC.

signal to noise ratio

The sum of the rms input signal amplitude and all other spectral components below the Nyquist frequency, excluding the first six harmonics and DC.

Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components. Peak spurious components may be harmonics. SFDR can report full scale in dBc (that is, decreases as the signal level decreases) or dBFS (always related to the converter).

temperature drift

The temperature drift of offset error and gain error specifies the maximum change from the initial (25°C) value to the value of Tmin or TMAX.

Total Harmonic Distortion (THD)

The sum of the rms input signal amplitude and the first six harmonic components.

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be IMD products.

Equivalent Circuit

theory of operation

The AD9445 architecture is optimized for high speed and ease of use. The analog input drives an integrated, high-bandwidth track-and-hold circuit that samples the signal prior to quantization by the 14-bit pipelined ADC core. The device includes an on-board reference and input logic that accepts TTL, CMOS or LVPECL levels. The digital output logic levels are user selectable as standard 3V CMOS or LVDS (ANSI-644 compatible) via the output mode pins.

Overview of Analog Inputs and References

The AD9445 contains a stable and accurate 0.5V bandgap voltage reference. The input range can be adjusted by changing the reference voltage applied to the AD9445 using the internal reference voltage or an externally applied reference voltage. The input range of the ADC tracks linear changes in the reference voltage.

Internal reference connection

The comparator in the AD9445 senses the potential at the sense pin and configures the reference to three possible states, as shown in Table 9. If the sensor is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 59), setting VREF to ~1.0V. Connecting the sensor pin to VREF switches the reference amplifier output to the sensor pin, completing the loop and providing a ~1.0V reference output. If the resistor divider is connected as shown in Figure 60, the switch is again set to the sense pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

In all reference configurations, REFT and REFB drive the analog-to-digital conversion core and determine its input range. The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

Internal reference fine-tuning

The internal reference voltage is adjusted during production test to adjust the gain (analog input voltage range) of the AD9445. Therefore, users who provide an external voltage reference to the AD9445 have little advantage. Perform the gain trimming Table 9 with the AD9445 input range set to 2.0 V pp nominal (sense). Refer to the configuration summary connected to AGND). Because of this trimming and the maximum ac performance provided by the 2 VPP analog input range, there is little benefit to using an analog input range less than 2 VPP. Users are warned that the differential nonlinearity of the ADC varies with the reference voltage. Configurations using <2.0v pp may show missing codes, thus degrading noise and distortion performance.

Xref Operations

Adjust the internal reference of the AD9445 to improve the gain accuracy of the ADC. The external reference temperature may be more stable, but the gain of the ADC is unlikely to increase. Figure 49 shows the typical drift characteristics of the internal reference in 1V and 0.5V modes.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 7kΩ load. Internal buffers still generate positive and negative full-scale references (REFT and REFB) for the ADC core. The input span is always twice the value of the reference voltage, therefore, the external reference must be limited to a maximum of 1.6 V.

analog input

As with most new high-speed, high-dynamic-range ADCs, the analog inputs to the AD9445 are differential. Differential inputs improve on-chip performance due to signal processing through attenuation and gain stages. Most of the improvements are differential analog stages with high rejection of even order harmonics. There are also benefits at the PCB level. First, the differential inputs have high common-mode rejection of spurious signals such as ground and power supply noise. Second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. The specified noise and distortion AD9445 cannot be implemented with a single-ended analog input, so such a configuration is discouraged. Contact sales of other 14-bit ADCs that support a single-ended analog input configuration are advised. The reference voltage is 1V, which is nominal (see the Internal Reference Trim section), and the differential input range AD9445 analog inputs are typically 2.0 V pp or 1.0 V pp on each input (VIN+ or VIN-). The AD9445 analog input voltage range is 3.5 V off ground. Each analog input is connected through a 1 kΩ resistor to a bias voltage of 3.5 volts and to the inputs of a differential buffer. An internal bias network at the input appropriately biases the buffer for maximum linearity and range (see Equivalent Circuits section).

Therefore, the analog source driving the AD9445 should be connected to the input pins. The recommended way to drive the analog input to the AD9445 is to use an RF transformer to convert a single-ended signal to a differential signal (see Figure 62). The transformer output and AD9445 analog input help to separate the analog input source from the switching transients caused by the internal sample-and-hold circuit. The series resistor, and the connected 1 kΩ resistor for the internal 3.5V bias, must account for impedance matching to the transformer input. For example, if RT is set to 51Ω and RS is set to 33Ω, with a 1:1 impedance ratio transformer, the input will match a 50Ω supply and a full-scale driver at 10.0 dBm. 50Ω impedance matching can also be included on the secondary side of the transformer, as shown in the evaluation board schematic (see Figure 67).

high frequency application

In applications where the analog input frequency range is greater than 100MHz, phase and amplitude matching of the analog input is critical to optimizing the performance of the ADC. The circuit in Figure 63 can be used to optimize the matching of these parameters. This configuration uses a dual balun configuration with low parasitics, high bandwidth, and parasitic cancellation.

Clock Input Considerations

Any high speed ADC is very sensitive to the quality of the sample clock provided by the user. The track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. Therefore, great care is taken when designing the clock input to the AD9445, and the user is advised to carefully consider the clock source.

Typical high speed ADCs use two clock edges to generate various internal timing signals and, as a result, may be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics. The AD9445 includes a clock duty cycle stabilizer (DC) that retimes non-sampling edges to provide an internal clock signal with a nominal 50% duty cycle. With DCS enabled, the noise and distortion performance is nearly flat over 30% to 70% duty cycle. The DCS circuit latches on to the rising edge of CLK+ and optimizes the timing internally. This allows a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still the most important issue and is not reduced by the internal stabilization circuit. The duty cycle control loop is nominally not suitable for clock frequencies less than 30mhz. In applications where the clock rate can be changed dynamically, the loop is related to a time constant, requiring a latency of 1.5 μs to 5 μs after the dynamic clock frequency is increased or decreased before the DCS loop relocks to the input signal. During the time that the loop is not locked, the DCS loop is bypassed and the internal device timing depends on the duty cycle of the input clock signal. In this application, the duty cycle stabilizer can be appropriately disabled. In all other applications, DCS circuits are recommended to maximize AC performance.

The DCS circuit is controlled by the DCS mode pin; a CMOS logic low (AGND) on DCS mode enables the duty cycle stabilizer, and a logic high (AVDD1=3.3v) disables the controller.

The AD9445 input sampling clock signal must be a high quality, very low phase noise source to prevent performance degradation. Maintaining 14-bit accuracy is an advantage of encoding clock phase noise. When using a high jitter clock source, the SNR performance can easily degrade by 3db to 4db when using a 70mhz analog input signal. (See AN-501 Application Note, Aperture Uncertainty and ADC System Performance.) For optimum performance, the AD9445 must be clocked differentially. The sample clock input is internally biased to ~2.2V, and the input signal is typically AC coupled to the CLK+ and CLK- pins through a transformer or capacitor. Figure 64 shows a preferred method of timing the AD9445. The clock source (low jitter) is converted from single-ended to differential by an RF transformer. Back-to-back Schottky diodes across the secondary of the transformer limit the clock skew to the AD9445 to a PP differential of approximately 0.8 V. This helps prevent large voltage fluctuations of the clock from passing through other parts of the AD9445 and limits the noise presented to the sampling clock input.

If a low jitter clock is available, it may help to bandpass filter the clock reference before driving the ADC clock input. Another option is to AC-couple the differential ECL/PECL signal encoding input pins, as shown in Figure 65.

Jitter Considerations

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given input frequency (f) and rms amplitude, the SNR degradation due only to aperture jitter (t) can be calculated using the following equation:

In the equation, rms aperture jitter represents the rms of all jitter sources, including clock inputs, analog input signals, and ADC aperture jitter specifications. If the undersampling application is particularly sensitive to jitter, see Figure 66.

When aperture jitter may affect the dynamic range of the AD9445, the clock input should be treated as an analog signal. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. A low jitter crystal controlled oscillator is the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be synchronized to the original clock in the last step.

Power Factor

There are radiating components that may be received by the AD9445. Each power pin should be separated from the package as much as possible using 0.1µF chip capacitors.

The AD9445 has separate digital and analog power supply pins. The analog supplies are denoted as AVDD1 (3.3v) and AVDD2 (5v), and the digital supply pins are denoted as DRVDD. Although the AVDD1 and DRVDD supplies can be tied together, performance is best when the supplies are separated. This is because fast digital output fluctuations can couple switch currents back into the analog supply. Note that AVDD1 and AVDD2 must remain within 5% of the specified voltage.

The DRVDD supply for the AD9445 is a dedicated supply for digital outputs in LVDS or CMOS output mode. In LVDS mode, DRVDD should be set to 3.3 V. In CMOS mode, the DRVDD supply can be connected from 2.5 V to 3.6 V, compatible with receive logic.

digital output

LVDS mode

Care should be taken when choosing a power source. A linear DC power supply is strongly recommended. The switching power supply resistor is placed on pin 5 (LVDS_bias) to ground. Dynamic performance, including SFDR and SNR, is maximized when the AD9445 is used in LVDS mode, encouraging designers to take advantage of this mode. The AD9445 outputs include complementary LVDS outputs per data bit (Dx+/Dx-), overrange outputs (or +/or -), and output data clock outputs (DCO+/DCO-). The R resistor currents are multiplied on-chip to set the output current for each output to a nominal 3.5 mA (11 × I). A 100Ω differential termination resistor placed at the input of the LVDS receiver results in a nominal 350 mV swing at the receiver. LVDS mode facilitates interfacing with LVDS receivers in custom ASICs and FPGAs that are LVDS capable and have excellent switching performance in noisy environments. A single point-to-point network topology is recommended, with a 100Ω termination resistor as close as possible to the receiver. It is recommended to keep track lengths under 2 inches and make the differential output track lengths as equal as possible.

CMOS mode

In applications that can tolerate a slight degradation in dynamic performance, the AD9445 output driver can be configured to interface with a 2.5V or 3.3V logic family by matching DRVDD to the digital supply of the interface logic. The CMOS output is available when the output mode is CMOS logic low (or AGND for convenience). In this mode, the output data bits Dx are single-ended CMOS, as are the overrange outputs,

or. The output clock is provided as differential CMOS signals DCO+/DCO-. A lower supply voltage is recommended to avoid coupling switching transients back to the sensitive analog parts of the ADC. Capacitive loading of the CMOS outputs should be minimized and each output should be connected to a single gate through a series resistor (220Ω) to minimize switching transients caused by capacitive loading.

opportunity

The AD9445 provides a latched data output with a pipeline delay of 13 clock cycles. Data output is available one propagation delay (t) after the rising edge of CLK+. See Figure 2 and Figure 3 for detailed timing diagrams.

Operation mode selection

Data format selection

The Data Format Select (DFS) pin of the AD9445 determines the encoding format of the output data. This pin is 3.3V CMOScompatible, logic high (or AVDD1, 3.3V) selects two's complement, and DFS logic low (AGND) selects offset binary format. Table 10 summarizes the output encodings.

output mode selection

Output mode pins control logic compatibility, as well as pins for digital outputs. This pin is a CMOS compatible input. The AD9445 outputs are CMOS compatible when the output mode is 0 (AGND), and the pin assignments for the device are shown in Table 8. When the output mode is 1 (AVDD1, 3.3v), the AD9445 output is LVDS compatible, and the pin assignments of the device are shown in Table 7.

Duty Cycle Stabilizer

The DCS circuit is controlled by the DCS mode pin; a CMOS logic low (AGND) on DCS mode enables the DCS, while a logic high (AVDD1, 3.3v) disables the controller.

RF enabled

The RF enable pin is a CMOS compatible control pin that optimizes the configuration of the AD9445 analog front end. The crossover analog input frequency used to determine the RF enable connection is different for the 105 MSPS and 125 MSPS speed grades. For the 125 MSPS speed grade, connect RF ENABLE to AGND to optimize SFDR performance for applications with analog input frequencies < 210 MHz. For applications with analog inputs greater than 210MHz, this pin should be tied to AVDD1 for best SFDR performance. Connecting this pin to AVDD1 reconfigures the ADC for improved high IF and RF spurious performance. Running in this mode increases power consumption from AVDD2 by 150 mW to 200 mW. For the 105 MSPS speed grade, connect RF ENABLE to AGND to optimize SFDR performance for applications with analog input frequencies < 230mhz. For applications with an analog input greater than 230MHz, this pin should be tied to AVDD1 to optimize performance.

Evaluation Committee

The evaluation board is only used to configure the AD9445 in CMOS or LVDS mode. This design represents the recommended configuration for using the device over a wide range of sample rates and analog input frequencies. These evaluation boards provide all the support circuitry required to operate the ADC in various modes and configurations. Complete schematics are shown in Figures 67 to 70. Gerber files are available from the engineering application and demonstrate proper routing and grounding techniques that should be applied at the system level.

Using a signal source with very low phase noise (<60fsec rms jitter) is key to achieving the ultimate converter performance. Appropriate filtering of the input signal to eliminate harmonics and reduce the overall noise at the input is also necessary to achieve the specified noise performance.

The evaluation board comes with a 115 V ac to 6 V dc power supply. The evaluation board includes low dropout voltage regulators to generate the various DC power supplies required by the AD9445 and its supporting circuitry. Provide a separate power supply to isolate the device under test from supporting circuits. Each input configuration can be selected by the correct connection of various jumpers (see Figure 67).

The LVDS mode evaluation board includes an LVDS-to-CMOS converter, making it compatible with the High Speed ADC FIFO Evaluation Kit (HSC-ADC-EVALA-SC). The kit includes a high-speed data acquisition board that provides a hardware solution for sampling up to 32kb of high-speed ADC output data in a FIFO memory chip (user upgradeable to 256kb of samples). The provided software allows the user to download the captured data to a PC via the USB port. The software also includes behavioral models for the AD9445 and many other high-speed ADCs.

Behavioral modeling of the AD9445 can also be found at /ADIsimADC. ADIsimADC™ software supports virtual ADC evaluation using ADI's proprietary behavioral modeling technology. This allows a quick comparison between the AD9445 and other high speed ADCs with and without a hardware evaluation board.

Users have the option to remove converters and terminations for direct access to the LVDS output.