feature

Single 3 V supply operation (2.7 V to 3.6 V); SNR = 70 dBc to Nyquist at 65 MSPS; SFDR = 85 dBc to Nyquist, 65 MSPS; Low Power: 300 mW at 65 MSPS; 500 MHz bandwidth differential input; on-chip reference and SHA; DNL=0.4 LSB; flexible analog input: 1 volt P to 2 VPP range; offset binary or two's complement data format clock duty cycle stabilizer.

application

Ultrasonic equipment; communication receiver IF sampling: IS-95, CDMA One, IMT-2000; battery-powered instruments; handheld oscilloscopes; low-cost digital oscilloscopes.

Product Description

The AD9235 is a family of monolithic, single 3V supply, 12-bit, 20/40/65MSPS analog-to-digital converters. This family features a high-performance sample-and-hold amplifier (SHA) and voltage reference. The AD9235 uses a multi-stage differential pipeline structure with output error correction logic to provide 12-bit accuracy at data rates of 20/40/65 MSPS with guaranteed code loss over the entire operating temperature range.

The wide bandwidth, true differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in continuous channels, as well as sampling single-channel inputs at frequencies well beyond the Nyquist rate. Not only does the AD9235 save power and cost compared to previously available analog-to-digital converters, it is also suitable for communications, imaging, and medical ultrasound.

A single-ended clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) can compensate for large variations in the clock duty cycle while maintaining good overall ADC performance. Digital output data is displayed in binary or two's complement format. The Out-of-Range (OTR) signal indicates an overflow condition and can be used with the most significant bit to determine low or high overflow.

Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead Thin Shrink Small Outline Package (TSSOP) and a 32-lead Chip Scale Package (LFCSP) and is specified over the industrial temperature range (–40°C to +85°C).

Product Highlights

1. The AD9235 is powered by a 3V power supply and has a separate digital output driver power supply that accommodates both 2.5V and 3.3V logic families.

2. The AD9235 operates at a speed of 65 milliseconds and consumes as little as 300 megawatts of power.

3. The patented SHA input maintains good performance with input frequencies up to 100 MHz and can be configured for single-ended or differential operation.

4. The AD9235 pin is similar to the AD9214-65 and is a 10-bit, 65 MSPS ADC. This simplifies the upgrade path for 65 MSPS systems from 10-bit to 12-bit.

5. The clock DCS maintains the overall performance of the ADC over the entire clock pulse width.

6. The OTR output bit indicates when the signal is outside the selected input range.

Specification Definition

Analog bandwidth (full power bandwidth)

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3db.

Aperture Delay (tA)

Delay between the 50% point of the rising edge of the clock and the instant the analog input is sampled.

Aperture Jitter (tJ)

Sample-to-sample variation of aperture delay.

Integral Nonlinearity (INL)

The deviation of each individual code between the lines drawn from negative full scale to positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as 1 1/2 levels LSB beyond the last code transition. Measure the deviation from the middle of each specific code to a true straight line.

Differential Nonlinearity (DNL, No Missing Code) An ideal ADC would show code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteeing no missing codes at 12-bit resolution indicates that all 4096 codes must be present in all working ranges.

offset error

A major carry transition should occur when the analog value is 1/2 LSB below VIN+=VIN–. Offset error is defined as the deviation of the actual transition point from this point.

gain error

The first code transition should occur at 1/2 LSB of the analog value above negative full scale. The last conversion should occur at 1 1/2 LSBs of the analog value below positive full scale. Gain error is the deviation between the actual difference between the first and last transcoding and the ideal difference between the first and last transcoding.

temperature drift

The temperature drift of offset error and gain error specifies the maximum change from the initial (25°C) value to the value of Tmin or TMAX.

power supply rejection ratio

The total change from the minimum supply to the maximum supply value.

Total Harmonic Distortion (THD)*

The ratio of the rms sum of the first six harmonic components to the rms value of the input signal under test.

Signal to Noise and Distortion (SINAD)*

The ratio of the rms signal amplitude (set to 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics, but excluding DC.

Effective Number of Bits (ENOB)

At a given input frequency, the effective number of digits of a sine wave input device can be calculated directly from its measured SINAD with the following formula:

Signal to Noise Ratio*

The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and DC.

Spurious Free Dynamic Range (SFDR)*

The difference in decibels between the rms amplitude of the input signal and the peak spurious signal.

Two-tone SFDR*

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be IMD products.

Clock Pulse Width and Duty Cycle

Pulse width high is the minimum amount of time that a clock pulse remains in a logic 1 state to achieve rated performance. Pulse width low is the minimum time a clock pulse should remain low. These specifications define acceptable clock duty cycles for a given clock rate.

Minimum conversion rate

The signal-to-noise ratio of the lowest analog signal frequency is below the guaranteed limit by no more than 3 dB of the clock rate.

maximum conversion rate

The clock frequency at which the parametric test is performed.

Output Propagation Delay (tPD)

The delay between the clock logic threshold and the time when all bits are within a valid logic level.

Out of range recovery time

*AC specifications can be reported in dBc (decreased as signal level decreases) or DBF (always relative to converter full scale).

The time required for the ADC to regain the analog input after a transition from 10% above positive full scale to 10% above negative full scale or from 10% below negative full scale to 10% below positive full scale.

Equivalent Circuit

Apply AD9235

theory of operation

The AD9235 architecture consists of a front-end sample-and-hold amplifier (SHA) and a pipelined switched-capacitor ADC. The pipelined ADC is divided into three sections, including 4-bit first stage, 8 1.5-bit stages and a final 3-bit flash. Each stage provides enough overlap to correct flash errors in previous stages. In the digital correction logic, the quantized outputs from each stage are combined into a final 12-bit result. The pipelined architecture allows the first stage to operate on new input samples, while the remaining stages operate on previous samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last stage, consists of a low-resolution flash ADC connected to a switched capacitor DAC and an interstage residual amplifier (MDAC). The residual amplifier amplifies the difference between the reconstructed DAC output and the flash input in the next stage of the pipeline. One bit redundancy is used per stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage contains a differential SHA, which can couple AC or DC in differential or single-ended mode. The outputtaging block aligns the data, performs error correction, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted. During power down, the output buffers go into a high impedance state.

analog input

The analog input to the AD9235 is a differential switched capacitor SHA, which is designed for optimum performance when dealing with differential input signals. The SHA input can support a wide common-mode range and maintain good performance, as shown in Figure 7. The input common-mode voltage of the intermediate supply will minimize signal-related errors and provide the best performance.

Referring to FIG. 6, the clock signal alternately switches the SHA between the sample mode and the hold mode. When the SHA switches to sampling mode, the signal source must be able to charge and stabilize the sampling capacitor within half a clock cycle. Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. Additionally, a small shunt capacitor can be placed at the input to provide dynamic charging current. This passive network will create a low-pass filter at the input of the ADC; therefore, the exact value depends on the application. In undersampling applications, any parallel capacitors should be removed. Combined with the driving source impedance, they will limit the input bandwidth.

For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched so that the common-mode regulation errors are symmetrical. These errors will be reduced by the common-mode rejection of the ADC.

Internal differential reference buffers generate positive and negative reference voltages REFT and REFB, respectively, which define the span of the ADC core. The output common mode of the reference buffer is set to "medium supply", and the reference voltage and reference voltage range are defined as follows:

As can be seen from the equation above, the REFT and REFB voltages are symmetrical around the mid-supply voltage, and by definition the input span is twice the value of the VREF voltage.

The internal voltage reference can be pinned to a fixed value of 0.5 V or 1.0 V, or it can be adjusted within the same range discussed in the Internal Reference Connections section. Maximum signal-to-noise performance will be achieved with the AD935 set to a maximum input span of 2 V PP. The relative SNR degradation will be 3 dB when going from 2 VPP mode to 1 VPP mode.

The SHA can be driven from a source that keeps the signal peaks within the allowable range of the selected reference voltage. The minimum and maximum common-mode input levels are defined as follows:

The minimum common-mode input level allows the AD9235 to accommodate ground-referenced inputs.

Although the best performance is obtained with differential inputs, single-ended supplies may be driven to VIN+ or VIN-. In this configuration, one input will accept a signal, while the other input should be set to midscale by connecting it to the appropriate reference. For example, a 2 V pp signal can be applied to VIN+, while a 1 V reference signal can be applied to VIN-. The AD9235 will then receive an input signal that varies between 2v and 0v. In a single-ended configuration, the distortion performance can be significantly reduced compared to the differential case. However, this effect will be less pronounced at lower input frequencies and lower speed grade models (AD9235-40 and AD9235-20).

Differential Input Configuration

As previously mentioned, the best performance is obtained when driving the AD9235 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible ADC interface. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers will not be sufficient to achieve the true performance of the AD9235. This is especially true if sampling undersampling applications with frequencies in the 70 MHz to 100 MHz range. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 9.

Signal characteristics must be considered when selecting a transformer. Most RF transformers will saturate at frequencies below a few megahertz, and too much signal power will saturate the core, causing distortion.

Single-ended input configuration

In cost-sensitive applications, single-ended inputs can provide adequate performance. In this configuration, SFDR and distortion performance will degrade due to excessive input common-mode oscillation. However, if the source impedances at each input are matched, there should be little impact on the SNR performance. Figure 10 details a typical single-ended input configuration.

Clock Input Considerations

Typical high-speed ADCs use two clock edges to generate various internal timing signals, and the results can be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics. The AD9235 includes a clock duty cycle stabilizer (DC) that retimes non-sampling edges and provides an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clocks without affecting the performance of the AD9235 Enter the duty cycle. As shown in TPC 20, the noise and distortion performance is nearly flat over a 30% duty cycle range.

The duty cycle stabilizer uses a delay locked loop (DLL) to create non-sampling edges. Therefore, any change to the sampling frequency will take about 100 clock cycles to allow the DLL to acquire and lock to the new rate.

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given full-scale input frequency (fINPUT), the SNR degradation due to aperture jitter (tJ) can be calculated as:

In the equation, the rms aperture jitter, tJ, represents the root sum squared of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.

In cases where aperture jitter may affect the dynamic range of the AD9235, the clock input should be treated as an analog signal. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

Power Consumption and Standby Modes

As shown in Figure 11, the power consumption of the AD9235 is proportional to its sampling rate. Digital power consumption does not vary substantially between the three speed grades, as it is primarily determined by the strength of the digital driver and the load on each output bit. The maximum DRVDD current can be calculated as:

where N is the number of output bits, 12 for the AD9235. The maximum current occurs when each output bit switches on each clock cycle, that is, at the Nyquist frequency, a full-scale square wave of FCLK/2. In practical applications, the DRVDD current will be determined by the average number of output bit swaps, which will be determined by the encoding rate and the characteristics of the analog input signal.

For the AD9235-20 speed grade, the digital power consumption can account for 10% of the total power consumption. Digital power consumption can be minimized by reducing the capacitive loading of the output driver. The data in Figure 11 was acquired with 5 pF loaded on each output driver.

The analog circuits are optimally biased, so each speed grade provides excellent performance while reducing power consumption. Each speed grade dissipates a baseline power at low sample rates that increases linearly with clock frequency.

By asserting the PDWN pin high, the AD9235 is placed into standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are in a high impedance state. Reinserting the PDWN pin low will return the AD9235 to its normal operating mode.

Low power consumption in standby mode is achieved by turning off the reference, reference buffer and bias network. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and must then be recharged when normal operation resumes. Therefore, the wake-up time is related to the time spent in standby mode, and a shorter standby period will result in a correspondingly shorter wake-up time. The recommended 0.1µF and 10µF decoupling capacitors on RFT and ReFB take approximately 1 second to fully discharge the reference buffer decoupling capacitors and 3 ms to restore full operation.

digital output

The AD9235 output driver can be configured to interface with 2.5V or 3.3V logic families by matching DRVDD to the digital supply of the interface logic. The output drivers are sized to provide enough output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the power supply, affecting converter performance. Applications that require the ADC to drive large capacitive loads or large fanouts may require external buffers or latches.

opportunity

The AD9235 provides a latched data output with a pipeline delay of seven clock cycles. The data output is available one propagation delay (tPD) after the rising edge of the clock signal. See Figure 1 for a detailed timing diagram.

The length of the output data lines and load should be minimized to reduce transients within the AD9235; these transients can degrade the dynamic performance of the converter.

The minimum typical conversion rate of the AD9235 is 1 MSPS. Dynamic performance may degrade when clock rates are below 1 ms/sec.

voltage reference

The AD9235 has a built-in stable and accurate 0.5V voltage reference. The input range can be adjusted by changing the reference voltage applied to the AD9235 using the internal reference voltage or an externally applied reference voltage. The input range of the ADC tracks linear changes in the reference voltage.

If the ADC is driven differentially through a transformer, the reference voltage can be used to bias the center tap (common mode voltage).

Internal reference connection

The comparator within the AD9235 senses the potential at the sense pin and configures the reference to one of four possible states, as shown in Table 1. If sense is grounded, the reference amplifier switch is connected to an internal resistor divider (see Figure 12), setting VREF to 1 V. Connecting the sense pin to VREF switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 V reference output. If the resistor divider is connected as shown in Figure 13, the switch will again be set to the sense pin. This will put the reference amplifier in a non-vertical mode with the VREF output defined as follows.

In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input range. The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs are tracking each other, a single reference (internal or external) may be required to reduce gain matching errors to acceptable levels. A high-accuracy external reference can also be selected to provide lower gain and offset temperature drift. Figure 14 shows the typical drift characteristics of the internal reference in 1V and 0.5V modes.

When the sense pin is tied to AVDD, the internal references are disabled, allowing the use of external references. The internal reference buffer will load the external reference with an equivalent 7 kΩ load. The internal buffers will still generate positive and negative full-scale references (REFT and REFB) for the ADC core. The input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 V.

If the AD9235's internal reference is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 15 depicts the effect of the load on the internal reference voltage.

Operation mode selection

As mentioned earlier, the AD9235 can output data in offset binary or two's complement format. There is also a provision for enabling or disabling the clock duty cycle stabilizer (DCS). The mode pins are multi-level inputs that control the data format and DCS status. The input thresholds and corresponding mode selections are outlined below.

The mode pin is internally pulled down to AGND by a 20 kΩ resistor.

TSSOP Evaluation Committee

The AD9235 evaluation board provides all the support circuitry required to operate the ADC in various modes and configurations. The converter can be driven by an AD8138 driver or transformer or single-ended differential. A separate power supply pin is provided to isolate the device under test from supporting circuitry. Each input configuration can be selected by the correct connection of various jumpers (see schematic). Figure 16 shows a typical bench characterization setup used to evaluate the ac performance of the AD9235. Using a signal source with very low phase noise (<1ps rms jitter) is key to achieving the ultimate converter performance. Appropriate filtering of the input signal to remove harmonics and reduce the overall noise at the input is also a necessary condition to achieve the specified noise performance.

The AUXCLK input should be selected in applications that require the lowest jitter and signal-to-noise performance (ie, if undersampling characteristics). It allows the user to apply 4 × AD9235's target sample rate to the clock input signal. The low jitter, differential divide-by-4 counter mc100lvel3d provides a 1× clock output, which is then returned to the CLK input through JP9. For example, a 260 MHz signal (sine wave) will be decomposed into a 65 MHz signal used to clock the ADC. Note that R1 must be removed along with the AUXCLK interface. Since many RF signal generators show improved phase noise at higher output frequencies, and the slew rate of a sinusoidal output signal is 4×4 for an equal-amplitude 1× signal, lower jitter is typically achieved with this interface.

The complete schematic and layout diagrams follow and demonstrate proper wiring and grounding techniques that should be applied at the system level.

LFCSP Evaluation Committee

A typical bench setup for evaluating the AD9235's ac performance is similar to the TSSOP evaluation board connections (see schematic for connection details). The AD9235 can be driven single-ended or differentially through a transformer. A separate power supply pin is provided to isolate the device under test from supporting circuitry. Each input configuration can be selected by the correct connection of various jumpers (see schematic).

An alternate differential analog input path using the AD8351 op amp is included in the layout, but not populated in production. Designers interested in evaluating op amps with ADCs should remove C15, R12, and R3 and populate the op amp circuit. The passive network between the AD8351 output and the AD9235 allows the user to optimize the frequency response of the op amp for the application.