feature

Integrated dual 10-bit ADC; single 3V supply operation; SNR = 57.6 dBc (to Nyquist, AD9216-105 ); SFDR = 74 dBc (to Nyquist, AD9216-105); low power: 150mw/ch at 105msps ; 300 MHz 3 dB bandwidth differential input; excellent crosstalk immunity <-80 dB; offset binary or two's complement data format; clock duty cycle stabilizer.

application

Ultrasonic equipment; communication receiver IF sampling; 3G, wireless point-to-point, LMDS, MMDS; battery-powered instruments; handheld oscilloscopes; low-cost digital oscilloscopes.

General Instructions

The AD9216 is a dual 3 V 10-bit 105 MSPS analog-to-digital converter (ADC). It features dual high-performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9216 uses a multi-stage differential pipeline structure with output error correction logic to provide 10-bit accuracy and guarantee no code loss over the entire operating temperature range at data rates up to 105 MSPS. The wide bandwidth, differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. The AD9216 is suitable for a variety of applications, including multiplexed systems that switch full-scale voltage levels in continuous channels, and sampling inputs at frequencies well in excess of the Nyquist rate.

Dual single-ended clock inputs are used to control all internal conversion cycles. There is a duty cycle stabilizer on the AD9216, which compensates for large changes in the clock duty cycle, allowing the converter to maintain good performance. Digital output data is displayed in binary or two's complement format.

Fabricated on an advanced CMOS process, the AD9216 features a space-saving, lead-free, 64-lead LFCSP (9 mm × 9 mm) and is specified over the industrial temperature range (-40°C to +85°C).

Product Highlights:

1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/65 MSPS ADC.

2. 105msps capability, allowing harsh, high frequency applications.

3. Low power consumption: AD9216–105:105 MSPS=300 MW.

4. The patented SHA input maintains excellent performance for input frequencies up to 200 MHz and can be configured for single-ended or differential operation.

5. Typical channel crosstalk <-80 dB from f to 70 MHz.

6. The clock duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

Timing diagram

Pin Configuration and Function Description

the term

analog bandwidth

Simulate the input frequency at which the spectral power of the fundamental frequency (determined by FFT analysis) is reduced by 3db.

Aperture delay

The delay between the 50% point of the rising edge of the encoded command and the instant the analog input is sampled.

Aperture uncertainty (jitter)

Sample-to-sample variation of aperture delay.

Clock pulse width/duty cycle

Pulse width high is the minimum amount of time a clock pulse should remain in a logic 1 state to achieve rated performance; pulse width low is the minimum amount of time a clock pulse should remain low. These specifications define acceptable clock duty cycles for a given clock rate.

crosstalk

When an adjacent interfering channel is driven by a full-scale signal, couples to one channel driven by a low level (-40 dBFS) signal.

Differential Analog Input Resistance, Differential Analog Input Capacitance, Differential Analog Input Impedance

Actual and complex impedance measured at each analog input port. Measure resistance statically, measure capacitance and differential input impedance with a network analyzer.

The differential analog input voltage range must be applied to the converter to produce a peak-to-peak differential voltage for a full-scale response. The peak differential voltage is calculated by looking at the voltage on a single pin and subtracting the voltage 180° out of phase from the other pin. The peak-to-peak difference is calculated by rotating the input phase by 180° and taking the peak measurement again. The difference between the two peak measurements is then calculated.

Differential nonlinearity

Deviation of any code width from the ideal 1lsb step size.

Effective Number of Bits (ENOB)

ENOB is calculated from the measured SINAD according to the equation (assuming full scale input):

Full-scale input power

Expressed in dBm and calculated using the following formula:

gain error

The difference between the ADC's measurement and the ideal full-scale input voltage range.

Harmonic Distortion, Second

The ratio of the rms signal amplitude to the rms value of the second harmonic component, expressed in dBc.

Harmonic Distortion, 3rd

The ratio of the rms signal amplitude to the rms value of the third harmonic component, expressed in dBc.

Integral nonlinearity

Deviation of transfer function from the reference line measured in fractions of 1 lsb from the best straight line determined by least squares curve fit.

Minimum conversion rate

The signal-to-noise ratio of the lowest analog signal frequency is below the guaranteed limit not exceeding the code rate of 3db.

maximum conversion rate

The encoding rate when performing the parametric test.

output propagation delay

Delay between the 50% crossing of the rising edge of CLK and the time when all output data bits are within valid logic levels.

Noise (applies to any range within the ADC)

This value includes thermal and quantization noise:

where: Z is the input impedance. FS is the full scale of the device in relation to the frequency. SNR is the value of a specific input level.

Signal is the signal level within the ADC reported in dB below full scale.

power supply rejection ratio

The specification shows the maximum size change from the maximum value change with supply to the minimum value with supply at its maximum.

Signal to Noise and Distortion (SINAD)

rms The ratio of the rms value of the signal amplitude (set to 1dB below full scale) to the sum of all other spectral components (including harmonics, but excluding DC).

Signal-to-noise ratio (no harmonics) rms The ratio of the signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first seven harmonics and DC.

Spurious Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak spurious spectral components. Peak spurious components may or may not be harmonics. It can also be reported in dBc (ie, decreases as signal level decreases) or dBFS (ie, always relative to converter full scale).

Two-tone intermodulation distortion suppression

The ratio of the rms value of the input tone to the rms value of the worst third-order intermodulation product, in dBc.

Two-tone SFDR

The ratio of the rms value of any input tone to the rms value of the peak spurious components. Peak spurious components may or may not be IMD products. It can also be reported in dBc (ie, decreases as signal level decreases) or dBFS (ie, always relative to converter full scale).

worst other stimulus

The ratio of the rms signal amplitude to the rms value of the largest spurious component (excluding the second and third harmonics), expressed in dBc.

Transient response time

The time required for the ADC to regain the analog input after a transient from 10% above negative full scale to 10% below positive full scale.

Out of range recovery time

The time it takes for the ADC to regain the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.

Typical performance characteristics

AVDD=3.0V, DRVDD=2.5V, T=25°C, differential drive, internal reference, DCS on, unless otherwise specified.

Equivalent Circuit

theory of operation

The AD9216 consists of two high performance ADCs based on the AD9215 converter core. The dual ADC paths are independent except for the shared internal bandgap reference, VREF. Each ADC path consists of a dedicated front-end SHA and a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, including a track-and-hold amplifier, seven 1.5-bit stages, and a final 3-bit flash. Each stage provides enough overlap to correct flash errors in previous stages. The quantized output of each stage is combined by a digital correction logic block into a final 10-bit result. The pipelined architecture allows the first stage to operate on new input samples, while the remaining stages operate on previous samples. Sampling occurs on the rising edge of the corresponding clock.

Each stage of the pipeline (excluding the last stage) consists of a low-resolution flash ADC and a residual multiplier that drives the next stage of the pipeline. The remaining multipliers use the flash ADC output to control a switched-capacitor digital-to-analog converter (DAC) with the same resolution. The DAC output is subtracted from the stage's input signal, and the remainder is amplified (multiplied) to drive the next pipeline stage. The remaining multiplier stages are also known as multiplying DACs (MDACs). A bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC.

The input stage contains a differential SHA that can be configured as ac or dc coupled in differential or single-ended mode. The output scratch block aligns the data, performs error correction, and passes the data to the output buffer. The output buffer is powered by a separate supply, allowing the output voltage swing to be adjusted.

analog input

The analog input to the AD9216 is a differential switched capacitor SHA designed for optimum performance when dealing with differential input signals. The SHA input accepts inputs with a wide common-mode range. To maintain optimum performance, it is recommended to use the input common-mode voltage of the power supply.

The SHA input is a differential switched capacitor circuit. In Figure 41, the clock signal alternately switches the SHA between sample mode and hold mode. When the SHA switches to sampling mode, the signal source must be able to charge and stabilize the sampling capacitor within half a clock cycle. Small resistors in series with each input help reduce the peak transient current required to drive the source output stage. Additionally, a small shunt capacitor can be placed at the input to provide dynamic charging current.

This passive network creates a low-pass filter at the input of the ADC; therefore, the exact value depends on the application. If in sampling applications, remove any parallel capacitors. Combined with the driving source impedance, they will limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched so that the common-mode regulation errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC.

Internal differential reference buffers generate positive and negative reference voltages REFT and REFB, respectively, which define the span of the ADC core. The output common mode of the reference buffer is set to "medium supply", and the reference voltage and reference voltage range are defined as:

As can be seen from the equation above, the REFT and REFB voltages are symmetrical around the mid-supply voltage, and by definition the input span is twice the value of the VREF voltage.

The SHA voltage can be driven from a source that keeps the signal peaks within the allowable range of the selected reference. The minimum and maximum common-mode input levels are defined as:

The minimum common-mode input level allows the AD9216 to accommodate ground-referenced inputs. Although the best performance is obtained with differential inputs, single-ended supplies may be driven to VIN+ or VIN-. In this configuration, one input accepts a signal, while the other input should be set to midscale by connecting it to the appropriate reference.

For example, a 2 volt pp signal can be applied to VIN+, while a 1 volt reference voltage can be applied to VIN-. The AD9216 then receives an input signal that varies between 2v and 0v. In a single-ended configuration, the distortion performance can be significantly reduced compared to the differential case. However, this effect is less pronounced at lower input frequencies.

Differential Input Configuration

As previously mentioned, the best performance is achieved when driving the AD9216 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible ADC interface. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.

At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is insufficient to achieve the true performance of the AD9216. This is especially useful for undersampling applications with sampling frequencies in the 70mhz to 200mhz range. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 43.

Signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz, and excessive signal power can also cause the core to saturate, resulting in distortion.

For DC-coupled applications, the AD8138, AD8139, or AD8351 can be used as convenient ADC drivers as needed. Figure 44 shows an example of the AD8138. An optional AD8139 is available on the AD9216 PCB as shown in Figure 53. Note that the AD8351 generally yields better performance for frequencies greater than 30 MHz to 40 MHz.

Single-ended input configuration

In cost-sensitive applications, single-ended inputs can provide adequate performance. In this configuration, SFDR and distortion performance are degraded due to large input common-mode oscillations. However, if the source impedances at each input are matched, there should be little impact on the SNR performance.

Clock Inputs and Considerations

Typical high-speed ADCs use two clock edges to generate various internal timing signals, and the results can be sensitive to the clock duty cycle. Typically, a 5% tolerance is required for the clock duty cycle to maintain dynamic performance characteristics.

The AD9216 provides separate clock inputs for each channel. Clocks operating at the same frequency and phase achieve the best performance. Timing channels asynchronously can significantly degrade performance. In some applications, it is desirable to skew the clock timing of adjacent channels. The independent clock inputs of the AD9216 allow for clock timing skew between channels (typically ±1ns) without significant performance degradation.

The AD9216 contains two clock duty cycle stabilizers, one for each converter, to retime non-sampling edges, providing an internal clock with a nominal 50% duty cycle. When maintaining a 50% duty cycle is difficult, a faster input clock rate can benefit from using DCS because a wide range of input clock duty cycles can be accommodated. Maintaining a 50% duty cycle clock is especially important in high-speed applications, as maintaining high performance requires proper track and hold times for the converter. DCS can be enabled by tying the DCS pin high.

The duty cycle stabilizer uses a delay locked loop to create non-sampling edges. Therefore, any change to the sampling frequency takes about 2 μs to 3 μs to allow the DLL to acquire and settle to the new rate.

High-speed, high-resolution ADCs are very sensitive to the quality of the clock input. At a given full-scale input frequency (f), the SNR degradation due only to aperture jitter (t) can be given by:

In the equation, RMS aperture jitter represents the root sum squared of all jitter sources, including clock inputs, analog input signals, and ADC aperture jitter specifications. Undersampling applications are particularly sensitive to jitter.

For best performance, especially where aperture jitter can affect the dynamic range of the AD9216, it is important to minimize input clock jitter. The clock input circuit should use a stable reference; for example, use the analog power and ground planes to generate valid high and low numbers for the AD9216 clock input. The power supply for the clock driver should be separated from the ADC output driver power supply to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators are the best clock source. If the clock is generated from another type of source (by gating, division, or other methods), it should be retimed by the original clock in the last step.

Power Consumption and Standby Modes

The power consumption of the AD9216 is proportional to its sampling rate. Digital (DRVDD) power consumption is primarily determined by the strength of the digital drivers and the load on each output bit. Digital drive current can be passed through:

where is the number of bits changed and is the average load on the changed digital pins.

The analog circuits are optimally biased, so each speed grade provides excellent performance while reducing power consumption. Each speed grade dissipates baseline power at a low sampling rate that increases with increasing clock frequency.

Either channel of the AD9216 can be independently put into standby mode by asserting the PWDN A or PDWN B pins. The time to enter or exit standby mode is a maximum of 5 cycles when only one channel is powered down. When both channels are powered down and VREF is grounded, the wake-up time is about 7 ms depending on the decoupling capacitor value.

It is recommended that the input clock and analog input remain static during stand-alone or full standby, which will result in a typical power consumption of the ADC of 3 mW. Typical power consumption of 10 mW is incurred if the clock input remains active in total standby mode.

Minimum standby power is reached when both channels are in full power down mode (PDWN_A=PDWN_B=HI). In this case, the internal reference will be closed. When one or both channel paths are enabled after a power-down, the wake-up time is directly related to the recharge of the REFT and REFB decoupling capacitors and the duration of the power-down.

Individual channels can be turned off for modest power savings. The power-down channel shuts down the internal circuitry, but the reference buffer and shared reference remain powered. Wake-up time is reduced to a few clock cycles as the buffers and voltage reference remain powered.

digital output

The AD9216 output driver can interface directly with the 3V logic family. Applications that require the ADC to drive large capacitive loads or large sectorized outputs may require external buffers or latches, as large drive currents tend to cause current glitches on the power supply, which can affect the performance of the converter.

The data format can be selected for offset binary or two's complement. This will be discussed in the data format section.

output encoding

opportunity

The AD9216 provides a latched data output with a pipeline delay of six clock cycles. The data output is available one propagation delay (t) after the rising edge of the clock signal. See Figure 2 for a detailed timing diagram.

The length of the output data lines and load should be minimized to reduce transients within the AD9216. These transients degrade the dynamic performance of the converter. The AD9216 has a minimum conversion rate of 10 MSPS. Dynamic performance may degrade when clock rates are below 10ms/sec.

Data Format

The AD9216 data output format can be configured as duplex two's complement or offset binary. This is controlled by the data format selection pin (DFS). Connecting DFS to AGND produces offset binary output data. Conversely, connecting DFS to AVDD will format the output data as two's complement.

Output data from dual ADCs can be multiplexed onto a 10-bit output bus. Multiplexing is accomplished by toggling the MUXYSELY bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, Channel A data is directed to the Channel A output bus and Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, channel data is inverted; that is, channel A data is directed to the channel B output bus, and channel B data is directed to the channel A output bus. Multiplexed data can be used on either output data port by toggling the MUX_SELECT bit.

This clock can be applied to the MUX_SELECT pin if the adc is running with synchronous timing. Any skew between CLK_A, CLK_B, and MUX_SELECT will degrade AC performance. It is recommended to keep clock skew <100phs. After the rising edge of MUX_SELECT, either data port has data for its respective channel; after the falling edge, the data for the alternate channel is placed on the bus. Typically, another unused bus is disabled by setting OEB appropriately high to reduce power consumption and noise. Figure 46 shows an example of the multiplexing mode. When multiplexing data, the data rate is twice the sample rate. Note that in this mode, both channels must remain active, and the power down pin of each channel must be held low.

voltage reference

The AD9216 has a built-in stable and accurate 0.5V voltage reference. The input range can be adjusted by changing the reference voltage applied to the AD9216 using an internal reference with different external resistor configurations or an externally applied reference voltage. The input range of the ADC tracks linear changes in the reference voltage.

Internal reference connection

The comparator in the AD9216 senses the potential at the sense pin and configures the reference to three possible states, as shown in Table 9. If the sensor is grounded, the reference amplifier switch is connected to an internal resistor divider (see Figure 47), setting VREF to 1V. If a resistor divider is connected, as shown in Figure 48, the switch is again set to the sensor pin. This puts the reference amplifier in a non-vertical mode and the VREF output is defined as:

Note: Best performance is obtained with VREF = 1.0V; performance degrades as VREF (and full scale) decreases (see Figure 25). In all reference configurations, REFT and REFB drive the ADC core and establish its input range. The input range of the ADC is always equal to twice the reference pin voltage of the internal or external reference.

Xref Operations

An external reference may be required to improve the gain accuracy of the ADC or to improve thermal drift characteristics. When multiple ADCs are tracking each other, a single reference (internal or external) may be required to reduce gain matching errors to acceptable levels. A high-accuracy external reference can also be selected to provide lower gain and offset temperature drift. Figure 49 shows the typical drift characteristics of the internal reference.

When the sense pin is tied to AVDD, internal references are disabled, allowing external references to be used. The internal reference buffer loads the external reference with an equivalent 7kΩ load. Internal buffers still generate positive and negative full-scale references (REFT and REFB) for the ADC core. The input span is always twice the reference voltage value; therefore, the external reference must be limited to 1 V maximum. If the internal reference of the AD9216 is used to drive multiple converters to improve gain matching, the reference loads of the other converters must be considered. Figure 50 depicts the effect of the load on the internal reference voltage.

Shared Reference Mode

Shared reference mode allows the user to connect references from dual ADCs together externally for excellent gain and offset matching performance. If the ADCs work independently, the reference decoupling can be handled independently and can provide better isolation between the dual channels. To enable shared reference mode, the shared reference pin must be tied high and the external differential reference must be shorted externally. (Reference A must be externally shorted to reference B, and reference A must be shorted to reference B.)

Dual ADC LFCSP PCB

PCBs require low jitter clock sources, analog sources, and power supplies. The PCB interfaces directly with ADI's standard two-channel data acquisition board (HSC-ADC-EVALDC), which together with ADI's ADC Analyzer™ software allows for quick ADC evaluation.

power connector

Power is supplied to the board through three removable four-wire power strips.

analog input

The evaluation board accepts a 2 V pp analog input signal, which is centered on the ground of the two SMB connectors (input a and input B). These signals are terminated at their respective primary side transformers. T1 and T2 are broadband RF transformers that provide single-ended to differential conversion, allowing the ADC to be driven differentially, minimizing even order harmonics. The analog signal can be low-pass filtered at the secondary transformer to reduce high frequency aliasing.

Optional op amp

The PCB is designed to accommodate the optional AD8139 op amp, which can serve as a convenient solution for DC-coupled applications. To use the AD8139 op amp, remove C14, R4, R5, C13, R37, and R36, and place R22, R23, R30, and R24.

clock

A single clock input is at J5; the input clock is buffered and drives two channels of input clocks from pin 3 at U8 to R79, R40, and R85. Jumpers E11 to E19 allow the input clock to be inverted. U8 also provides CLKA and CLKB outputs, which are buffered by U6 and U5, which drive the DRA and DRB signals (these are the data-ready clocks off the card). DRA and DRB can also be reversed at their respective jumpers.

voltage reference

The ADC detection pin is brought out to E41, and the internal reference mode is selected by connecting a jumper wire from E41 to ground (E27). External reference mode is selected by placing jumpers between E41 to E25 and E30 to E2. R56 and R45 allow programmable reference mode selection.

data output

The ADC output is buffered on the PCB of U2, U4. The ADC output has a recommended series resistance to limit the effect of switching transients on ADC performance.

Thermal factor

The AD9216 LFCSP package has an integrated thermal slug that, when locally connected to the ground plane of the PCB, improves the thermal and electrical performance of the package. A hot (filled) pass through the array to a ground plane under the part provides a path for the heat to escape the package, lowering the junction temperature. Improved electrical performance is also due to reduced package parasitics due to proximity to the ground plane. Recommended arrays are 0.3mm vias with 1.2mm pitch. θ=26.4°C/W, recommended configuration. Soldering the slag to the PCB is a requirement for this package.

Dimensions