feature

Dual 10-bit/12-bit, 100 MSPS ADC SNR=67 dB, fIN=30.1 MHz; Dual 10-bit/12-bit, 170 MSPS DAC; ACLR=74 dBc; 5 channels of analog auxiliary input/output; low power consumption, 425 mW at maximum sampling rate supports full- and half-duplex data interfaces; small 72-lead LFCSP lead-free package.

application

Wireless infrastructure; picocell base stations; medical device ultrasound AFE; portable instrument signal generators, signal analyzers.

General Instructions

, providing two ADC channels with a sampling rate of 100 MSPS and two DAC channels with a sampling rate of 170 MSPS. These converters are optimized for the transmit and receive signal paths of communication systems that require low power consumption and low cost. The digital interface provides flexible clocking options. Transmission can be configured for 1×, 2×, 4×, 8× interpolation. The receive path has a bypassable 2x decimation low pass filter.

The AD961 and AD963 have five auxiliary analog channels. Three are the inputs to the 12-bit ADC. Two of the inputs can be configured as outputs by enabling the 10-bit DAC. The other two channels are dedicated outputs for two separate 12-bit DACs.

The highly integrated features, small size, and low power consumption of the AD9961/AD9963 make them ideal for portable and low-power applications.

Product Highlights

1. High performance and low power consumption.

The DAC operates on a 1.8 V to 3.3 V supply. At 170 MSPS, the transmission path power consumption is less than 100 mW. Receive path power consumption is less than 350mw at 100msps from 1.8v supply. Sleep and power-down modes are available during low-power idle periods.

2. Highly integrated.

Dual transmit and dual receive data converters, five auxiliary data conversion channels and clock generation provide a complete solution for many modem designs.

3. Flexible digital interface.

The interface works seamlessly with most digital baseband processors.

the term

Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line from zero scale to full scale.

Differential Nonlinearity (DNL)

DNL is a measure of change in analog value, normalized to full scale, relative to a 1lsb change in digital input code.

Monotonicity

A DAC is monotonic if the output increases or stays the same as the digital input increases.

offset error

The deviation of the output current from the ideal zero is called offset error. For TXIN, when all inputs are 0, the expected output is 0 mA. For TXIP, when all inputs are set to 1, the expected output is 0 mA.

gain error

The difference between the actual output range and the ideal output range. The actual range is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.

Output conforms to range

The allowable voltage range at the output of the current output digital-to-analog converter. Operation beyond the maximum compliance limit can result in output stage saturation or breakdown, resulting in nonlinear performance.

temperature drift

Temperature drift is specified as the maximum change from ambient (25°C) value to T or T value, and for offset and gain drift, drift is reported in parts per million of full scale range (FSR) (in degrees Celsius). For reference drift, the drift is reported in ppm/°C.

Power supply rejection

The maximum change as the full-scale output of the power supply changes from the minimum to the maximum specified voltage.

Settling time

Measured from the output transition, the time required for the output to reach and remain within the specified error band around its final value.

Spurious Free Dynamic Range (SFDR)

The difference (in decibels) between the peak amplitude of the output signal and the peak spurious signal between DC and frequency, equal to half the input data rate.

Total Harmonic Distortion (THD)

THD is the ratio of the rms value of the first six harmonic components to the rms value of the measured fundamental. It is expressed in percent or decibels.

signal to noise ratio

SNR is the ratio of the rms value of the output signal under test to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and DC. The signal-to-noise ratio is expressed in decibels.

Adjacent Channel Leak Rate (ACLR)

The ratio between the power measured in one channel and its adjacent channels.

complex image suppression

In conventional two-part upconversion, two images are generated around the second intermediate frequency. These images waste transmitter power and system bandwidth. By connecting the real part of the second complex modulator in series with the first complex modulator, high or low frequency images near the second IF can be rejected.

theory of operation

The AD9961/AD9963 are designed to meet the mixed-signal front-end needs of multiple wireless communication systems. They have a receive path consisting of dual 10/12-bit receive ADCs and a transmit path consisting of dual 10/12-bit transmit DACs (TxDAC). The AD9961/AD9963 integrate additional functions typically required in most systems, such as power supply scalability, Tx gain control, and clock multiplication circuitry.

The AD9961/AD9963 minimize size and power consumption to meet a range of application needs from the low power portable market to the high performance femto base station market. The part is housed in a 72-lead frame chip scale package (LFCSP) with a package size of only 10 mm x 10 mm. By combining power-down control, low-power ADC modes, and TxDAC power scaling, power consumption can be optimized for specific applications.

In full-duplex mode, the AD9961/AD9963 use two 12-bit buses and a qualified clock signal to transfer Rx path data and Tx path data. Both buses support single data rate or double data rate data transfer. The data bus and many other device options can be configured through the serial port by writing to internal registers. The device can also be used in a single-port, half-duplex configuration.

Serial control port

The AD961/AD963 serial control port is a flexible, synchronous, serial communication port that allows easy interfacing with many industry-standard microcontrollers and microprocessors. The AD9961/AD9963 serial control port is compatible with most synchronous transfer formats, including Motorola SPI and Intel SSR protocols. The serial control port allows read/write access to all registers that configure the AD9961/AD9963. Single-byte or multi-byte transfers and MSB-first or LSB-first transfer formats are supported.

Serial Control Port Pin Description

The serial control port has three pins: SCLK, SDIO and CS:

(1), SCLK (serial clock) is the input clock used to register the serial control port read and write. Write data bits are registered on the rising edge of this clock and read data bits are registered on the falling edge. This pin is internally pulled down to ground by a 30 kΩ resistor.

(2), SDIO (serial data input/output) as input and output data pins.

(3), CS (chip selection bar) is an active low level control, which can

Read and write cycles. When CS is high, SDIO is in a high impedance state and SCLK is disabled. This pin is internally pulled to DRVDD by a 30 kΩ resistor.

General Operation of the Serial Control Port

The falling edge of CS and the rising edge of SCLK together determine the start of the communication cycle. The communication cycle with the AD9961/AD9963 is divided into two parts. The first part writes the 16-bit instruction word to the AD9961/AD9963, coinciding with the first 16 SCLK rising edges. The instruction word provides information about the data transfer to the AD9961/AD9963 serial control port, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address of the first byte of the data transfer.

command header

The MSB of the instruction word is R/W, which indicates whether the serial port transfer is a read or a write. The next two bits, N1:N0, indicate the length in bytes of the transfer. The last 13 bits are the address (A12 to A0) to start a read or write operation.

For writes, the instruction word is followed by the number of data bytes indicated by bits N1 through N0 (see Table 10).

A12 to A0 select the addresses in the register map that are written or read during the data transfer portion of the communication cycle. For multibyte transfers, the address is the starting byte address.

Only address bits[A7:A0] need to cover the range of the 0xFF register used by the AD9961/AD9963. Address bits[A12:A8] must always be 0.

write transfer

If the instruction header indicates a write operation, the data bytes written to the SDIO line are loaded into the serial control port buffer of the AD9961/AD9963. Data bits are registered on the rising edge of SCLK.

The length of the transfer (1 byte, 2 bytes, 3 bytes, or streaming mode) is represented by two bits (N1:N0) in the instruction byte. Streaming mode does not skip unused or reserved registers during writes; therefore, the user must know the bit pattern to write to the reserved registers in order to maintain correct operation of the part. It doesn't matter what data is written to unused registers.

read transfer

If the instruction word is used for a read operation, the next N × 8 SCLK cycles clock data from the address specified in the instruction word, where N is 1 to 3 determined by N1:N0. If N=4, the read operation is in streaming mode and continues until CS is raised. Streaming mode does not skip reserved or unused registers. Readback data is valid on the falling edge of SCLK.

MSB/LSB first transmission

The AD9961/AD9963 instruction word and byte data formats can be selected as MSB-first or LSB-first. The default value for the AD9961/AD9963 is MSB first. When MSB first mode is active, instruction and data bytes must be written from the MSB to the LSB. A multibyte data transfer in MSB first format begins with an instruction byte containing the register address of the most significant data byte. Subsequent data bytes must be in order from high address to low address. In MSB first mode, the serial control port internal address generator decrements each data byte of a multibyte transfer cycle.

When LSB first is active, instruction and data bytes must be written from the LSB to the MSB. A multi-byte data transfer in LSB first format begins with an instruction byte that includes the register address of the least significant data byte followed by a number of data bytes. The serial control port's internal byte address generator is incremented for each byte of a multibyte transfer cycle.

It takes effect immediately when LSB first is set by register 0x00 bit 2 and register 0x00 bit 6. In a multibyte transfer, subsequent bytes reflect any changes in the serial port configuration. To avoid problems reconfiguring serial port operation, any data written to 0x00 must be mirrored (eight bits should read the same data, forward or backward). Mirroring the data makes it irrelevant whether LSB first or MSB first takes effect. As an example of this image, the default setting for register 0x00 is 00011000.

End of period transfer

When the transfer is 1, 2, or 3 bytes, the data transfer has been received for the required number of clock cycles. CS can be raised after every 8-bit sequence ends the bus (except after the last byte ends the loop). When the bus is suspended, serial transmission resumes when CS drops. Raising CS on a non-byte boundary resets the serial control port.

The AD9961/AD9963 serial control port register address is decremented from the register address just written to the multibyte I/O operation to 0x00 (if MSB first mode is active (default)). If LSB first mode is active, the register address of the serial control port will be incremented from the address just written to 0xFF for multibyte I/O operations.

Streaming mode transfers always terminate when CS is raised. Streaming mode transfers are also terminated when the address reaches 0xFF. Note that unused addresses are not skipped during multibyte I/O operations. To avoid unpredictable device behavior, do not write to reserved registers.

Sub-serial interface communication

The AD9963/AD9961 have two registers that require different communication sequences. These registers are 0x0F and 0x10. The order in which these two registers are written requires that register 0x05 be written first, then register (0x0F or 0x10), and then register 0xFF. The write takes effect when the write to register 0xFF is complete.

For example, to enable the RXCML pin output buffer, the register write sequence is:

1. Write 0x03 to register 0x05. This addresses both Rx adcs.

2. Write 0x02 to register 0x0F. This will set the RXCML enable bit.

3. Write 0x01 to register 0xFF. This updates the internal registers, thereby activating the RXCML buffer.

4. Write 0x00 to register 0x05. This will return the SPI to normal addressing mode.

An example of updating Register 0x10 is given in the ADC Digital Offset Adjustment section.

receive path

Receive Path General Description

The AD9961/AD9963 receive path consists of dual differential inputs, a 100 MSPS ADC, and an optional 2× decimation filter. The Rx path also has digital offset and gain adjustment.

The dual ADC paths share the same clock and reference circuit to provide the best matching characteristics. ADC has multi-stage differential pipeline switched capacitor structure and output error correction logic. ADCs support IF sampling frequencies up to 140MHz, making them suitable for undersampling receivers. Alternatively, one of the ADCs can be powered down and the digital interface can be placed in single ADC mode. This flexibility makes this section ideal for sampling real signals.

Receive ADC operation

The nominal differential impedance of the Rx path analog input is 4 kΩ. The Rx inputs are self-biased, so they can be AC coupled or direct coupled. The nominal DC bias level of the input is 1.4 volts. There is a buffered version of the bias voltage on the RXCML pin. This voltage can be used to bias external buffer circuits when DC coupling is required.

For best dynamic performance, the analog inputs should be driven differentially. The source impedances driving the Rx inputs should be matched so that the common-mode regulation errors are symmetrical. The Rx input can be driven with a single-ended source, but with reduced SNR and SINAD performance.

ADC reference voltage

An internal differential voltage reference generates positive and negative reference voltages that define the full-scale input voltage of the ADC. This full-scale input voltage range can be adjusted by the RX_FSADJ[4:0] parameter in Configuration Register 0x7D. See the Configuration Registers section for details on setting the voltage.

The nominal input voltage range is 1.56v. In general, there is a trade-off between linearity and signal-to-noise ratio. Increasing the input voltage range can improve the signal-to-noise ratio. Reduce the input voltage range for better linearity.

RXBIAS

The AD9961/AD9963 provide the user the option to place a 10 kΩ resistor between the RXBIAS pin and ground. This resistor is used to set the main current reference for the ADC core. The RXBIAS resistor should have a tolerance of 1% or better to maintain accuracy over the full scale range of the ADC. Care should be taken in the layout to avoid any noise coupling into the RXBIAS pin.

RXCML

The RXCML pin of the AD9961/AD9963 provides the user with a buffered version of the desired ADC common-mode bias voltage. The RXCML output is nominally 1.4V. Bypassing the RXCML output to analog ground maintains output buffer stability and reduces noise. To maintain the accuracy of the RXCML bias voltage, the current drawn from the pin should be kept below 1 mA.

Differential Input Configuration

Best performance is achieved by driving the analog inputs in a differential input configuration. For baseband applications, the ADA437 differential driver provides excellent performance and a flexible ADC interface.

Figure 41 shows the AC-coupled input configuration. The VOCM pin should be connected to a voltage that provides enough headroom for the output driver of the differential amplifier. Typically, setting VOCM to 1/2 the amplifier supply voltage is the best setting. Placing the source resistance in series with the amplifier output isolates the amplifier from the onboard parasitic capacitance for more stable operation.

Set the output common-mode voltage of the ADA4937 to match the common-mode voltage required by the ADC by connecting the RXCML output to the amplifier's VOCM input. The RXCML output is nominally 1.4V. Bypassing the RXCML output to analog ground maintains output buffer stability and reduces noise.

At higher input frequencies, the amplifier required to maintain the full dynamic power of the AD9963 requires considerable supply current. For high frequency power sensitive applications, differential transformer coupling is the recommended input configuration. Signal characteristics must be considered when selecting a transformer. Most RF transformers have saturation frequencies below a few megahertz, and too much signal power can also cause the core to saturate, causing distortion.

In any configuration, the value of the shunt capacitor C depends on the input frequency and may need to be reduced or removed.

Single-ended input configuration

Driving the Rx input with a single-ended signal often limits the achievable ADC performance. When using this configuration, best performance is obtained by maintaining balanced impedances at each Rx input, as shown in Figure 44.

Interface with ADF4602 Rx baseband output

The ADF4602 is an RF transceiver suitable for femtocell and other wireless communication applications. The ADF4602 Rx baseband outputs have a nominal output common-mode voltage that can be set to 1.4 V. The ADF4602 can be data coupled to the AD9963. It is recommended to place a first-order low-pass filter between the two devices to suppress unwanted high-frequency signals that may alias into the desired baseband signal.

In this application, the ADF4602 is setting the common-mode input voltage of the AD9963 adc. The input common-mode buffer of the AD9963 should be disabled (set Register 0x7E, Bit 1 = 1) to avoid contention with the ADF4602 output driver.

Decimation Filter and Digital Offset

Decimation filter

The I and Q receive paths each have a bypassable 2× decimation low-pass filter. A half-band digital filter reduces the output sample rate by a factor of 2, while rejecting aliases that fall into the frequency band of interest. These low-pass filters provide greater than 7dB of stopband rejection for 40% of the output data rate. When used with quadrature signals, the complex output frequency band is 80% of the quadrature output data rate. The passband response plot of the decimation filter is shown in Figure 46.

ADC digital offset adjustment

The Rx path also has a single digital offset that can be applied to the data captured by the ADC. The offset is a 6-bit digital value that is added directly to the LSB of the ADC output data. The offset value is configured by first addressing the ADC by setting the appropriate address in Register 0x05 and then writing the desired offset (in lsb) to Register 0x10. For example, to set the +6 and -2 offsets for the I and Q channels respectively, the register write sequence would be:

1. Write 0x01 to register 0x05. This address is the I-channel ADC.

2. Write 0x06 to register 0x10. This sets the IADC_offset value to +6 LSB.

3. Write 0x02 to register 0x05. This solves the problem with the Q channel ADC.

4. Write 0xFE to register 0x10. This will set the QADC_offset value to -2 lsb.

5. Write 0x01 to register 0xFF. This will update the datapath registers and apply the offset to the data.

6. Write 0x00 to register 0x05. This will return the SPI to normal addressing mode.

transmission path

Send Path General Description

The transmit section consists of two complete paths of interpolation filter stages, each followed by a high-speed current output DAC. The data assembler receives interleaved data from one of the two digital interface ports, and deinterleaves and buffers the data before providing the data samples to the two data paths. The interpolation filter bank consists of three stages that can be completely bypassed or cascaded to provide 2×, 4× or 8× interpolation. The clock rates supported by each interpolation filter and transmit DAC are listed in Table 1.

Interpolation filter

The I and Q transmission paths contain three interpolation filters designated INT0, INT1, and SRRC. Each interpolation filter provides 2x the output data rate. Filters can be completely bypassed or cascaded to provide 2×4× or 8× upsampling rates. The interpolation filter effectively increases the update rate of the DAC while suppressing the image at the input data rate. This reduces the requirement for an analog output reconstruction filter.

The digital filters should be cascaded so that INT0 is enabled at an interpolation factor of 2×, INT0 and INT1 are enabled at an interpolation factor of 4×, and INT0, INT1, and SRRC are enabled at an interpolation factor of 8×.

The bandwidth of the INT0 and INT1 filters is 40% of the input data rate. The passband ripple of the filter is less than 0.1db over the available bandwidth. The attenuation coefficient of SRRC is 0.22 and the stopband attenuation is 60db. In 2x and 4x interpolation modes, the interpolation filter has greater than 70db of image rejection. In 8x interpolation mode, image suppression is greater than 65db. The usable bandwidth of filters is generally limited by the stopband attenuation they provide, not the passband flatness. The transfer functions of the interpolation filters configured for the 2×4× and 8× interpolation ratios are shown in FIGS. 49 to 51 .

Interpolation filter coefficients

Interpolation filters INT0 and INT1 are half-band filters implemented with a set of symmetrical coefficients. Except for the central coefficient, all other coefficients (even coefficients) are zero. Table 17 to Table 19 list the coefficient values for the three interpolation filters.

Data flow and clock generation

The transmit port TXD[11:0] and TXIQ signals are captured from devices with input latches. The data is then formatted and buffered into an 8-word deep FIFO. Data exits the FIFO and is processed by enabling any interpolation filters. Then, the data is sent for sampling by the DAC. The FIFO absorbs any phase drift between the two clock domains driving the transmitted data. Data is read from the FIFO by the RDCLK signal. The RDCLK signal is always the DACCLK divided by the interpolation ratio, I. Data is written to the FIFO by the WRCLK signal at the quadrature data input rate, ff equal to half the bus speed because the I and Q samples are interleaved. Data Data Figure 52 shows a block diagram of the transmission path data flow in full duplex mode. The figure also shows the input data clock options and clock multiplier selection.

The signal on the TXCLK pin can be configured as input or output. This is configured by the TXCLK_MD variable (Register 0x31, Bits[5:4]). Whether configured as input or output, the TXCLK signal can be inverted by configuring the TXCKI_INV or TXCKO_INV variable.

The transmit path clock multiplier is only used when all interpolation filters are bypassed (I=1) and the transmit path is configured in bus rate mode (TX_SDR=1). See Table 22 for more information on configuring the clock multiplier.

Transmit DAC operation

Figure 53 shows a simplified block diagram of a transmission path dac. Each DAC consists of an array of current sources, a switching core, digital control logic, and full-scale output current control. The DAC contains an array of current sources capable of delivering a nominal full-scale current (I) of 2ma. The output currents from the TXIP and TXIN pins are complementary, which means that the sum of the two currents is always equal to the full-scale current of the DAC. The digital input code of the DAC determines the effective differential current delivered to the load. The water outlet DAC is powered through the TXVDD pin and operates from a supply range of 1.8 V to 3.3 V. To facilitate direct connection of the outputs of the AD9961/AD9963 to a range of common-mode levels, an internal bias voltage is provided through the TXCML pin.

The DAC full-scale output current is regulated by the reference control amplifier and is determined by the product of the reference current, a programmable reference resistor R, an internal programmable resistor R, and a pair of programmable gain scaling parameters.

Transmission DAC transmission function

The output currents from the TXIP and TXIN pins are complementary, which means that the sum of the two currents is always equal to the full-scale current of the DAC. The digital input code of the DAC determines the effective differential current delivered to the load. All bits are high when TXIP provides the highest output current. The relationship between the output current output by the DAC and the DACCODE is expressed as:

where DACCODE=0 to 2N-1. A number of adjustments can be made to IOUTFS to provide programmability of output signal levels.

Transmission path gain adjustment

Adjusting the output signal level is accomplished by scaling the full-scale output current of the transmit DAC. There are four independently programmable parameters that can be used to adjust the full-scale output of the DAC: repass voltage, R resistance, and fine and coarse gain control parameters.

Adjust the recirculation voltage

Both the I and Q channel DACs use a reference voltage. The REFIO reference voltage is generated by an internal 100µA current source terminated in programmable resistor R. The nominal R resistance is 10 kΩ, resulting in a 1.0 V reference voltage. The resistance can be changed by adjusting the REFIO_ADJ[5:0] bits in Register 0x6E. This will add or subtract as much as 20% from the R resistor and the resulting REFIO voltage and DAC full-scale current. The second effect of changing the ReFiO voltage is that the full-scale voltage in the auxiliary DAC also changes by the same magnitude. The registers use two complementary formats, where 011111 maximizes the voltage on the ReFio node and 100000 minimizes the voltage. Figure 54 shows the recirculation voltage versus recirculation adjustment value.

The REFIO pin should be separated from AGND with a 0.1µF capacitor. If the voltage at REFIO is for external use, an external buffer amplifier with an input bias current of less than 100nA should be used.

An external reference can be used for applications requiring tighter gain tolerance or lower temperature drift. Additionally, a variable external voltage reference can be used to implement a gain control method for the DAC output. An external reference applies to the REFIO pin. Note that no 0.1µF compensation capacitor is required. External references can directly overdraw internal references or close internal references. The input impedance of the REFIO is 10 kΩ at power-up and 1 MΩ at power-down.

Adjust the current scaling resistor

Each pass DAC has a resistor to adjust the full-scale current. The nominal resistance is 16 kΩ, resulting in a full-scale current of 2 mA (when V equals 1.0 V). The 6-bit programmable values IRSET[5:0] and QRSET[5:0] (Register 0x6A and Register 0x6D) provide an output current adjustment range of ±20%, as shown in Figure 55.

Adjust gain parameters

Each transmit DAC has coarse and fine gain control parameters for scaling the full-scale output current. These adjustments only change the full-scale current of the DAC and have no effect on the recharge voltage. A coarse-scale adjustment (GAAI1) allows the nominal output current to vary by approximately 0.25 dB steps at ±6 dB. The adjustment range of the fine scale adjustment (GAIN2) is about ±2.5%. Figure 56 and Figure 57 show the resulting gain scale as a function of the GAIN1 and GAIN2 parameters.

Send DAC output

The best noise and distortion performance is achieved when the AD9961/AD9963 are configured for differential operation. The source of common-mode error at the DAC output is greatly reduced due to the common-mode rejection of the transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement of distortion performance becomes more pronounced as the frequency content of the reconstructed waveform and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough and noise.

Figure 58 shows the most basic DAC output circuit. A pair of resistors, R, are used to convert each complementary output current to a differential voltage output, V. Since the current output of the DAC is very high impedance, the differential drive point impedance R of the DAC output is equal to 2×R.

Figure 59 shows the output voltage waveform.

The common mode signal voltage V is calculated as:

The peak output voltage V is calculated as:

In this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage.

Set TXCML pin voltage

The TXCML pin is used to change the DAC bias voltage in the part, allowing it to operate at higher common-mode voltages of the output signal. When the common mode of the output signal is lower than 0.8v, the TXCML pin should be connected directly to AGND. When the output signal common mode is greater than 0.8V, the TXCML pin should be set to 0.5V. The TXCML pin should be a low AC impedance source (capacitive decoupling is recommended).

When the TXVDD power supply is 1.8V, the common mode voltage of the output signal should be kept around 0V, and the TXCML pin should be directly grounded. When the TXVDD power supply is 3.3V, the output signal common mode can be as high as 1.25V.

The circuit shown in Figure 60 shows a typical output circuit configuration that provides a non-zero bias voltage at the TXCML pin. Resistor values of 499Ω (R) and 249Ω (R) produce a 2 V pp differential output voltage swing with an output common-mode voltage of 1.0 V, providing 0.5 V to the TXCML pin. 2 mA full-scale current flows through 249 ohms R, resulting in 0.5 volts TXCML. Decoupling capacitors to ensure low AC drive impedance at the TXCML pin.

Transmission DAC output circuit configuration

The following sections describe some typical output configurations of the AD9961/AD9963 pass DACs. Unless otherwise noted, assume I is set to nominally 2.0 mA. For applications requiring the best dynamic performance, a differential output structure is recommended. The differential output configuration can consist of an RF transformer or a differential op amp configuration. The transformer configuration provides the best high frequency performance and is recommended for any application where AC coupling is allowed. Differential op amp configurations are suitable for applications requiring DC coupling, signal gain, and/or low output impedance. The single-ended output of the water outlet is suitable for low-cost and low-power applications. Transformers Differentially coupled RF transformers can be used to perform differential-to-single-ended signal conversion, as shown in Figure 61. The distortion performance of transformers often exceeds that of standard op amps, especially at higher frequencies. Transformer coupling provides excellent rejection of common-mode distortion (ie, even-order harmonics) over a wide frequency range. It also provides electrical isolation, which can provide voltage gain without adding noise. Transformers with different impedance ratios can also be used for impedance matching purposes. The main disadvantages of transformer coupling are low frequency attenuation, insufficient power gain, and high output impedance.

The center tap on the primary side of the transformer must be connected to a voltage that keeps the voltage on TXIP and TXIN within the output common-mode voltage range of the device. Note that the dc component of the DAC output current is equal to I and flows out of TXIP and TXIN. The center tap of the transformer should provide a path for this DC current. In most applications, AGND provides the most convenient voltage for the transformer center tap. The complementary voltages present at TXIP and TXIN (that is, V and V) swing symmetrically around AGND and should remain within the output compliance range specified by the AD9961/AD9963.

In applications where the transformer output is connected to the load R through a passive reconstruction filter or cable, a differential resistor R can be inserted. The R reflected by the transformer is chosen to provide source termination that results in a low voltage standing wave ratio (VSWR). Note that about half of the signal power is dissipated on R.

Differential Buffered Output Using Op Amp Dual op amps (see the circuit shown in Figure 62) can be used in a differential version of the single-ended buffer shown in Figure 63. The same RC network is used to form a single-pole differential low-pass filter to isolate the op amp input from the high frequency image produced by the DAC output. The feedback resistor R is determined by the following formula:

The minimum single-ended voltages at the amplifier outputs are:

The common-mode voltage of the differential output is determined by:

Using the single-ended buffer output of an op amp An op amp, such as the ADA4899-1, can be used to perform single-ended current-to-voltage conversion, as shown in Figure 63. The AD9961/AD9963 are configured with a pair of series resistors, R, that turn off each output. For best distortion performance, R should be set to 0Ω. The feedback resistor R is given by the following formula:

The maximum and minimum voltages at the output of the amplifier are:

Interface with ADF4602

The ADF4602 is an RF transceiver suitable for Femtocell and other wireless communication applications. The ADF4602 Tx baseband inputs have a nominal input common-mode voltage requirement of 1.2 V. As shown in Figure 64, the AD9963 can be DC coupled to the ADF4602. When configured for a full-scale current of 2 mA, the output of the circuit swings 1 volt ppd centered at 1.2 volts. The TXMCL pin is biased at 0.5V to increase the headroom at the DAC output. The TXVDD and CLK33V supplies must provide 3.3v to support the output compliance range of the DAC.

An optional 100 kΩ resistor connected between the AUXIO pin and the TXIN (and TXQN) pin allows a DC offset to be provided at the ADF4602 output to make the LO feedthrough zero.

Device timing

clock distribution

The clock distribution diagram shown in Figure 65 outlines the clock options for each data converter. The receive path adc and transmit path dac can be clocked directly from the CLKP/CLKN input or from the output of the on-chip DLL. The auxiliary ADC sample clock is always a split version of the input clock. The auxiliary DAC is updated synchronously with the serial clock, independent of the CKP/CKN input. The best data converter performance is achieved when a low jitter clock source drives the CLKP/CLKN input, and this signal is used directly (or via an on-chip divider) as the data converter sampling clock. The ADC and DAC sampling clocks are independently selected to be derived from the CLKP/CLKN input or from the DLL output DLLCLK. Using DLLCLK as the data converter sampling clock signal may degrade the converter's noise and SFDR performance. More information is given in the Clock Multiplication Using DLLs section.

The receive path ADC has a duty cycle stabilizer (DCS) that helps make the ADC performance insensitive to changes in the input clock duty cycle. DCS can be bypassed. See the "Clock Duty Cycle Considerations" section for recommendations on using DCS.

The ADC clock divider and DLL clock multiplication support various ratios between the receive path ADC sampling clock and the transmit path DAC sampling clock. Table 21 details the specific values supported by the device and the register bits that need to be configured.

drive clock input

For best performance, the AD9961/AD9963 clock inputs (CLKP and CLKN) should be clocked with low jitter, fast rise time differential signals. This signal should be ac-coupled to the CLKP and CLKN pins through a transformer or capacitor. The CLKP/CLKN inputs are internally biased and do not require external bias circuitry. Figure 66 through Figure 69 show the preferred method for timing the AD9961/AD9963.

In applications where the receiving analog input signal and the sending analog output signal are at low frequencies, a single-ended CMOS signal can be used to drive the sample clock input. In this application, CLKP should be driven directly from the CMOS gate and the CLKN pin should be grounded through a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 67). Series termination resistors at the output of the clock driver can improve the dynamic response of the driver.

Note that the 39 kΩ resistor shown in the CMOS clock driver example shifts the CLK_N input to about 0.9v. This is optimal when the CMOS driver is powered by a 1.8v supply.

2.5v CMOS drivers can also be used. In this case, the minimum CLK 33V supply voltage should be 2.5 V. In this case, the 39 kΩ resistor should be removed. Connecting CLKN to ground with only a 0.1µF capacitor causes the CLKN voltage to be biased to about 1.2v.

Clock Duty Cycle Considerations

The duty cycle of the input clock should be kept between 45% and 55%. Duty cycles outside this range can affect the dynamic performance of the ADC. This is especially true at sample rates greater than 75mhz. It is recommended to use a duty cycle stabilizer (DCS) at clock frequencies above 75 MHz to ensure that the sampling clock maintains the proper duty cycle inside the device. Below 75 MHz, DCS should be bypassed. By setting register 0x66, bit 2 high, DCS is bypassed.

DLL duty cycle warning

The stability of the DLL output requires that the duty cycle of the master clock input be less than or equal to 50%. In systems with duty cycles greater than 50%, care should be taken to swap the CLKP and CLKN pins to reverse this effect.

Clock Multiplication Using DLL

The AD9961/AD9963 contain a circular DLL as shown in Figure 70. This circuit allows the input CLK signal (REFCLK) to be multiplied by a programmable M/N factor. This provides a way to generate a wide range of DLL output clock (DLLCLK) frequencies. The DLLCLK signal can be used to receive the ADC sampling clock, transmit the DAC sampling clock, or both. If desired, the EXTDLLCLK signal can be programmed to appear on the TXCLK pin or on TRXCLK.

The dynamic link library consists of a ring oscillator made of programmable delay lines. The ring oscillator output signal is labeled MCLK. The MCLK signal is set to oscillate at a frequency M times greater than the REFCLK signal. The DLL output clock DLLCLK is the MCLK signal divided by a programmable factor, NM can be set to a value between 1 and 32, and N can be set to a value between 1 and 6 and 8.

DLL frequency lock range

The DLL frequency lock range is determined by the output frequency of the ring oscillator MCLK. The MCLK frequency range for DLL locking is 100 MHz to 310 MHz. The DLL lock can be verified by polling the DLL lock bit (Register 0x72, Bit 7).

DLL Filter Considerations

The DLL requires an external loop filter between the DLLFILT pin (pin 54) and ground for stable operation. The circuit diagram in Figure 71 shows the recommended DLL filter configuration. External components should be placed as close as possible to the device pins. It is important that no noise is coupled into the filter circuit or the DLL output clock jitter performance degrades.

Dynamic link library startup program

To enable DLL, three bits should be set. The DLL bit (Register 0x60, Bit 7) and the DLL REF_EN bit (Register 0x71, Bit 4) should be set to 1, and the DLLBIAS_PD bit (Register 0x61, Bit 5) should be set to 0.

The CLK input signal should be stable. The DLL RESB bit should be asserted low for at least 25 microseconds and then inactive (high) to start frequency acquisition. The DLL needs several REFCLK cycles to acquire the lock. The DLL lock bit can be queried to verify that the DLL is locked.

Configuring the Clock Multiplier

Each receive and transmit data path has a clock multiplier used to clock data through the device. These clock multipliers are only used in single data rate clock mode when no interpolation or decimation is used.

These multipliers should be configured according to the following guidelines.

Register 0x3A, Register 0x3B, and Register 0x3C configure the operating point of the multiplier and should be initialized with the following values: 0x3A=0x55, 0x3B=0x55, 0x3C=0x00

The clock multiplier mode and pulse width should be configured according to the DAC and ADC sampling rates. Should be configured according to Table 22.

digital interface

The AD9961/AD9963 have two parallel interface ports: the Tx port and the TRx port. The operation of the port depends on whether the device is configured in full-duplex or half-duplex mode.

In full duplex mode, the TRx and Tx ports work independently. The TRx port outputs samples from the receive path, and the Tx port receives incoming samples from the transmit port.

In half-duplex mode, the TRx ports output samples from the receive path and accept incoming samples from the transmit path. The send port is disabled. The operation of the digital interface is described in detail in the following sections.

TRX port operation (full duplex mode)

In full-duplex mode, the TRX port obtains data from the AD9961/AD9963 I and Q receive channels. The interface consists of an output data bus (TRXD[11:0]) that carries interleaved I and Q data. The data is accompanied by a defined output clock (TRXCLK) and an output signal (TRXIQ) that identifies the data as coming from the I or Q channel. The maximum guaranteed data rate is 200 MSPS.

The basic timing diagram of the Rx path is shown in Figure 72. By default, the time-aligned TRXD[11:0] and TRXIQ output signals are driven on the rising edge of the TRXCLK signal. Table 23 specifies the t parameter. OD Another configuration bit, RXCLKPH, can be used to invert TRXCLK. In this case, the TRX data and TRXIQ signals are driven on the falling edge of TRXCLK, and t is measured relative to the falling edge of TRXCLK.

Simultaneously sample the analog signal to form a pair of quadrature data. This creates two possible sequences of data pairs on the output bus: I data followed by Q data, or Q data followed by I data. There are also two possible ways to align the bus data to the TRXIQ signal, one is I data aligned with TRXIQ high, and the other is I data aligned with TRXIQ low. The IQ pairing and data-to-TRXIQ alignment relationships create four possible timing patterns. The AD9961/AD9963 enable any of these four modes to be obtained from the device. The data pairing order is controlled by the first bit of RX. The phase relationship between the Rx data and the RXIQ signal is controlled by the RXIQ-HILO bits. These two programming options generate the four timing diagrams shown in Figure 73.

The output clock on TRXCLK can also be configured as a double data rate (DDR) clock. In this mode, the output clock is divided by 2 and the samples are placed on the TRXD[11:0] bus on the rising and falling edges of TRXCLK. Figure 74 shows the time.

Single ADC Mode

The receive port can only operate if one of the ADCs is working. In this mode, the TRXCLK signal can operate in bus rate clock mode or double data rate clock mode. The TRXIQ pin indicates which ADC is active. Figures 75 through 78 show the available timing options.

In addition to the different timing modes listed in Figures 75 through 78, input data can also be transferred from the device in unsigned binary or two's complement format. The format type is selected by the RX_BNRY configuration bit.

TX port operation (full duplex mode)

The Tx port uses a qualified clock that can be configured as input or output. The incoming data (TXD[11:0]) must be accompanied by the TXIQ signal, which identifies which transport channel (I or Q) the data is to be sent to. By default, the data and TXIQ signals are latched by the device on the rising edge of TXCLK. The timing diagram is shown in Figure 79:

Assemble the input samples of the device to create orthogonal data pairs. The data can be ordered in two possible data pairings, and with two possible data-to-TXIQ signal phase relationships. This yields four possible timing modes. The AD9961/AD9963 can be configured to accept any of these four modes. The data pairing order is controlled by the first bit sent. The data relative to the TXIQ phase is controlled by the TXIQ-HILO bits. These two programming options generate the four timing diagrams shown in Figure 80.

In addition to the different timing modes listed above, the device can accept input data in unsigned binary or two's complement format. The format type is selected by sending configuration bits.

The Tx port has an optional double data rate (DDR) clock mode. In DDR mode, transmit data is latched on the rising and falling edges of TXCLK. The polarity of the edge identifies the destination channel of the incoming data. In this mode, the TXIQ signal is not required.

Interleaved digital data for the I and Q DACs is accepted by the Tx bus (TXD([11:0]). Data must be presented to the device to hold during setup and hold times t and t around the rising and falling edges of the TXCLK signal Stable. A detailed timing diagram is shown in Figure 81.

In DDR mode, the TXCLK signal is always an input and must be provided along with the data. Table 24 gives the setup and hold time requirements for Tx ports in DDR mode:

half duplex mode

The AD9961/AD9963 offer half-duplex mode to support a reduced-width digital interface. In half-duplex mode, the transmit and receive ports are multiplexed onto the TRXD, TRXIQ, and TRXCLK lines. The direction of the bus can be controlled by the TXIQ/TXnRX pins (referred to simply as the TXnRX pins in the remainder of this section) or by the serial port configuration registers.

The operation of the transmit and receive ports in half-duplex mode is very similar to that in full-duplex mode. In half-duplex mode, the interface can be configured to operate with a single clock pin or with two clock pins. When in Rx mode (source data), the TRX port operates the same in half-duplex mode as it does in full-duplex mode. In Tx mode, the TXIQ and TXD[11:0] signals are mapped to the TRXIQ and TRXD[11:0] pins, respectively. The TXCLK pin is mapped to the TRXCLK pin in one clock mode and remains on the TXCLK pin in two clock modes. Therefore, in single clock mode, when set in the Rx direction, the TRXCLK pin carries the RXCLK signal, and when set in the Tx direction, the TRXCLK pin carries the TXCLK signal. In dual clock mode, the TRX pin carries the RXCLK signal and the TXCLK pin carries the TXCLK signal, regardless of the bus direction. By default, the clock provided by the device only exists when the corresponding direction of the bus is active. The setup and hold times for the TRx ports are shown in Table 25.

The bus turnaround time is shown in Figures 83 and 84.

Auxiliary converter

The AD9961/AD9963 feature two fast and stable servo DACs, as well as one analog input and two analog I/O pins. All auxiliary converters run on a dedicated power supply pin. Input and output compliance ranges depend on the supplied voltage.

Auxiliary ADC

The auxiliary ADC is a 12-bit SAR converter accessed and controlled through the serial port registers (Register 0x77 via Register 0x7b). The ADC voltage reference and clock signals are generated on-chip. There is a seven-input multiplexer in front of the auxiliary ADC. The ADC input can be connected to the AUXIN1, AUXIO2, AUXIO3 input pins, or to one of the four internal signals, as shown in Figure 85.

Conversion clock

The auxiliary ADC conversion clock is generated by programmable binary division of the CLK input signal. The frequency of the ADC conversion clock is programmable and can be calculated by the following formula:

where R is programmed through Register 0x7A, Bits[2:0]. For best performance and lowest power consumption, the conversion clock speed should be set to the lowest speed that meets the system conversion time requirements. The maximum allowed auxiliary ADC clock speed is 10 MHz.

voltage reference

The auxiliary ADC has an internal, temperature stable, 2.5 volt reference. This results in an input voltage range of 0 V to 3.2 V. When using the internal voltage reference, the AUXADCREF pin should be separated from AGND by a 0.22µF capacitor. The AUXADCREF pin can be used as a reference output for external devices, but the current load on the pin should be limited to less than 5mA source and less than 100µA sink.

For systems with high precision requirements, a higher precision external reference can be used to supply voltage to the AUXADCREF pin. The input voltage range of the external voltage reference is 1.0 V to 2.5 V. The input impedance of the AUXADCREF pin is 100 kΩ. The full-scale input voltage of the ADC is a function of the voltage reference as follows:

analog input

The ADC can be configured to sample one of eight analog inputs. Inputs are selected via the channel select bits (Register 0x77, Bits[2:0]). These eight signals are described in Table 28.

When selected, input pins 70, 71 and 72 are connected to the sampling cap of the auxiliary ADC. Therefore, the circuit driving these inputs needs to be within the sampling window from connecting the discharged 10pf capacitor to it at the beginning of the conversion to recover to the desired accuracy. A programmable delay (Register 0x7B, Bits[1:0]) can be added to the conversion cycle time to allow additional settling time for the input. If the ADC input is driven by a low source impedance, such as the output of an op amp, a conversion time of 20 cycles should yield good results. High impedance sources may require a transition time of 34 cycles to fully stabilize. If conversion cycle time is not an issue, a full 34-cycle conversion time is recommended.

Conversions where the input multiplexer switches between inputs require a longer conversion cycle time than consecutive conversions from the same multiplexer input.

Digital output coding

The digital output encoding is straight binary. The ideal transfer characteristics of the auxiliary ADC are shown in Figure 86.

Auxiliary ADC Conversion Cycle

A conversion is initiated by writing to SPI Register 0x77. Conversions begin on the first rising edge of AUXADCCLK after writing to Register 0x77 (serial port register writes are completed on the eighth rising edge of SCLK during a data word write cycle). Depending on the conversion time setting programmed in Register 0x77, conversions take 20 to 34 AUXADCCLK cycles to complete. In most cases, ADC throughput is a function of serial port clock rate and ADC conversion time.

Figure 87 shows a typical timing scheme for the auxiliary ADC conversion cycle. The scene shows a write that initiates a transformation, followed by a read that retrieves the results of the transformation. In some cases, it may be necessary to add a wait time between writes and reads to ensure that the conversion completes. The latency depends on the ADC conversion cycle time and the speed of the serial port clock. The minimum wait time is calculated as follows:

where n is the number of auxiliary ADC clock cycles resulting from the conversion time setting in Register 0x7b.t and is the serial port clock cycle. A negative wait time means that no wait time is required.

It is important to note that the ADC takes about 100µS to stabilize after initial power-up or recovery from power-down. In many cases, the result of the first conversion should be discarded in order to assist the ADC to achieve optimal operating conditions.

Auxiliary DAC

The AD963 has two 10-bit auxiliary DACs and two 12-bit auxiliary DACs for calibration and control functions. The dac has a voltage output with selectable full-scale voltage and output range. Auxiliary DAC configuration and update via serial port interface.

10-bit auxiliary DAC

The two 10-bit DACs have the same transfer function and output on the AUXIO2 and AUXIO3 pins. Both DACs can be enabled and configured independently. The DAC has 5 selectable maximum scale voltages and 4 selectable output ranges, resulting in 20 possible transfer functions.

The circuit is easiest to analyze using a superposition of the op amp's two inputs, a 0.5V reference, and a programmable current source. The following equation describes the no-load output voltage:

DACCODE (see Register 0x49 and Register 0x4A for DAC10A and Register 0x46 and Register 0x47 for DAC10B) is interpreted as I at full scale at 0x000 and zero at 0x3FF. This will cause the output voltage to increase with code as shown in Figure 89 and Figure 90. Five selectable gain settings Resistors 3.2 kΩ, 4.0 kΩ, 5.3 kΩ, 8.0 kΩ, and 16 kΩ result in full-scale output voltage levels of 3.0 V, 2.5 V, 2.0 V, 1.5 V, and 1.0 V, respectively Four selectable Full-scale currents of 31µA, 62µA, 93µA, and 124µA yield voltage output ranges of 0.5v, 1.0v, 1.5v, and 2.0v, respectively.

The curves in Figure 89 represent four possible DAC transfer functions with a full-scale voltage of 3.0V and spans of 0.5V, 1.0V, 1.5V, and 2.0V. The curves in Figure 90 represent four possible DAC transfer functions with a full-scale voltage of 1.5V, a span of 0.5V, 1.0V, 1.5V, and 2.0V. Note that a 2.0V span results in clamping at the lower end of the scale at 0V, where the equation results in a negative output voltage.

12-bit auxiliary DAC

The two 12-bit DACs have similar transfer functions and output on the DAC12A and DAC12B pins. Both DACs can be enabled and configured independently. Figure 91 shows a simplified schematic of the 12-bit auxiliary DAC.

Note that VREF can be derived from a 1.0V bandgap reference or ratiometrically using an AUX33V supply. Another gain stage follows the DAC that sets the final full-scale output voltage. The following equation describes the no-load output voltage:

where Vis is set to the bit combination shown in Table 29.

1x=A or B.

The curves in Figure 92 show the two transfer functions when using the internal 1.0V bandgap reference.

power supply

The AD9961/AD9963 power distribution is shown in Figure 93. The function blocks labeled Rx ANLG, Rx ADC, SPI and digital core, clock and DLL operate from a 1.8 V supply. The functional blocks labeled TX DACS, AUX DACs, and digital I/O operate over a supply voltage range from 1.8 V to 3.3 V. The auxiliary ADC operates from a 3.3V supply.

By using the RX18V, RX18VF, DLL18V, CLK18V and DVDD18V power pins, only 1.8V modules can be powered directly with 1.8V. In this mode, the on-chip voltage regulator must be disabled. To provide the best ESD protection for the device, the input to the LDO regulator should not be left floating. When not used, the LDO regulator input should be connected to one of the LDO outputs (for example, if RX33V is not used, connect RX33V to RX18V or RX18VF).

When using LDO regulators, the RX18V, RX18VF, DLL18V, CLK18V, and DVDD18V pins should be separated from ground with 0.1µF or larger capacitors. The LDO input can operate from 2.5v to 3.3v.

The LDO_EN pin (pin 14) is a tri-state input pin that controls the operation of the LDO. When LDO_EN is high, all LDOs are enabled. When LDO_EN is low, all LDOs are disabled. When LdoxEN is floating or approximately DRVDD/2, only the DVDD18V LDO is enabled. With the exception of the DVDD18V LDO, all LDOs can be independently disabled through serial port control and writing to Register 0x61.

The three DRVDD pins are connected together internally, therefore, these pins must be connected to the same voltage. As described in the Digital Interface section, the voltages applied to these pins affect the timing of the device.

The TXVDD and AUX3V supplies can operate from 1.8 V to 3.3 V. It should be noted that the auxiliary ADC requires Aux33 V to operate at 3.3 V. The performance of the Tx DAC varies with the TXVDD supply, as shown in Table 1 and Figures 4 through 11.

Example of Power Configuration

There are several ways to configure the AD9961/AD9963 power supply. Two example power supply configurations are shown in Figure 94 and Figure 95.

Figure 94 shows the 3.3V supply configuration. In this case, all internal circuits that require a 1.8V supply are powered by an on-chip regulator. The LDO_EN pin is set high and all internal LDOs are enabled. Send DACs, auxiliary converters, and I/O pads run from a 3.3V supply.

Figure 95 shows a power supply configuration where all 1.8V rails are powered by an external power supply. The LDO_EN pin is grounded and all internal LDOs are disabled. Send DACs, auxiliary converters and I/O pads run from a 3.3V supply.

Power consumption

The power dissipation of the AD9961/AD9963 is highly dependent on the operating conditions. Table 30 and Figure 96 through Figure 103 show the typical current consumption of the power domain under different operating conditions.

The current consumption of the 1.8V supplies is independent of whether they are powered by the on-chip regulator or an external 1.8V supply. The quiescent current of the LDO regulator is about 100µA.

The Aux33V supply current drawn by the auxiliary ADC is typically 350µA. The 10-bit auxiliary DAC typically draws 275µA from the Aux3V supply. The 12-bit auxiliary DAC typically draws 550µA from the Aux33V supply.

Power Calculation Example

The following example demonstrates how to estimate device power consumption under typical operating conditions. Working conditions: f=60mhz f=120mhz f=120mhz f=60mhz 4×interpolation CLK company dynamic link library digital-to-analog converter analog-to-digital converter;

2 × draw;

DAC full-scale current = 2 mA;

TXVDD=CLK33V=AUX33V=3.3V;

Auxiliary ADC enable;

All other power supplies are powered from an external 1.8 V supply.

Boot sequence example

configure DLL

The AD9963 dynamic link library is shown in the clock distribution diagram in Figure 65. The registers written in Table 31 configure the DLL to drive the DACs from the main CLKP/CLKN inputs with a multiplier of 10 and a division of 3. From the default register settings at reset, this requires a 20 MHz CLKP/CLKN clock, multiply it by 200 MHz, then divide the clock by 3 to get 66.67 MHz. Writing to Register 0x71 configures the DAC clock to come from the DLL. By default, the Rx and Tx data buses operate in SDR mode. The clock frequency of each DAC is 66.67mhz and the TxCLK pin outputs 133.33mhz.

Configure Clock Multiplier (DDLL)

The AD9963 includes two clock multipliers. If the Rx clock multiplier is enabled, the frequency of the CLKP/CLKN signal is multiplied when entering the circuit that generates ADCCLK (Figure 65). The Tx clock multiplier multiplies the DACCLK signal and can optionally be included in the TxCLK generator circuit (Figure 52). When the ADC and DAC are operating at frequencies above 15 MHz, it is recommended to use both clock multipliers.

Bypass the duty cycle stabilizer in the ADCCLK generator circuit when operating below 75 MHz, taking care to ensure that the duty cycle is 45% to 55% of the CLKP/CLKN clock input. The write sequence in Table 32 configures the Rx clock multiplier to clock the ADC from reset. These writes are for ADC clocks less than 75mhz.

This sequence can be used to set clocks greater than 75MHz by removing the write to register 0x66.

Dimensions: