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64 Kbit/ 256 Kbit Ferroelectric Random Access Memory (F-RAM) logically organized as 8K×8 ( FM31L276 )/32K×8FM31L278) high endurance 100 trillion (1014) read/write 151 years data retention period (see Data Retention and Endurance Table) NoDelay 8482 ; Write Advanced High Reliability Ferroelectric Process High Integration Device Replaceable Multiple Parts Serial Non-Volatile Memory Real Time Clock (RTC) Low Voltage Reset Early Power Loss Warning/NMI Two 16 Bit event counter Serial number with write lock for security Real-time clock/calendar Backup current at 2 V: 1.15∏A, +25∏C 10064 ; seconds, in BCD format for centuries Tracking years spanning 2099 use Standard 32.768 kHz crystal (6 pF/12.5 pF) Software calibration Supports battery backup or capacitor Processor Companion Active low reset output for VDD and watchdog Programmable low VDD reset trip point Manual reset filtering and denoising Programmable gate Dog Timer Dual Battery Event Counter Tracks System Intrusion or Other Events Power Failure Interrupt Comparator 64-bit Programmable Serial Number with Lock RTC, master device controlled via I2C interface Select pins for up to 4 memory devices Low power consumption 1.5 mA at 1 MHz Active current 120 μA Standby current Operating voltage: VDD=2.7 V to 3.6 V Industrial temperature: –40°C to + 85°C? ? 14-pin Small Outline Integrated Circuit (SOIC) package compliant with Restriction of Hazardous Substances (RoHS) Underwriters Laboratories (UL) approved

Functional Overview

The FM31L276/FM31L278 devices integrate F-RAM memory for processor-based systems. Key features include non-volatile memory, real-time clock, low VDD reset, watchdog timer, non-volatile event counter, lockable 64-bit serial number area and general availability for power failure (NMI) interrupts or any other purposes. FM31L276/FM31L278 are 64 Kbit/256 Kbit non-volatile memories using advanced ferroelectric technology. A ferroelectric random access memory or F-RAM is non-volatile that performs read and write operations similar to RAM. This memory is truly non-volatile, not battery backed. It provides reliable data retention for 151 years while eliminating the complexity, overhead and system-level reliability issues caused by other non-volatile memory. The FM31L276/FM31L278 are capable of supporting 1014 read/write cycles, or 100 million times more write operations than EEPROM cycles. Real Time Clock (RTC) in BCD format. It can be permanently powered from an external backup voltage source, battery or capacitor. This timer uses a common external 32.768khz crystal and provides a calibration mode that allows software to adjust the timing accurately. Processor Companion includes commonly required CPU support functions. Supervisory functions include a reset output controlled by a low VDD condition or a watchdog-controlled signal timeout. When VDD falls below a programmable threshold and remains active after 100ms VDD is above the trigger point. Programmable watchdog timer from 100ms to 3s. But if enabled, it will assert the reset signal for 100ms if not restarted by the host before the timeout. The flag bit indicates the reset source. The comparator on the PFI connects the external input pin to the onboard 1.2V reference. This is useful for generating power failure interrupts (NMIs), but can be used for any purpose. This series also includes a programmable 64-bit serial number that can be locked so that it cannot be changed. In addition, it provides a battery backup event counter that tracks rising or falling edges detected on dedicated input pins.

Overview

The FM31L276/FM31L278 devices combine a serial non-volatile RAM with a real-time clock (RTC) and a processor companion. Companion is a highly integrated peripheral that includes a processor manager, comparator warning for early power down, a non-volatile event counter and a 64-bit serial number. The FM31L276/FM31L278 integrate these complementary functions under a common interface in a single package. Products are organized into two logical devices. The first is memory and the second is buddy, including all remaining functions. From the system's point of view on the serial bus are two separate devices with unique IDs. Memory is organized as independent non-volatile I2C memory using standard device ID values. Real time clock and access manager functions using separate I2C device IDs. This allows maintaining recently used memory addresses. Clock and supervisor functions are controlled by 25 Special Function Registers. The RTC and event counter circuits are maintained by the power supply on the VBAK pin, allowing them to be powered from the battery or back up capacitors when VDD falls below a set threshold. Each functional block is described below. Memory structure FM31L276/FM31L278 device memory size available 64 kbit/256 kbit. The device uses double bytes to address the memory portion of the chip. This makes device software compatible with standalone memory counterparts, but makes them compatible throughout the home. The storage array is logically organized as 8192×8 bits/32768×8 bits, using the industry standard I2C access interface. The memory uses F-RAM technology. Therefore, it can be thought of as RAM, and at the speed of the I2C bus, there is no delay for write operations. It also provides effective unlimited write endurance non-volatile memory technology. Describes that the I2C protocol memory array can be write protected by software. Two bits in the processor pairing area (WP1, WP0 in register 0Bh) control the protection settings. Depending on the settings, protected addresses cannot be written to and the I2C interface will not be able to acknowledge any data to the protected addresses. In particular, the function registers that contain these bits are described in detail

Processor Companion In addition to non-volatile RAM, the FM31L276/FM31L278 integrates a real-time clock and a highly integrated processor companion. The accompaniment includes a low VDD reset, a programmable watchdog timer, battery powered event counter, comparators for early power failure detection or other uses and a 64-bit serial number. Processing Supervisor The supervisor provides two basic functions of the host processor: power failure detection and a watchdog timer to evade software lockout conditions. The FM31L276/FM31L278 has a reset pin (RST) to drive the processor reset input during power failure, power up and software lockout. It is an open-drain output with a weak internal pull-up to VDD. This allows other reset sources to be connected or connected to the first pin. when? VDD is above the programmed trigger point and the RST output is pulled down to VDD. If VDD is below the reset trip point voltage level (VTP), the RST pin will be driven low. It will remain low until VDD drops too low for VRST level circuit operation. When VDD is higher than VTP again, RST continues to drive low for at least 100 ms (tRPU) to ensure a reliable VDD level. After tRPU is satisfied, the first pin will go back to a weak high state. When RST is asserted, the serial bus is locked for activity below VTP even though transactions occur as VDD. It will be done internally when VDD is above VTP. Table 1 below shows how bit VTP controls a low VDD reset. They are located in bits 1 and 0 of register 0Bh. The reset pin will drive a low voltage when VDD is below the selected VTP and the I2C interface and F-RAM array will be locked out. Note that the position of bit 1 is a don't care. Figure illustrates reset operation for low VDD.

The watchdog timer can also be used to drive the active reset signal. The watchdog is a free-running programmable timer. This timeout is software programmable from 100 ms to 3 seconds in 100 ms increments via a 5-bit nonvolatile register. All programmed to minimum values and to operating specifications with temperature. This watchdog has two additional control operations associated with it, the watchdog enable bit (WDE) and the timer restart bit (total weight) must both set the enable bit and the watchdog drive RST to activate the timeout. If a reset event occurs, the timer will automatically restart the pulse on the rising edge of reset. If WDE=0, the watchdog timer runs, but failure of the watchdog will not cause RST to be asserted low. The WTR flag will be set, indicating a watchdog failure. This setting is useful if the developer does not wish to drive. Note that setting the max timeout setting (11111b) disables the counter to save power. The second control is the nibble that restarts the timer to prevent resets. The timer should restart after changing the timeout value. The watchdog timeout value is located in register 0Ah, bits 4:0, and the watchdog enable is bit 7. The watchdog writes mode 1010b to the lower nibble of register 09h by restarting. Writing to this mode will also cause the timer to load with new timeout values. Writing other modes to this address will not affect its operation. Note that the watchdog timer is free running. When enabling it earlier, the user should restart the timer as described above. This ensures that the full timeout is set immediately after it is enabled. The watchdog is disabled when VDD is below VTP. The following table summarizes the watchdog bits. One block below is the diagram.

Note that the internal weak pull-up eliminates external components. Reset Flag In a reset condition, a flag bit will be set to indicate the source of the reset. A low VDD reset is indicated by the POR flag, register 09h bit 6. A watchdog reset is indicated by the WTR flag, register 09h bit 7. Note that the flags are set internally in response to a reset source, but they must be cleared by the user. When reading registers, if both of these occur after the last time the user cleared them. An early power-down comparator can provide early power-fail warning to the processor before VDD is out of specification. The comparator is used to create a power failure interrupt (NMI). This can be done by passing through a resistor divider. The application circuit is shown below.

Compare the voltage on the PFI input pin to the onboard 1.2v reference. When the PFI input voltage falls below this threshold, the comparator will drive the calibration/power factor output pin to a low state. Comparator has 100 mV (max) hysteresis to reduce noise sensitivity, only for rising PFI signals. Because of a falling PFI edge, there is no hysteresis. The comparator is a general purpose device and its application is not limited to the NMI function. The comparator is not integrated into the special function register unless it shares its output pins with the calibration output. When RTC calibration mode is invoked by setting the calibration bit (register 00h, bit 2), the CAL/PFO output pin will use a 512 Hz square wave and the comparator will be ignored. Since most users only invoke calibration mode during production, this pair uses comparators. Note: The maximum voltage at the comparator input PFI is limited to 3.75 V under normal operating conditions. Event Counters The FM31L276/FM31L278 provide the user with two battery powered event counters. Input pins CNT1 and CNT2 for programmable edge detectors. A 16-bit counter per clock. When an edge occurs, the counters will increment their respective registers. Counter 1 is located in registers 0Dh and 0Eh, and counter 2 is located in registers 0Fh and 10h. These register values can be read when VDD is higher than VTP, and they will increment as long as a valid VBAK supply is provided. To read, set bits 3 to 1 of RC bit register 0Ch. This is a snapshot counter byte for four photos, allowing a stable value during reading even if the count occurs. Registers can be used to allow counters to be cleared or initialized by the system. Counting is blocked during write operations. The two counters can be cascaded by setting CC to create a single 32-bit counter control bit (register 0Ch, bit 2). When cascaded, the CNT1 input will cause the counter to increment. CNT2 is not used in this mode and should be connected to ground.

The control bits for the event count are located in register 0Ch. Counter 1 polarity is bit C1P, bit 0; counter 2 polarity is bit C2P, bit 1; cascade control is CC, bit 2; read counter bit is RC, bit 3. The polarity bit must be set before setting the counter value. If the polarity bit is changed, the counter may inadvertently increment. If countersink pins are not used, tie them to the ground. The serial number provides the memory location for writing the 64-bit serial number. It is a writable block of non-volatile memory that can be accessed by the user once the serial number is set. The 8-byte data and lock bits are all companions accessed through the processor's device ID. So the serial number area is separate from the memory array. The serial number register can be written an unlimited number of times, so these locations are general purpose memory. However, once the lock bit is set, the value cannot be changed, nor can the lock be removed. Once locked the serial number register can still be used by the system. The serial number is located in registers 11h to 18h. The lock bit is SNL (Register 0Bh, Bit 7). Setting the SNL bit to '1' disables writing to the serial number register, and the SNL bit cannot be illuminated. Real Time Clock Operation A real time clock (RTC) is a timekeeping device that can be permanently powered by a battery or capacitor. It provides a software calibration function that allows high accuracy. RTC consists of oscillators, clock dividers and registers to form a user access system. It will have a 32.768khz time base, providing a minimum resolution of seconds (1 Hz). Static registers provide the user with time values. It includes registers for seconds, minutes, hours, day of the week, date, month and year. The block diagram (Figure 7) illustrates the RTC functionality. The user registers are synchronized with the timer core using the R and W bits in register 00h described below. Changing the R bit from "0" to "1" goes from the core into a holding register that can be read by the user. If a timer update is pending while R is set, the core will do the update before loading the user registers. The register is frozen until the R bit is cleared to '0'. R is used to read the time. Setting the W bit to '1' locks the user registers. Clearing to '0' causes the value in the user register to be loaded into the timing core. The W bit is used to write a new time value. The user should ensure that invalid values such as FFh are not loaded into the timing registers. Updates to timing cores are made continuously unless locked.

The backup power real time clock/calendar is permanently powered. The VDD pin will drop when the main system is powered off. When VDD is less than 2.5 V, the RTC (and event counter) will switch to the backup power supply on VBAK. The clock operates at very low current to maximize. battery or capacitor life. However, in conjunction with the clock function of F-RAM memory, data is not lost regardless of the backup power source. IBAK current varies with temperature and voltage (see DC Electrical Characteristics table). IBAK is shown as a function of VBAK. These curves are useful for calculating backup times when capacitors are used as VBAK sources.

The minimum VBAK voltage varies linearly with temperature. This user can expect a minimum VBAK voltage of 1.23 V at +85°C and 1.90 V at -40°C. Test limit is 1.55 V at +25°C. Note: Minimum VBAK voltages are characterized by -40°C and +85°C, but are not 100% tested.

Trickle Charger To facilitate capacitor backup, the VBAK pin can optionally provide a trickle charge current. When the VBC bit (Register 0Bh, Bit 2) is set to '1', the VBAK pin will source approximately 80µA until VBAK. to VDD. This charges the capacitor to VDD without the need for an external diode and resistor charger. Charge mode is quickly enabled by the FC bit (register 0Bh, bit 5). In this mode the trickle charger current is set to about 1mA, allowing a large backup capacitor to charge faster. When not using a battery, the VBAK pin should be tied to VSS. Make sure to turn off the trickle charger (VBC='0'), otherwise the charger current will be shunted from VDD to ground. Note: Systems using Lithium batteries should clear the VBC bit to '0' to prevent battery charging. The VBAK circuit includes an internal 1K series resistor as a safety element. The trickle charger is UL certified. Calibration When the calibration bit in register 00h is set to '1', the clock enters calibration mode. In calibration mode, the calibration/power factor output pins are temporarily unavailable for the calibration function and the power-fail output is dedicated. The counter is digitally corrected by applying the frequency based error. In this mode, the CAL/PFO pin drives a square wave at 512 Hz (nominal). Any measured deviation from 512 Hz becomes a timing error. The user converts the measured error and writes the appropriate correction value to the calibration register. The correction factors are listed in the table below. A positive ppm error requires a negative adjustment to remove the pulse. Negative ppm errors require correction of positive incremental pulses. Positive ppm adjustments have the CAL (sign) bit set to "1", while negative ppm adjustments have CAL set to "0". After calibration, the clock will have the maximum value. The monthly error when calibrated is ±2.17 ppm or ±0.09 minutes of temperature. Calibration settings are stored in F-RAM, so there is no loss of backup source failure. It is in register 01h with bits CAL (4:0). Only when the CAL bit is set to "1". To exit calibration mode, the user must clear the calibration bit to '0'. When the CAL bit is "0", the CAL/PFO pin will resume the power-down output function.

Crystal Oscillators Crystal oscillators are designed to use a 6 pF/12.5 pF crystal and require no external components such as loading capacitors. The FM31L276/FM31L278 devices have built-in load capacitors optimized for 6 pF crystals, but work well for 12.5pf crystals. Neither crystal nor additional external load capacitors are recommended. If a 32.768 kHz crystal is not used, an external oscillator can be connected to the FM31L276/FM31L278. Apply the oscillator to the X1 pin. Its high and low voltage levels can be driven strip by strip or with amplitudes as low as about 500 mV p-p to ensure proper operation, a DC bias must be applied on the X2 pin. It should center the pin between the high and low of X1. This can be achieved with a voltage divider.

In this example, R1 and R2 are chosen so that the X2 voltage is centered on the X1 oscillator drive level. If you are willing to avoid DC current, you can choose to drive a reverse clock inverter with an external clock and X2, using CMOS.

Layout Recommendations X1 and X2 transistor pins using high impedance circuits connected to these pins of the oscillator will be disrupted by noise or additional loading. To reduce RTC clock error switching noise from the signal, a guard ring must be placed around these pads to ground. The SDA and SCL traces should be drawn from the X1/X2 pads. The X1 and X2 trace lengths should be less than 5 mm. The best ground plane to use is the backside or inner board layer. See layout example. Red is the top layer and green is the bottom layer.