feature

205 MSPS maximum slew rate; 500 MHz programmable analog bandwidth; 0.5 V to 1.0 V analog input range; less than 450 ps pp PLL clock jitter @ 205 MSPS; 3.3V power supply; :1 analog input multiplexer; 4:2:2 output format mode; mid-scale clamp; power down mode; low power: <1W, typical power, 205 MSPS.

application

RGB graphics processing; LCD monitors and projectors; plasma displays; scan converters; microdisplays; digital television.

General Instructions

The AD9888 is a complete 8-bit 205 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 205 MSPS code rate capability and 500 MHz full-power analog bandwidth support resolutions up to UXGA ( 1600 x 1200 at 75 Hz).

For ease of design and to minimize cost, the AD9888 is a fully integrated flat panel display interface solution. The AD9888 includes an analog interface and a 205 MHz triple ADC, internal 1.25 V reference, PLL to generate pixel clock from HSYNC and COAST, mesoscale clamp, programmable gain, offset and clamp control. Users only provide 3.3V power, analog input, high-speed sync and coasting signals.

The tri-state CMOS output can be powered from 2.5v to 3.3v.

The on-chip PLL of the AD9888 generates the pixel clock from the HSYNC and COAST inputs. The pixel clock output frequency ranges from 10 MHz to 205 MHz. PLL clock jitter is typically less than 450 ps pp at 205 MSPS. When a coast signal is present, the PLL maintains its output frequency without HSYNC. Provides sampling phase adjustment. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled and an external clock input is provided as the pixel clock. The AD9888 also provides full synchronization processing for composite synchronization and synchronization on green applications.

The clamp signal is generated internally or can be provided by the user through the clamp input pin. The interface is fully programmable via a 2-wire serial interface.

Fabricated on an advanced CMOS process, the AD9888 is housed in a space-saving 128-lead MQFP surface mount plastic package and specified over the 0°C to 70°C temperature range.

Design Guidelines

General Instructions

The AD9888 is a fully integrated solution for capturing and digitizing analog RGB signals for display on a flat panel display or projector. This circuit is ideal for providing a computer interface for high-definition television displays or high-performance video scan converters.

Implemented in a high-performance CMOS process, the interface can capture signals at pixel rates up to 205 MHz and can capture signals up to 340 MHz using alternative pixel sampling modes.

The AD9888 includes all necessary input buffering, signal DC recovery (clamping), offset and gain (brightness and contrast) adjustments, pixel clock generation, sampling phase control, and output data formatting. All controls are programmable via a 2-wire serial interface. The full integration of these sensitive analog functions enables straightforward system design with low sensitivity to physical and electrical environments.

The typical power consumption of the unit is only 650 MW, and the operating temperature range is 0°C to 70°C, with no special environmental considerations.

input signal processing

The AD9888 has six high-impedance analog input pins for the red, green, and blue channels. They will accommodate signals from 0.5 V to 1.0 V pp.

The signal is usually brought to the interface board via a DVI-I connector, a 15-pin D connector, or a BNC connector. The AD9888 should be placed as close to the input header as possible. Signals should be routed to the IC input pins through matched impedance traces (typically 75Ω).

At this point, the signal should be resistor terminated (to the signal ground return) and capacitively coupled to the AD9888 input through a 47 nF capacitor. These capacitors form part of the DC recovery circuit.

In an ideal world with perfectly matched impedances, the widest possible signal bandwidth would yield the best performance. The ultra-wideband input of the AD9888 (500 MHz) continuously tracks the input signal as it moves from one pixel level to the next and digitizes the pixel over long flat pixel times. In many systems, however, there are mismatches, reflections, and noise, which can cause excessive ringing and distortion of the input waveform. This makes it more difficult to build a sampling stage that provides good image quality. The AD9888 can digitize graphic signals over a very wide frequency range (10 MHz to 205 MHz). Often a characteristic that is beneficial at one frequency is detrimental at another. Analog bandwidth is one such feature. For UXGA resolutions (up to 205mhz), very high analog bandwidth is required due to the fast input signal slew rate. For VGA and lower resolutions (down to 12.5 MHz), a very high bandwidth is not desirable because it allows too much noise to pass through. To accommodate these changing needs, the AD9888 includes variable analog bandwidth control. Four settings are available (75MHz, 150MHz, 300MHz, and 500MHz), allowing the analog bandwidth to match the resolution of the input graphics signal.

Synchronous processing

The AD9888 contains circuitry that enables it to accept composite sync inputs, such as sync on green or tri-level sync in digital television signals. The Sync Slicers and Sync Delimiters sections provide a complete description of the sync processing functionality.

Hsync, Vsync input

The interface also uses a horizontal sync signal to generate the pixel clock and clamp timing. The AD9888 can be operated without Hsync (with external clock, external clamp, and single-port output mode) applied, but many features of the chip will not be available; Hsync is recommended. This can be a sync signal directly from the graphics source, or a preprocessed TTL or CMOS level signal.

The Hsync input includes a Schmitt trigger buffer for noise immunity and long rise time signals. In a typical PC-based graphics system, the sync signal is just a TTL-level driver, supplied with an unshielded wire in the monitor cable. Therefore, termination is not required or desired.

Serial control port

The serial control port is designed for 3.3V logic. If there is a 5V driver on the bus, these pins should be protected with 150Ω series resistors placed between the pull-up resistors and the input pins.

output signal processing

The digital outputs are designed and specified to operate from a 3.3V supply (VDD). They also work with VDD as low as 2.5V for compatibility with other 2.5V logic.

clamp

RGB clamping

To properly digitize the input signal, the DC offset at the input must be adjusted to fit the operating range of the onboard A/D converter.

Most graphics systems produce an RGB signal with black at ground and white at about 0.75 V. However, if the sync signal is embedded in the pattern, the sync tip is often at ground, black at 300 mV; white at about 1 V. Some common RGB line amplifier boxes use emitter follower buffers to separate the signal and increase drive capability. This introduces 700 mV of DC offset to the signal, which the AD9888 must remove for proper capture.

The key to clamping is to identify the part (time) of the signal when the graphics system is known to produce black. An offset is then introduced and the A/D converter produces a black output (code 00H) when a known black input is present. Then, when other signal levels are processed, the offset remains in place and the entire signal is shifted to remove the offset error.

In most graphics systems, black is transmitted between the active video lines. Going back to the cathode ray tube display, when the electron beam finishes writing the horizontal lines on the screen (right side), the electron beam is deflected quickly to the left side of the screen (called horizontal retrace) and provides a black signal to prevent the electron beam from interfering with the image .

In systems with embedded sync, a signal darker than the black signal (Hsync) is briefly generated, signaling the CRT to start backtracking. For obvious reasons, it is important to avoid gripping the tip of the Hsync. Fortunately, there's almost always a period after Hsync called the back porch, which provides a good black reference here. Clamping should be done at this point.

Simply use the clamp pin at the appropriate time (external clamp = 1) to determine clamping timing. The polarity of this signal is set by the clamp polarity (Register 0FH, Bit 6).

A simpler clamp timing method is to use the AD9888 internal clamp timing generator. The clamp placement register is programmed with the number of pixels that should pass after the trailing edge of HSYNC before clamping begins. The second register (Clamp Duration, Register 06H) sets the duration of the clamp. These are all 8-bit values, providing considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of the Hsync because the back porch (black reference) always follows the Hsync, although the Hsync duration varies widely. A good starting point for establishing a clamp is to set the clamp to 08H (give the graphics signal 8 pixel periods to settle after syncing) and set the clamp duration to 14H (give 20 pixels to the clamp cycle to re-establish the black reference).

Clamping is done by placing an appropriate charge on the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there will be significant amplitude changes within the horizon time (between clamping intervals). If the capacitor is too large, the clamp will take a long time to recover from large changes in the input signal offset. The recommended value (47nf) results in recovery from a 100 mV step error to within 1/2 LSB of 10 lines on a 60Hz SXGA signal with a clamp duration of 20 pixel periods.

YUV clamping

YUV graphics signals are slightly different from RGB signals in that the dc reference level (the black level in an RGB signal) can be at the midpoint of the video signal instead of the bottom. For these signals, it may be necessary to clamp to the mid-scale range of the A/D converter range (80H) rather than the bottom of the A/D converter range (00H).

The clamp can be set to midscale instead of ground by setting the clamp select bits in the serial bus register. The red and blue channels each have their own select bits so that they can be individually clamped to midscale or ground. The clamp control is located in bits 1 and 2 of register 10H. Each A/D converter clips a separately provided mid-scale reference voltage on the RMIDSCV and BMIDSCV pins. These two pins should be bypassed to ground with a 0.1µF capacitor (even if midscale clamping is not required).

Gain and offset controls

The AD9888 accommodates input signals with an input range of 0.5 V to 1.0 V full scale. The full-scale range is set in three 8-bit registers (red gain, green gain, and blue gain; registers 08H, 09H, and 10H, respectively). Note that increasing the gain setting will result in a reduction in the contrast of the image.

The offset control shifts the entire input range, resulting in changes in image brightness. Three 7-bit registers (red offset, green offset, blue offset; registers 0BH, 0CH, and 0DH) provide independent settings for each channel.

The offset control provides an adjustment range of ±63 LSB. This range is tied to the full-scale range, so if the input range is doubled (from 0.5 V to 1.0 V), the offset step is also doubled (from 2 mV/step to 4 mV/step).

Figure 2 illustrates the interaction of gain and offset control. The size of the LSB in the offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. If the offset setting is close to midscale, the change is minimal. When changing the offset, the full-scale range is not affected, but the offset for the full-scale level is the same as the offset for the zero-scale level.

Sync on Green

The sync on green input operates in two steps. First, it sets the baseline clamp level for a negative peak detector. Second, it sets the sync trigger level (nominally 150mV above the negative peak). The exact trigger level is variable and can be programmed via register 11H. The green sync input must be AC coupled to the green analog input through its own capacitor, as shown in Figure 3. The value of the capacitor must be 1 nF±20%. If sync on green is not used, this connection is not required and the SOGIN pin should be left unconnected. (Note: Sync on Green is always negative.) See the Sync Processing section for more details.

clock generation

A phase-locked loop (PLL) is used to generate the pixel clock. The Hsync input provides the reference frequency for the PLL. A voltage controlled oscillator (VCO) produces a higher pixel clock frequency. This pixel clock is divided by the PLL divide value (registers 01H and 02H) and compared to the Hsync input. Any errors are used to shift the VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important factor in providing the sharpest and most stable images. Within each pixel time, there is a period in which the signal rotates from the old pixel amplitude and settles at its new value. Then for a while, when the input voltage stabilizes, the signal must transition to a new value (Figure 4). The ratio of slew time to settling time is a function of graphics DAC bandwidth and transmission system bandwidth (cable and termination). It is also a function of the overall pixel rate. Obviously, if the dynamics of the system remain the same, then the slew and settling times are also fixed. This time must be subtracted from the total pixel period to preserve stable periods. At higher pixel frequencies, the overall cycle time is shorter, as is the stabilization pixel time.

Any jitter in the clock reduces the accuracy of determining the sample time and must also be subtracted from the stable pixel time.

In the design of the AD9888's clock generation circuit, considerable care has been taken to minimize jitter. As shown in Figure 5, the clock jitter of the AD9888 is less than 9% of the total pixel time in all modes of operation, making the reduction in effective sampling time due to jitter negligible.

PLL characteristics are determined by loop filter design, PLL charge pump current, and VCO range settings. The design of the loop filter is shown in Figure 6. Table 4 lists the recommended settings for the VCO range and charge pump current for the VESA standard display mode.

Four programmable registers are provided to optimize the performance of the PLL. These registers are:

1. 12-bit divisor register. The input sync frequency range is 15 kHz to 110 kHz. The PLL multiplies the frequency of the Hsync signal to produce a pixel clock frequency in the range of 10mhz to 205mhz. The divisor register controls the exact multiplication factor. This register can be set to any value between 221 and 4095. (The actual division ratio used is the programmed division ratio plus 1.)

2. 2-bit VCO range register. In order to reduce the sensitivity of the output frequency to the noise of the control signal, the operating frequency range of the VCO is divided into four overlapping regions. The VCO range register sets this operating range. Because there are only four possible regions, only the two least significant bits of the VCO range register are used. The frequency ranges of the lowest and highest regions are shown in Table II.

3. 3-bit charge pump current register. This reduces the current driving the low-pass loop filter changes. Table 3 lists the possible current values.

4, 5-bit phase adjustment register. The phase of the generated sampling clock can be shifted to locate the optimal sampling point within the clock cycle. The phase adjustment register provides 32 phase shift steps of 11.25° each. The Hsync signal with the same phase shift is available through the hsout pin. Phase adjustment is still available if the pixel clock is provided externally.

The COAST pin is used to allow the PLL to continue operating at the same frequency without an incoming Hsync signal. This can be used during vertical sync or any other time when the Hsync signal is not available. The polarity of the coast signal can be set through the coast polarity register. In addition, the polarity of the Hsync signal can be set through the Hsync polarity register.

Alternate pixel sampling mode

A logic 1 input on Clock Inversion (CKINV, Pin 29) inverts the nominal ADC clock. CKINV can be toggled between frames to implement alternate pixel sampling modes. This allows for higher effective image resolution at lower pixel rates but lower frame rates.

In a frame, only even-numbered pixels are digitized. On subsequent frames, odd pixels are sampled. The complete image can be reconstructed by reconstructing the entire frame in the graphics controller. This is similar to the interlacing process used in broadcast television systems, but the interlacing is vertical instead of horizontal. Frame data is still rendered to the display at the full desired refresh rate (usually 60hz), so no flickering artifacts are added.

opportunity

The following timing diagrams show the operation of the AD9888 analog interface in all clock modes. When the leading edge of Hsync is sent to the "A" data port, this part establishes timing by sending the samples corresponding to the digitized pixels. In dual channel mode, the next sample is the "B" port. Future samples alternate between "A" and "B" data ports. In single channel mode, data is only sent to the "A" data port, and the "B" port is in a high impedance state.

Generates the output data clock signal so that its rising edge always occurs between "A" data transitions and can be used to externally lock the output data.

Sync timing

Horizontal synchronization is handled in the AD9888 to remove the ambiguity of the leading edge timing of the pixel clock and data relative to the phase delay.

The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase relative to Hsync can be adjusted through a full 360° in 32 steps via the phase adjustment register (to optimize pixel sampling time). Display systems use Hsync to adjust memory and display write cycles, so it is important to maintain a stable timing relationship between the Hsync output (HSOUT) and the data clock (DATACK).

There are three cases for horizontal synchronization of the AD9888. First, determine the polarity of the Hsync input to have a known output polarity. Known output polarity can be programmed as active high or active low (register 0EH, bit 5). Second, HSOUT is aligned with the packet and data output.

Third, the duration of HSOUT (pixel clock) is set via register 07H. HSOUT is the sync signal that should be used to drive the rest of the display system.

taxi time

In most computer systems, the Hsync signal is provided continuously over a dedicated line. In these systems, coast inputs and functions are unnecessary and should not be used.

However, in some systems, Hsync is disturbed during vertical synchronization (Vsync). In some cases, the Hsync pulse disappears. In other systems, such as those employing a composite sync (Csync) signal or embedded sync on green (SOG), Hsync includes equalization pulses or other distortions during Vsync. It is important to ignore these distortions in order to avoid disturbing the clock generator during Vsync. If the pixel clock PLL sees an extraneous pulse, it will try to lock to this new frequency and change the frequency at the end of the Vsync period. Then it takes a few lines of correct Hsync timing to recover at the start of a new frame, causing the image to "tear" at the top of the display.

Coast input is provided to eliminate this problem. It is an asynchronous input that disables the PLL input and allows the clock to run freely at its current frequency. The PLL can run several lines freely without significant frequency drift.

2-Wire Serial Control Register Detailed Chip Identification

007-0 Chip revision

An 8-bit register representing the silicon version. Version 0=0000 0000, Version 1=0000 0001.

Crossover Control

01 7-0 PLL divided by MSBs

The 8 most significant bits of the 12-bit phase-locked loop

Divide by the proportional PLLDIV. (The operating split ratio is PLLDIV+1.)

The PLL derives the master clock from the incoming Hsync signal. The master clock frequency is then divided by the integer value so that the output is locked to Hsync. The PLLDIV value determines the number of pixels per line (pixels plus horizontal blanking overhead). This is typically 20% to 30% more than the number of active pixels in the display.

The 12-bit value of the PLL divider supports division ratios from 2 to 4095. The higher the value loaded in this register, the higher the resulting clock frequency relative to the fixed Hsync frequency.

VESA has established standard timing specifications that will help determine the value of PLLDIV as a function of horizontal and vertical display resolution and frame rate.

However, many computer systems do not fully comply with these recommendations and these numbers should only be used as a guide. The display system manufacturer should provide a means to automatically or manually optimize the PLLDIV. An incorrectly set PLLDIV will often produce one or more vertical noise bars on the display. The larger the error, the higher the number of bars produced.

The power-on default for PLLDIV is 1693 (PLLDIVM=69H, PLLDIVL=DxH).

The AD9888 only updates the full divide ratio when the LSB is changed. Writing to this register alone will not trigger an update.

02 7-4 PLL division ratio LSBs

The 12-bit PLL divides the four least significant bits of PLLDIV. The operating split ratio is PLLDIV+1.

The power-on default for PLLDIV is 1693 (PLLDIVM=69H, PLLDIVL=DxH).

The AD9888 only updates the full divide ratio when writing to this register.

Clock Generator Control

03 7-6 VCO range selection

Two bits that determine the operating range of the clock generator.

VCORNGE must be set to correspond to the desired operating frequency (input pixel rate).

Phase-locked loops have the best jitter performance at high frequencies. For this reason, in order to output a low pixel rate and still get good jitter performance, the PLL actually operates at a higher frequency, but then divides the clock rate by . Table VI shows the pixel rates for each VCO range setting. The PLL output divisor is automatically selected by the VCO range setting.

The power-up default is 01.

03 5-3 Charge Pump Current

Three bits of current that drive the loop filter are established in the clock generator.

The current must be set to correspond to the desired operating frequency (input pixel rate).

The power-up default is CURRENT=001.

04 7-3 Clock Phase Adjustment

A 5-bit value that adjusts the sampling phase in 32 steps within one pixel time. Each step represents an 11.25° displacement of the sampling phase.

The power-up default is 16.

Clamp timing

05 7-0 Fixture Placement

An 8-bit register that sets the position of an internally generated clamp.

When the external clamp control bit is set to 0, the clamp signal is generated internally at the position determined by the clamp placement and for the duration set by the clamp duration. Begin clamping (clamp placement) the pixel period after the trailing edge of Hsync. The clamping position can be programmed to any value up to 255, except 0.

The clamp should be placed during the time period when the input signal exhibits a stable black level reference, usually the back porch cycle between Hsync and the picture.

This register is ignored when the external clamp control bit is set to 1.

06 7-0 Clamping Duration

An 8-bit register that sets the duration of an internally generated clamp.

When the external clamp control bit is set to 0, the clamp signal is generated internally at the position determined by the clamp placement and for the duration set by the clamp duration. Clamping begins (clamp placement) pixel periods after the trailing edge of Hsync and continues (clamp duration) pixel periods. The clamp duration can be programmed to any value between 1 and 255. Value 0 is not supported.

For best results, the clamp duration should be set to include most of the black reference signal time after the trailing edge of the Hsync signal. Insufficient clamping time produces brightness changes at the top of the screen and slow recovery from large changes in average picture level (APL) or brightness.

This register is ignored when the external clamp control bit is set to 1.

Sync pulse width

07 7-0 Synchronous output pulse width

An 8-bit register that sets the duration of the Hsync output pulse.

The leading edge of the Hsync output is triggered by an internally generated phase-adjusted PLL feedback clock. The AD9888 then counts the number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted.

input gain

08 7-0 Red channel gain adjustment

An 8-bit word that sets the gain of the red channel. The AD9888 accommodates input signals with a full-scale range between 0.5 V and 1.0 V pp. Setting REDGAIN to 255 corresponds to an input range of 1.0 V. Setting REDGAIN to 0 establishes an input range of 0.5 V. Note that increasing REDGAIN results in an image with less contrast (the input signal uses fewer available converter codes). See Figure 2.

09 7-0 Green channel gain adjustment

An 8-bit word that sets the green channel gain. See Red Gain (08).

0A 7-0 Blue channel gain adjustment

An 8-bit word that sets the gain of the blue channel. See Red Gain (08).

input offset

0B

7-1 Red Channel Offset Adjustment

A 7-bit offset binary word that sets the DC offset for the red channel. One LSB of offset adjustment is equal to one LSB change in ADC offset.

Therefore, the absolute magnitude of the offset adjustment varies with the channel gain. A nominal setting of 63 would cause the channel to nominally clamp the back porch (during the clamping interval) to code 00. An offset setting of 127 will cause the channel to clamp to code 64 of the ADC. Offset is set to 0 clamp to code –63 (offset from bottom of range). Increasing the value of Red Offset reduces the brightness of the channel.

0 degree

7-1 Green Channel Offset Adjustment

A 7-bit offset binary word that sets the DC offset for the green channel. See REDOFST (0B).

0D

7-1 Blue Channel Offset Adjustment

A 7-bit offset binary word that sets the DC offset of the blue channel. See REDOFST (0B).

0E

7 Sync Input Polarity Override

This register is used to override the internal circuitry that determines the polarity of the Hsync signal entering the phase locked loop

The default value for Hsync polarity override is 0 (polarity is determined by the chip).

0E 6 HSPOL Hsync input polarity

A bit that must be set to indicate the polarity of the Hsync signal applied to the PLL Hsync input.

Active low indicates that the leading edge of the Hsync pulse is negative. All timings are based on the leading edge of Hsync, the falling edge. A rising edge has no effect.

Active high indicates that the leading edge of the Hsync pulse is positive. This means that the timing will be based on the leading edge of Hsync, which is now the rising edge.

If this bit is not set correctly, the device will operate, but the internally generated clamp established by clamp placement (register 05H) will not place as expected, which may produce clamp errors.

The power-on default is HSPOL=1.

0E 5 Hsync output polarity

A bit that determines the polarity of the Hsync output and SOG output. Table X shows the effect of this option. SYNC represents the logic state of the sync pulse.

The default setting for this register is 0.

0E 4 Active Hsync Override

This bit is used to override automatic Hsync selection. To override, set this bit to logic 1. On rewrite, the active Hsync is set via Bit 3 in this register.

The default value of this register is 0.

0E 3 Active Hsync Select

This bit is used in two situations. It is used to select the active Hsync when the override bit (bit 4) is set. Alternatively, it is used to determine the active Hsync when not overriding but detecting both Hsyncs at the same time.

The default value of this register is 0.

0E 2 Vsync output inverted

Bit to invert the polarity of the vertical sync output. Table XIII shows the effect of this choice.

The default setting for this register is 0.

0E 1 Active Vsync Override

This bit is used to override automatic Vsync selection. To override, set this bit to logic 1. When rewritten, the active interface is set via Bit 0 in this register.

The default value of this register is 0.

0E 0 Active Vsync Select

This bit is used to select the active Vsync when the overtravel bit (bit 1) is set.

The default value of this register is 0.

0F 7 clamp input signal source

A bit that determines the source of the clamp timing.

0 enables the clamp timing circuit controlled by clamp and clamp duration. The clamping position and duration are calculated from the trailing edge of Hsync.

A 1 Enable external clamp input pin. When the clamp signal is activated, the three channels are clamped. The polarity of the clamp is determined by the Clamp Polarity bit (Register 0FH, Bit 6).

The power-up default is external clamp=0.

0F 6 clamp input signal polarity

A bit that determines the polarity of an externally supplied clamp signal.

A logic 1 means that the circuit will clamp when the clamp is low and pass the signal to the ADC when the clamp is high.

A logic 0 means that the circuit will clamp when the clamp is high and pass the signal to the ADC when the clamp is low.

The power-up default is Clamp Polarity=1.

0F 5 Shore Selection

This bit is used to select the active coast source. Choice of coast input pin or Vsync. If Vsync is selected, an additional decision needs to be made to use the Vsync input pin or the output of the sync splitter (register 0EH, bits 1, 0).

The default value of this register is 0.

0F 4 Coast Input Polarity Override

This register is used to override the internal circuitry that determines the polarity of the coast signal entering the PLL.

The default value for Coastal Polarity Override is 0.

0F 3 Coasting Input Polarity

A bit that indicates the polarity of the coast signal applied to the coast input of the PLL.

Active low means that when COAST is low, the clock generator will ignore the Hsync input and continue to run at the same nominal frequency until COAST is high.

Active high means that the clock generator will ignore the Hsync input when COAST is high and continue to run at the same nominal frequency until COAST goes low.

This feature needs to be used in conjunction with the Coast Polarity Override bit (bit 4).

The power-on default is CSTPOL=1.

0F 2 Search Mode Override

This bit is used to enable or disable low power modes. A low power mode (seek mode) occurs when there is no signal on any of the sync inputs.

The default value of this register is 1.

0F 1 password

This bit is used to put the chip in power down mode. In this mode, the power consumption of the chip is reduced to a fraction of the typical power consumption (see the electrical characteristics table for specific power consumption). When power-down, HSOUT, VSOUT, DATACK, DATACK and all 48 data outputs go into a high impedance state. (Note: The SOGOUT output is not input high impedance.) Circuit blocks that remain active during power-down include voltage reference, sync processing, sync detection, and serial registers. These modules facilitate fast start-up from a power-down state.

The default value of this register is 1.

10 7-3 Green Slicer Sync Threshold

This register allows adjustment of the comparator threshold for the Syncon Green slicer. This register is adjusted in 10 mV steps, with a minimum setting equal to 10 mV and a maximum setting equal to 330 mV.

The default setting is 15, which corresponds to a threshold of 0.16 V.

102 red clamp options

A bit that determines whether the red channel is fixed on the ground or on the midscale. For RGB video, all three channels are referenced to ground. For YcbCr (or YUV), the Y channel is referenced to ground, but the CbCr channel is referenced to the midscale. Clamping to mid-scale actually clamps to pin 9.

The default setting for this register is 0.

10 1 blue clamp selection

A bit that determines whether the blue channel is fixed on the ground or on the midscale. Clamping to mid-scale actually clamps to pin 24 .

The default setting for this register is 0.

11 7:0 Sync Separator Threshold

This register is used to set the response of the sync delimiter. It sets how many internal 5MHz clock cycles the sync separator must count before switching high or low. It works like a low pass filter, ignoring the Hsync pulses to extract the Vsync signal. This register should be set larger than the maximum number of Hsync pulsewidths.

NOTE: The sync splitter threshold uses an internal dedicated clock with a frequency of approximately 5 MHz.

The default value of this register is 32.

12 7-0 Pre-Coast

This register allows the coast signal to be applied before the Vsync signal. This is necessary in the presence of pre-equalization pulses. The step size of this control is one Hsync cycle.

The default value is 0.

13 7-0 Back Coast

This register allows the coast signal to be applied after the Vsync signal. This is necessary in the presence of post-equalization pulses. The step size of this control is one Hsync cycle.

The default value is 0.

14 7 Sync detection

This bit is used to indicate when activity is detected on the selected Hsync input pin. If HSYNC remains high or low, no activity is detected.

The synchronization processing block diagram shows where this functionality is implemented.

14 6 AHS – Active Sync

This bit indicates which Hsync input source is being used by the PLL (green for Hsync input or sync). Bit 7 and Bit 1 in this register determine which source is used. If both Hsync and SOG are detected, the user can determine which has priority via bit 3 in register 0EH. The user can override this function via bit 4 in register 0EH. If the override bit is set to logic 1, the bit will be forced to whatever state of Bit 3 in register 0EH.

AHS=0 means use HSYNC pin input for HSYNC.

AHS=1 means use the SOG pin input of HSYNC.

The rewrite bit is in register 0EH, bit 4.

14 5 Hsync input polarity status detected

This bit reports the status of the HSYNC input polarity detection circuit. It can be used to determine the polarity of the HSYNC input. The location of the detection circuit is shown in the synchronization process block diagram (Figure 25).

14 4 Vertical sync detection

This bit is used to indicate when activity is detected on the selected Vsync input pin. If Vsync remains high or low, no activity is detected.

The synchronization processing block diagram (Figure 25) shows where this function is implemented.

14 3 AVS – Active Vsync

This bit indicates which Vsync source is being used; either the Vsync input or the output of the sync separator. Bit 4 of this register determines which is active. If both Vsync and SOG are detected, the user can determine which has priority via bit 0 in register 0EH. The user can override this function via bit 1 in register 0EH. If the override bit is set to logic 1, the bit will be forced to whatever state of Bit 0 in Register 0EH.

AVS=1 means synchronization separator.

AVS=0 means Vsync input.

The rewrite bit is in register 0Eh, bit 1.

14 2 Vsync output polarity status detected

This bit reports the status of the Vsync output polarity detection circuit. It can be used to determine the polarity of the Vsync input. The location of the detection circuit is shown in the synchronization process block diagram (Figure 25).

14 1 Sync on Green Detection

This bit is used to indicate when sync activity is detected on the selected sync on the green input.

The synchronization processing block diagram (Figure 25) shows where this function is implemented.

14 0 Coastal polarity status detected

This bit reports the status of the coasting input polarity detection circuit. It can be used to determine the polarity of the coast input. The location of the detection circuit is shown in Figure 25.

Mode Control 1

15 7-channel mode

A bit that determines whether all pixels are presented to a single port (A), or bits that demultiplex alternate pixels to ports A and B.

When DEMUX=0, the Port B output is in a high impedance state. The maximum data rate in single port mode is 110 MHz. The timing diagrams starting with Figure 13 show the effect of this option.

The power-on default value is 1.

15 6 output mode

Determine if all pixels are rendered to

Port A and Port B operate simultaneously on the rising edge of each second packet, or alternate on successive packet rising edges.

When in single-port mode (DEMUX=0), this bit is ignored. The timing diagram (Figure 17) shows the effect of this option.

The power-on default is parallel=1.

15 5 output port phase

One bit to determine whether even or odd pixels enter port A.

In normal operation (output phase = 0), when operating in dual port output mode (DEMUX = 1), the first sample after the Hsync leading edge appears on port A. Every subsequent odd sample appears at port A. All even samples go to port B.

When OUTPHASE=1, the ports are reversed and the first sample goes to port B.

When DEMUX=0, this bit is ignored because data always comes from port A only.

15 4 4:2:2 output mode selection

Configure the bits of the output data in 4:2:2 mode. This mode can be used to reduce the number of data lines from 24 to 16 for applications using YUV, YCbCr or YPbPr graphics signals. The timing diagram for this mode is shown in Figure 12. Recommended input and output configurations are shown in Table XXXVII. In 4:2:2 mode, the red and blue channels can be interchanged to help meet board layout or timing requirements, but the green channel must be in the Y configuration.

15 3-input multiplexer

A bit that selects the analog input of channel 0 or the analog input of channel 1.

15 2-1 Analog Bandwidth Control

Select the two digits of the analog bandwidth.

15 0 External clock selection

A bit that determines the source of the pixel clock.

A logic 0 enables the internal PLL that generates the pixel clock from an externally supplied HSYNC.

A logic 1 enables the external CKEXT input pin. In this mode, the PLL divide ratio (PLLDIV) is ignored. Clock phase adjustment (phase) still works.

The power-on default is EXTCLK=0.

2-wire serial control port

Provides a 2-wire serial control interface. Up to two AD9888 devices can be connected to the 2-wire serial interface, each with a unique address.

The 2-wire serial interface includes clock (SCL) and bidirectional data (SDA) pins. The AD9888 acts as a slave to receive and transmit data over the serial interface. When the serial interface is inactive, the logic levels on SCL and SDA are pulled high by external pull-up resistors.

Data received or transmitted on the SDA line must remain stable during the SCL positive pulse. Data on SDA can only be changed when SCL is low. If SDA changes state while SCL is high, the serial interface interprets the operation as a start or stop sequence.

Serial bus operation has five components: start signal; slave address byte; base register address byte; read or write data byte; stop signal.

Communication is initiated by sending a start signal when the serial interface is inactive (SCL and SDA high). When SCL is high, the start signal on SDA is a high-to-low transition. This signal alerts all slave devices that a data transfer sequence is imminent.

The first 8 bits of data transferred after the start signal include the 7-bit slave address (first 7 bits) and a single R/W bit (8th bit). The R/W bit indicates the data transfer direction for reading from (1) or writing (0) the slave device. If the sent slave address matches the device address (set by the state of the A0 input pin in Table XLI), the AD9888 acknowledges it by driving SDA low on the ninth SCL pulse. If the addresses do not match, the AD9888 does not acknowledge.

Data transfer via serial interface

For each data byte read or written, the MSB is the first bit in the sequence.

If the AD9888 does not acknowledge the master during the write sequence, SDA is held high so that the master can generate a stop signal. If the master does not acknowledge the AD9888 during the read sequence, the AD9888 interprets it as an "end of data". SDA is kept high so that the master can generate a stop signal.

Writing data to a specific control register of the AD9888 requires writing the 8-bit address of the control register of interest after the slave address is established. This control register address is the base address for subsequent write operations. The base address is automatically incremented by one byte for each byte of data written after the data byte prepared for the base address. If more bytes are transferred than are available, the address will not be incremented and will remain at its maximum value of 19H. Any base address higher than 19H will not generate an acknowledge signal.

Data is read from the AD9888's control register in a similar fashion. A read requires two data transfer operations.

The base address must be written with the lower R/W bits of the slave address byte to set up sequential read operations.

Reads (high R/W bits of the slave address byte) start from the previously established base address. The address of the read register is automatically incremented after each byte transfer.

To terminate the read/write sequence to the AD9888, a stop signal must be sent. The stop signal consists of a low-to-high transition of SDA when SCL is high.

Repeated start signals occur when a master device driving a serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the communication mode (read, write) between slave and master without releasing the serial interface line.

Serial Interface Read/Write Example

Write a control register to start the signal

Slave address byte (R/W bit = low)

base byte

data byte to base stop signal

Write four consecutive control register start signals

Slave address byte (R/W bit = low)

base byte

data byte to base address

data byte to (base address + 1)

data byte to (base address + 2)

data byte to (base address + 3) stop signal

Read start signal from a control register

Slave address byte (R/W bit = low)

base byte

start signal

Slave address byte (R/W bit = high)

data byte from base stop signal

read from four consecutive control registers

start signal

Slave address byte (R/W bit = low)

base byte

start signal

Slave address byte (R/W bit = high)

data byte from base address

data byte from (base address + 1)

data byte from (base address + 2)

data byte from (base address + 3)

stop signal

Synchronous processing

Sync Slicer

The purpose of the sync slicer is to extract the sync signal from the green graphics channel. The sync signal is not present in all graphics systems, only those that are synced to green. The sync signal is extracted from the green channel in a two-step process. First, the SOG input is clamped to its negative peak (typically 0.3v below black level). Next, the signal goes to a comparator with a variable trigger level, nominally 0.15v above the clamp level. A "slice" sync is usually a composite sync signal containing Hsync and Vsync.

sync separator

The sync separator extracts the Vsync signal from the composite sync signal. It is implemented by a low-pass filter or integrator-like operation. It works by keeping the Vsync signal active much longer than the Hsync signal. Therefore, it rejects any signal smaller than the threshold, which is between the Hsync pulse width and the Vsync pulse width.

The sync separator on the AD9888 is an 8-bit digital counter with a 5 MHz clock. It works independently of the polarity of the composite sync signal. (The polarity is decided elsewhere on the chip) The basic idea is that the counter counts when there is an Hsync pulse. But due to the relatively short width of the Hsync pulse, the counter only reaches the value of N before the end of the pulse. The countdown then begins, eventually reaching 0 before the next Hsync pulse arrives. The specific value of N varies for different video modes, but is always less than 255. For example, for a 1μs wide Hsync, the counter will only reach 5 (1μs/200 ns = 5). Now, when Vsync appears on composite sync, the counter also counts. However, since the Vsync signal is longer, it will count to a higher number M. M will be at least 255 for most video modes. Therefore, when the counter count is greater than N, Vsync can be detected by detecting the composite sync signal. The specific count of trigger detection (T) can be programmed through the serial register (0FH).

Once Vsync is detected, there is a similar process to detect when it becomes inactive. On detection, the counter first resets to 0, then starts counting when Vsync disappears. Similar to the previous case, when the counter reaches the threshold count (T), it will detect the absence of Vsync. This way it will reject noise and/or sawtooth pulses. Once the absence of Vsync is detected, the counter will reset to 0 and start the loop again.

PCB Layout Recommendations

The AD9888 is a high-precision, high-speed analog device. For maximum performance, it is important to have a well-placed board. The following are guidelines for designing a board using the AD9888.

Analog interface input

It is important to use the following layout techniques on the graphics input side.

Minimize trace length into graphics input. This is achieved by placing the AD9888 as close as possible to the graphics (VGA) interface. Long input trace lengths are undesirable as they will pick up more noise from the board and other external sources.

Place the 75Ω termination resistor (see Figure 1) as close as possible to the AD9888 chip. Any additional trace length between the termination resistor and the AD9888 input will increase the magnitude of the reflection, which will corrupt the graphic signal.

Use 75Ω matched impedance traces. Tracking impedances other than 75Ω also increase the chance of reflections.

The AD9888 has a very high input bandwidth (500 MHz). While this is desirable for acquiring high-resolution PC graphics signals with fast edges, it means it will also capture any high-frequency noise present. Therefore, it is important to reduce the noise coupled to the input. Avoid running any digital traces near analog inputs.

The AD9888 can digitize graphic signals over a very wide frequency range (10 MHz to 205 MHz). Often, properties that are beneficial at one frequency are detrimental at another. Analog bandwidth is one such feature. For UXGA resolutions (up to 205mhz), very high analog bandwidth is required due to the fast input signal slew rate. For VGA and lower resolutions (down to 12.5 MHz), a very high bandwidth is not desirable because it allows too much noise to pass through. To accommodate these changing needs, the AD9888 includes variable analog bandwidth control. Four settings are available (75MHz, 150MHz, 300MHz, and 500MHz), allowing the analog bandwidth to match the resolution of the input graphics signal.

power bypass

A 0.1µF capacitor is recommended to bypass each supply pin. The exception is when two or more power pins are next to each other. For these power/ground groupings, only one bypass capacitor is required. The basic idea is to have a bypass capacitor within 0.5cm of each power pin. Also, avoid placing the capacitor on the other side of the AD9888's PC board, as it will insert resistive vias in the path.

Bypass capacitors should be located between the power plane and the power pins. Current should flow out of the power plane => capacitor => power pin. Do not make power connections between capacitors and power pins. Placing vias under the capacitor pads, all the way to the power plane, is usually the best approach.

Of particular importance is the PVD (clock generator power supply) that maintains low noise and good stability. Sudden changes in PVD can lead to similar changes in sampling clock phase and frequency. This can be avoided by careful attention to conditioning, filtering and bypassing. It is best to provide a separate regulated power supply for each analog circuit group (VD and PVD).

Some graphics controllers use very different power levels when active (during active picture time) and idle (during horizontal and vertical sync). This results in a measurable change in the voltage supplied to the analog power regulator, which in turn produces a change in the regulated analog supply voltage. This can be mitigated by regulating the analog supply or at least the PVD from a different, cleaner supply (eg from a 12V supply).

It is also recommended to use a single ground plane for the entire board. Experience has shown time and time again that single-surface noise performance is equal or better. Using multiple ground planes can be detrimental because each individual ground plane is smaller and can result in long ground loops.

In some cases, the use of a separate ground plane is unavoidable. For these cases, it is recommended to place at least a single ground plane under the AD9888. The location of the split should be at the receiver of the digital output. In this case, it's more important to place components wisely, as the current loop will be longer (the path for the current to have the least resistance). An example of a current loop: power plane => AD9888 => digital output trace => digital data sink => digital ground plane => analog ground plane.

phase locked loop

Place the PLL loop filter components as close as possible to the filter pins.

Do not place any digital or other high frequency traces near these parts.

Use a value with a tolerance of 10% or less suggested in the data sheet.

output (data and clock)

Minimize the trace length that the digital output must drive. Longer traces have higher capacitance, require more current, and generate more internal digital noise. Shorter trajectories reduce the chance of reflections.

Adding a 22Ω to 100Ω series resistor to the AD9888 suppresses reflections, reduces EMI, and reduces current spikes. However, if 50Ω traces are used on the PCB, these resistors should not be required for the data output.

The 22Ω resistor on the packet output should provide good impedance matching to reduce reflections. If EMI or current spikes are an issue, we recommend using a lower drive strength setting by adjusting Register 14H. If using series resistors, place them as close as possible to the pins of the AD9888 (but avoid adding vias or extra length to the output traces to bring the resistors closer together).

If possible, limit the capacitance driven by each digital output to less than 10 pF. This can easily be achieved by keeping the traces short and connecting the output to only one device. Loading the output with too much capacitance will increase the current transients inside the AD9888, causing more digital noise on its power supply.

digital input

The digital inputs on the AD9888 are designed for 3.3V signals, but allow 5.0V signals. So if 5.0v logic is used, no additional components need to be added.

Any noise entering the Hsync input tracking will add jitter to the system. Therefore, try to minimize the track length and do not run any digital or other high frequency tracks near it.

voltage reference

Bypass with 0.1µF capacitor. Place it as close as possible to the AD9888 pins. Keep the ground connection as short as possible.