To achieve a high signal-to-noise ratio (SNR), the aperture jitter of the ADC must be low. ADCs with aperture jitter as low as 60 fs rms are currently available ( AD9445 14-bit 125MSPS and AD9446 16-bit 100MSPS). To avoid degrading the ADC's performance, a sampling clock with very low jitter must be used because the total jitter is equal to the root sum of the converter's internal aperture jitter and the external sampling clock jitter. However, oscillators used to generate sampling clocks are often characterized by phase noise rather than time jitter. The purpose of this paper is to present a simple method to convert oscillator phase noise into time jitter.
Phase Noise Definition First define several definitions. Figure 1 shows a typical output spectrum of a non-ideal oscillator with jitter in the ie domain, corresponding to phase noise in the frequency domain. The spectrum shows that the noise power in the 1Hz bandwidth is a function of frequency. Phase noise is defined as the ratio of noise within a 1Hz bandwidth at nominal frequency offset fm to oscillator signal amplitude at frequency fO Figure 1: Oscillator power spectrum affected by phase noise

The sampling process is basically the multiplication of the sampling clock by the analog input signal. This is multiplication in the time domain, which is equivalent to convolution in the frequency domain. Therefore, the spectrum of the sample clock oscillator is convolved with the input and displayed on the FFT output of a pure sine wave input signal (see Figure 2).
Figure 2: Effect of sampling clock phase noise on an ideal digitized sine wave

"Carrier close" phase noise "smears" the fundamental signal in multiple frequency bins, reducing the overall spectral resolution. "Broadband" phase noise causes overall SNR degradation, as shown in Equation 1:
SSB phase noise is often used to characterize oscillators, as shown in the phase noise (dBc/Hz) versus frequency offset fm plot in Figure 3, where the frequency axis is on a logarithmic scale. Note that the actual curve is fitted by multiple regions, each with a slope of 1/fx, x=0 corresponds to the "white" phase noise region (slope=0dB/10x), and x=1 corresponds to "flicker" "The phase noise region (slope = –20dB/10 times) also has regions with x = 2, 3, and 4, which appear in sequence, getting closer and closer to the carrier frequency.
Figure 3: Oscillator Phase Noise (dBc/Hz) vs. Frequency Offset

Note that the phase noise curve is somewhat similar to the amplifier's input voltage noise spectral density. Like amplifier voltage noise, oscillators also have a strong need for a lower 1/f corner frequency.
We have seen that oscillator performance is often described in terms of phase noise, but in order to correlate phase noise to ADC performance, phase noise must be converted to jitter. To correlate this curve to a modern ADC application, an oscillator frequency (sampling frequency) of 100MHz was chosen for ease of discussion, and a typical curve is shown in Figure 4. Note that the phase noise curve is fitted by a number of line segments whose endpoints are defined by data points Figure 4: Calculating jitter from phase noise

Converting Phase Noise to Jitter The first step in calculating equivalent rms jitter is to obtain the integrated phase noise power over the frequency range of interest (ie, area A of the curve). The curve is divided into separate regions (A1, A2, A3, A4), each defined by two data points. In general, assuming no filtering between the oscillator and the ADC input, the upper limit of the integration frequency range should be 2 times the sampling frequency, which is approximately the bandwidth of the ADC sampling clock input.
The choice of the lower limit of the integral frequency range also needs some consideration. In theory, it should be as low as possible in order to get true rms jitter. In practice, however, manufacturers generally do not give oscillator characteristics for offset frequencies less than 10 Hz, but this can be calculated with sufficient accuracy. In most cases, it is reasonable to choose 100Hz as the lower limit of the integral frequency if the characteristic at 100Hz is provided. Otherwise, 1kHz or 10kHz data points can be used.
It should also be considered that "close-in" phase noise affects the spectral resolution of the system, while broadband noise affects the overall system signal-to-noise ratio. Perhaps the most sensible approach is to integrate each region separately as described below and examine the magnitude of the jitter contribution of each region. If a crystal oscillator is used, the low frequency contribution may be negligible compared to the broadband contribution. Other types of oscillators may have considerable jitter contributions in the low frequency region, and their importance to the overall system frequency resolution must be determined.
The integration of each region yields individual power ratios, which are then summed and converted back to dBc. Once the integrated phase noise power is known, the rms phase jitter can be calculated (in radians, see References 3 to 7 for more information and implications):
Dividing the above result by 2πfO converts jitter expressed in radians to jitter expressed in seconds: it should be noted that computer programs and spreadsheets can be found on the web to perform piecewise integration and calculate rms jitter, greatly simplifying the calculation process ( References 8, 9).
Figure 5 shows an example calculation that assumes only broadband phase noise is present. The selected –150dBc/Hz wideband phase noise is characteristic of a good signal generator, and the resulting jitter values are representative of the actual situation. The phase noise of –150dBc/Hz (expressed as a ratio) is multiplied by the integration bandwidth (200MHz) to give an integrated phase noise of –67dBc. Note that this multiplication is equivalent to adding a 10log10 [200MHz–0.01MHz] quantity to the phase noise (dBc/Hz). In practice, the lower frequency limit of 0.01MHz can be discarded in the calculation as it will not have a significant impact on the final result. Using Equation 3, the total rms jitter is about 1ps.
Figure 5: Example of jitter calculation assuming only broadband phase noise is present

Crystal oscillators generally have the lowest phase noise and jitter, and Figure 6 shows a few examples for comparison. All oscillators shown have a 1/f corner frequency of 20kHz, so the phase noise represents the white phase noise level. The two Wenzel oscillators are fixed frequency and offer excellent performance (Reference 9). It is difficult to achieve such high performance with a variable frequency signal generator, a relatively high quality generator will have a performance of –150dBc as shown.

Figure 6: Broadband Phase Noise Floor Comparison of 100 MHz Oscillators (Wenzel ULN and Sprinter series are featured and quoted with permission from Wenzel Associates)
It should be noted here that there is a theoretical limit to the noise floor of the oscillator, which is determined by the thermal noise of the matched source: –174dBm/Hz at +25°C. Therefore, an oscillator with phase noise of –174dBc/Hz driving a 50Ω (2.82-Vp-p) load with a +13-dBm output would have a noise floor of –174dBc+13dBm=–161dBm. This is the case with the Wenzel ULN series shown in Figure 6.

Figure 7 shows the jitter calculations for two Wenzel crystal oscillators. The data points in each case were taken directly from the manufacturer's data sheet. Due to the low 1/f corner frequency, the vast majority of jitter is caused by the "white" phase noise region. Calculated values of 64fs (ULN-Series) and 180fs indicate extremely low jitter. The noise contribution of each region is marked separately in the figure for reference. Figure 7: Jitter calculation for a low noise 100MHz crystal oscillator (phase noise data used with permission from Wenzel Associates)

In system designs that require low-jitter sampling clocks, the cost of low-noise dedicated crystal oscillators is typically prohibitive. An alternative is to use a phase-locked loop (PLL) and a voltage-controlled oscillator to "purify" the noisy system clock, as shown in Figure 8. There are many good references on PLL design (e.g. References 10 to 13) and will not be discussed further here, but just to make a point: using narrow bandwidth loop filters and voltage controlled crystal oscillators (VCXOs) can often be obtained lowest phase noise. As shown in Figure 8, PLLs tend to reduce “close-to-carrier” phase noise while reducing the overall phase noise floor. Connecting an appropriate bandpass filter after the PLL output can further reduce the white noise floor

Figure 8: Conditioning a noisy clock source using a phase-locked loop (PLL) and a bandpass filter

The effect of having a free-running VCO built into the PLL is shown in Figure 9. Note that the "close-to-carrier" phase noise is greatly reduced due to the PLL.
Figure 9: Phase noise of a free-running VCO and a VCO connected to a PLL

ADI offers many different frequency synthesis products, including DDS systems, integer-N and fractional-N PLLs, and more. For example, the ADF4360 family is a fully integrated PLL with a built-in VCO. The phase noise of the ADF4360-1 2.25-GHz PLL when combined with a 10kHz bandwidth loop filter is shown in Figure 10, and the piecewise approximation and jitter calculations are shown in Figure 11. Note that even with an amorphous VCO, the rms jitter is only 1.57ps.
Figure 10: Phase Noise of ADF4360-1 2.25-GHz PLL with 10 kHz Bandwidth Loop Filter

Figure 11: Piecewise Approximate Jitter Calculation for ADF4360-1 2.25-GHz PLL Phase Noise

Historically, PLL design has relied heavily on textbooks and application notes to help design loop filters, etc. PLL design is now made easy with ADI's free downloadable ADIsimPLL™ software. To start designing, select a circuit by entering the desired output frequency range, then select the PLL, VCO, and crystal reference. Once the loop filter configuration is selected, the circuit can be analyzed and optimized in both frequency and time domains for phase noise, phase margin, gain, spurious levels, lock time, and more. The program also calculates the rms jitter from the PLL phase noise to evaluate the final PLL output as the sampling clock.

Conclusion Sampling clock jitter can have a catastrophic effect on the signal-to-noise performance of a high-performance ADC. Although the relationship between signal-to-noise ratio and jitter is well known, most oscillators are characterized by phase noise. This article shows how to convert phase noise into jitter so that the drop in signal-to-noise ratio can be easily calculated.
ADF4360-1
Output frequency range: 2050 MHz to 2450 MHz
Divide-by-2 Output 3.0 V to 3.6 V Supply 1.8 V Logic Compatible Integer-N Divide-by-N Frequency Synthesizer Programmable Dual Modulo Prescalers: 8/9, 16/17, 32/33
Programmable output power level 3-wire serial interface Analog and digital lock detection

Modern PLLs that use crystal VCOs (and proper filtering), while not as ideal as expensive stand-alone crystal oscillators, can also achieve excellent jitter performance for most but the most demanding applications. Because of the low jitter requirement, the whole clock distribution problem becomes more important.