feature

Low voltage and low power operation: FT24C02 A: VCC=1.8V to 5.5V, industrial temperature range (-40°C to 85%). Two versions of the FT24C02A: FT24C02A-5xx: Low cost, 5 active pins. Suitable for most applications, except for multiple EEPROMs on the same IIC bus. Details in the Device Addressing section. FT24C02A Uxx: 8 valid pins for all applications. Maximum standby current <1μA (0.02μA and 0.06μA, 1.8V and 5.5V, respectively).

16-byte page write mode. Partial page write operations are allowed. Internal Organization: 256 x 8 (2K). Standard 2-wire bidirectional serial interface. Schmitt trigger, filtered input for noise protection. Self-timed programming cycle (maximum 5ms). 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) compatibility. Erase automatically before write operation. Write protect pin for hardware data protection. High reliability: typically 1 million cycles durability. 100 years data retention. Standard 8-pin PDIP/SOIC/TSSOP/DFN and 5-pin SOT-23 /TSOT-23 lead-free packages.

illustrate

FT24C02A is a 2048-bit serial electrically erasable programmable read-only memory, commonly known as EEPROM. They are organized into 256 words of 8 bits (1 byte) each. Devices are fabricated on a dedicated advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead DFN, and 5-lead SOT-23/TSOT-23 packages. A standard 2-wire serial interface is used to handle all read and write functions. Our extended VCC range (1.8V to 5.5V) devices enable applications.

Absolute Maximum Ratings Industrial Operating Temperature -40°C~85°C Storage Temperature: -50°C to 125°C Input Voltage to Ground on Any Pin: -0.3V to VCC+0.3V Maximum Voltage: 8V ESD on All Pins Protection: >2000V Stresses exceeding those listed under "Absolute Maximum Ratings" may cause permanent damage. device. Confidence in the functional operation of the device under conditions beyond those listed in the specification. Long-term exposure to extreme conditions may affect device reliability or functionality.

Pin Description

(A) Serial Clock (SCL) The rising edge of this SCL input is to latch data into the EEPROM device, and this clock is used to clock data from the EEPROM device.

(B) Serial Data Line (SDA) The SDA data line is a bidirectional signal for serial devices. It is an open-drain output signal that can be interfaced with other open-drain output devices.

(C) Write Protect (WP) The FT24C02A device has a WP pin to protect the entire EEPROM array from programming. Programming operations are allowed if the WP pin is not connected or input to VIL. Conversely, all programming functions are disabled if the WP pin is connected to VIH or VCC. Read operations are not affected by the input level of the WP pin. The memory organization for the FT24C02A device has 16 pages. Since there are 16 bytes per page, random word addressing to the FT24C02A requires an 8-bit data word address. Device Operation (A) Serial Clock and Data Conversion The SDA pin is normally pulled high by an external resistor. only when the serial clock SCL is at VIL. Any SDA signal transition can be interpreted as a start or stop condition as described below. (B) Start condition When SCL ≥ VIH, a high-to-low transition of SDA is interpreted as a start condition. All valid commands must begin with a start condition. (C) Stop condition When SCL ≥ VIH, a low-to-high transition of SDA is interpreted as a stop condition. All valid read or write commands end with a STOP condition. If the device enters standby mode after the read command. A stop condition following a page or byte write command will trigger the chip to enter standby mode after the auto-timed internal programming is complete.

(D) Acknowledges that the 2-wire protocol uses 8-bit words to send address and data to the EEPROM. This EEPROM acknowledges the data or address by outputting a "0" after each word is received. This acknowledgment appears on the 9th serial clock after each word. DS3011B-page4 © 2009 Fremont Micro Devices Corporation. FT24C02A 2009 Fremont Micro Devices DS3011B-page5

(E) Standby Mode After receiving a stop bit, the EEPROM enters a low-power standby mode upon power cycle in read mode, or upon completion of a self-timed internal programming operation.

Device addressing The 2-wire serial bus protocol requires an 8-bit device address word to invoke a valid read or write command after a start bit condition. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are the device address bits. The three device address bits (bits 5, 6, and 7) match the state of the external chip select/address pins. If there is a match, the EEPROM device outputs an acknowledge signal after the 8th read/write bit, otherwise the chip will enter standby mode. However, the "-5xx" version of the chip cannot be matched. These three device address bits are unimportant and can be encoded from 000(b) to 111(b). Only one FT24C02A device can be used on the 2-wire bus. If there is a match, the EEPROM device outputs an acknowledge signal after the 8th read/write bit, otherwise the chip will go into standby mode. The last or 8th bit is the read/write command bit. If bit 8 is at VIH, the chip enters read mode. If a "0" is detected, the device enters programming mode. Write Operation (A) Byte Write A byte write operation begins when the microcontroller sends a start bit condition, followed by the EEPROM device address, followed by a write command. If the device address bits match the chip select address, the EEPROM device will acknowledge on the 9th clock cycle. The microcontroller will then send the remaining lower 8 bits of the word address. On the 18th cycle, the EEPROM will acknowledge the 8-bit address word. The microcontroller will then send 8 bits of data. Following the 27th clock cycle, an acknowledge signal from the EEPROM, the microcontroller will issue a stop bit.

After receiving the stop bit, the EEPROM will enter an automatic timing programming mode during which all external inputs are disabled. After the programming time of the TWC, the byte programming will complete and the EEPROM device will return to standby mode. (B) Page Writes Page writes are similar to byte writes, but 1 to 16 bytes can be programmed along the same page or row of memory. All FT24C02As are organized with 16 bytes or pages per memory row. Using the same write command as a byte write, the microcontroller sends the first byte of data and receives an acknowledge signal from the EEPROM on the 27th clock cycle. Instead, it sends the second 8-bit data word, and the EEPROM loops on the 36th. This data transmission and EEPROM acknowledgement cycle repeats until the microcontroller sends a stop bit after n × 9 clock cycles. After that, the EEPROM device will enter self-timed partial or full-page programming mode. After the page programming is completed TWC, the device will return to standby mode. The least significant 4 bits of the word address (column address) are internally incremented by 1 to receive each data word. The remaining word address bits (row addresses) do not change internally, but point to the specific memory row or page to be programmed. The first page write data word can be at any column address. A page can load up to 16 data words. If more than 16 data DS3011B-page6 © 2009 Fremont Micro Devices Corporation. After the FT24C02A loads the word, the 17th data word will be loaded to the 1st data word column address. The 18th data word will be loaded into the second data word column address and so on. In other words, the data word address (column address) will "roll over" the previously loaded data.

(C) Confirmation Polling Confirmation Polling can be used to poll the programmed status programming in an automatically timed internal process. By issuing a valid read or write address command, the EEPROM will not acknowledge on the 9th clock cycle if the device is still in automatic timing programming mode. However, if programming is complete and the chip has returned to standby mode, the device will return a valid acknowledgment signal on the 9th clock cycle. Read Operation The read command is similar to the write command, except that the 8th read/write bit in the address word is set to '1'. The three read operation modes are described as follows: (A) Current address read EEPROM internal address word counter holds the last read or write address plus a device power has not been cut off. To initiate a current address read operation, the microcontroller issues a start bit and a valid device address word with the read/write bit (bit 8) set to '1'. The EEPROM will respond with an acknowledge signal on the ninth serial clock cycle. An 8-bit data word will then be serially clocked out. Then the internal address word counter will automatically increment by one. For the current address read, the microcontroller does not issue an acknowledge signal for the 18th clock cycle. The microcontroller terminates the read operation on the 18th clock cycle. The device then returns to standby mode. (B) Sequential read Sequential reads are very similar to current address reads. The microcontroller issues a start bit and a valid device address word with the read/write bit (bit 8) set to "1". The EEPROM will respond to the acknowledge signal on the 9th serial clock cycle. The 8-bit data word will then be clocked serially. At the same time, the internal address word counter will automatically increment by one.

Unlike the current address read, the microcontroller sends an acknowledgment signal on the 18th clock cyclically to signal the EEPROM device that it needs another byte of data. Upon receipt of an acknowledgment signal, the EEPROM will increment the internal address counter according to. If the microcontroller needs another data, it sends an acknowledgment on the 27th clock cycle. Then, another 8-bit data word will be clocked out continuously. As long as the microcontroller sends an acknowledgment signal, the sequential read will continue after new data words are received. When the internal address counter reaches its maximum valid address, it rolls over to the beginning of the memory array address. Similar to the address currently read, the microcontroller can terminate a sequential read by not acknowledging the last data word received, but then sending a stop bit. 2009 Fremont Micro Devices Inc. DS3011B-page 7FT24C02A Model DS3011B-page 8 © 2009 Fremont Micro Devices Inc. (C) Random Read Random read is a two-step process. The first step is to use the target read address using a "pseudo-write" instruction. The second step is to read the current address. To initialize the internal address counter with the target read address, the microcontroller issues a valid device address with first the start bit and then the read/write bit (bit 8) set to "0". Electrically Erasable Programmable Read-Only Memory will then recognize. The microcontroller will then send the address word. EEPROM will recognize again. The microcontroller does not send valid write data to the EEPROM to execute the current address read command to read the data. Note that once the start bit is issued, the EEPROM will reset the internal programming process and continue with a new instruction - that is, read the current address.

Note: 1. This parameter was obtained by characterization, but not fully screened by testing.

2. AC measurement conditions: RL (connected to Vcc): 1.3KΩ Input pulse voltage: 0.3Vcc to 0.7Vcc Input and output timing reference voltage: 0.5Vcc