General Instructions

FM27C512 is a high performance 512K UV erasable electrically programmable read only memory (EPROM). Manufactured using Fairchild's proprietary CMOS AMG 8482 ;EPROM technology, it achieves the perfect combination of speed and economy while delivering exceptional reliability. The FM27C512 provides the capacity for a microprocessor-based system to store operating system and application software portions. Its 90 ns access time provides high-performance CPUs with wait-free operation. The FM27C512 provides a solution to the MCU's 100 % fixed device code storage requirements. Commonly used software programs are quickly executed from the EPROM memory, greatly improving the usability of the system. The FM27C512 is configured in a standard JEDEC EPROM with pinouts that provide an easy upgrade path for the following systems. The standard EPROM is currently being used. Block Diagram May 2001 The FM27C512 is a member of the high-density EPROM family with densities ranging up to 4 Mbits.

feature

High performance CMOS - 90, 120, 150 ns access times Fast turn off Microprocessor compatibility Manufacturer identification code JEDEC Standard pin configuration - 32-pin PLCC package - 28-pin CERDIP package

Absolute Maximum Ratings (Note 1) Storage Temperature -65°C to +150°C All input voltages except A9 -0.6V to +7V VPP and A9 -0.7V to +14V relative to ground

VCC supply voltage relative to ground -0.6V to +7V ESD protection (MIL Standard 883, Method 3015.2 ) >2000V All output voltages relative to ground VCC +1.0V to ground -0.6V

Note 1: The stresses listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is only a pressure rating and functional operation of the device under the above or any other conditions stated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.

Note 2: This parameter is only sampled, not 100% tested.

Note 3: After CE falling edge, OE may be delayed up to tACC–tOE without affecting tACC.

Note 4: The tDF and tCF comparison levels are determined as follows: high to tri-state, measure VOH1(DC) -0.10V; low to tri-state, measure VOL1(DC) +0.10V.

Note 5: Tri-state can be achieved using OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended to use at least a 0.1µF ceramic capacitor between VCC and GND on each device.

Note 7: The output must be limited to VCC+1.0V to avoid latch-up and device damage.

Note 8: 1 TTL gate: IOL=1.6mA, IOH= -400µA . CL: 100 pF including clamp capacitance.

Note 9: Input and output may be below -2.0V, 20 ns max.

Functional Description Device Operation: Table 1 lists the six operating modes of the EPROM. It should be noted that all inputs for the six modes are at TTL levels. The required power supplies are VCC and OE/VPP. Running Experience/Virtual Private Program During three programmings, the power supply must be 12.75 V mode and 5V in the other three modes. During the three programming process of VCC, the power supply must be 6.5V mode, and the other three modes are 5V. The read mode EPROM has two control functions, both of which must be logically active in order to obtain data on the output. Chip Enable (CE/PGM) is a power control that applies to device selection. Output Enable (OE/VPP) is the output control and should be used to transfer data to the output pins, independent of device selection. Assuming the address is stable, the address access time (tACC) is equal to the delay from CE to output (tCE). Data is at the output toe, available after the falling edge of OE, assuming CE has been low and the address is stable for at least some time tACC-TOE. Standby Mode The EPROM has a standby mode that can reduce active power from 220 MW to 0.55 MW with losses over 99%.

EPROM by applying a CMOS high signal to the CE/PGM input. When in standby mode, the output is in a high impedance state, independent of the OE input. Output Disable Signal sent to OE input by applying TTL high, EPROM is in output disable state. When the input and output are disabled, all circuits are enabled, but the output is in a high impedance state (tri-stated). Output or Type Because EPROMs are often used in larger memory arrays, Fairchild provides a two-wire control function that accommodates the use of multiple memory connections. The two-wire control feature allows: 1. the lowest possible memory power consumption, and 2. full assurance that output bus contention will not occur. For the most efficient use of these two control lines, it is recommended that CE/PGM be decoded and used as the primary device selection function, while OE/VPP become a common connection for all devices in the array and connect to the system control bus. This ensures that all deselected memory devices are in low power standby mode and that the output pins are only activated when data from a specific memory device is required.

Programming Note: If the voltage on pin 22 (OE/VPP) exceeds 14V, the Eprom will be damaged. Initially, after each erase, all bits of the EPROM are in the "1" state. Data is introduced into the desired bit position by selectively programming "0"s. Although only "0" will be programmed, both "1" and "0" can be displayed in the data word. The only way to change "0" to "1" is UV Erase. When OE/VPP is at 12.75V. It is required to place at least a 0.1µF capacitor through VCC to ground to suppress stray voltage transients that can damage the device. The data to be programmed is to apply 8 bits in parallel to the data output pins. required level because address and data inputs are TTL. When the address and data are stable, an active low TTL program pulse is applied to the CE/PGM input. A program pulse must be applied to each address location to be programmed. The EPROM is programmed using the turbo programming algorithm shown in Figure 1. Each address is pulsed with a series of 50 seconds until the verification is good, up to a maximum of 10 pulses. Most memory cells will be programmed using a single 50 microsecond pulse. (Standard National Semiconductor algorithm can also be used, but the programming time is longer.) EPROM must not be used for CE/PGM input. Programming multiple EPROMs in parallel with the same data is easy to implement because of the simplicity of programming. Similar inputs of parallel EPROMs can be tied together when programmed with the same data. Low level TTL pulse parallel EPROM applied to CE/PGM input program.

It is also easy to program multiple eproms in parallel with different data. All similar input parallel eproms (including OE/VPP) except CE/PGM may be common. A TTL low-level program pulse applied to the CE/PGM of the EPROM at 12.75V into OE/VPP will program the EPROM. TTL high CE/PGM level inputs inhibit programming of other EPROMs. Program Verification should be performed on the programming bit to determine if it was programmed correctly. Validation is done at VIL with OE/VPP and CE. Data should be verified by TDV after CE falling edge. An opaque label should be attached to the EPROM window after programming to prevent inadvertent erasure. Covering the windows will also prevent temporary malfunctions due to photo-generated ocean currents. Manufacturer Identification Code EPROMs have a manufacturer identification code to aid in programming. When the device is plugged into the EPROM programmer socket, the programmer reads the code and then automatically calls the section. This automatic programming is controlled only by programmers who have the ability to read code. The manufacturer's identification code, shown in Table 2, is used exclusively to identify the manufacturer and device type. The code for the FM27C512 is "8F85", where "8F" means it is made by Fairchild Semiconductor, and "85" means 512K part. The code is accessed by applying 12V±0.5V to address pin A9. Addresses A1-A8, A10-A16 and all control pins

Functional Description (continued). Address pin A0 is kept at VIL for manufacturer's code and at VIH for device code. The code is on the eight data pins, O0–O7. Only guarantee correct code access at 25°C ±5°C. Erase Characteristics The erase characteristics of the device are such that when exposed to shorter wavelength light greater than about 4000 Angstroms begins to occur. It should be noted that fluorescent lamps and some types of fluorescent lamps have wavelengths between 3000 and 4000 Ohnes. The recommended erasing procedure for EPROM is exposure to a wavelength of 2537 Å. The combined dose (i.e. UV intensity x exposure time) erasure should be at least 15W sec/cm~2. The EPROM should be placed within 1" of the lamp during the erasing process. Some lamps have a filter on the tube that should be removed before erasing. The erasing system should be calibrated regularly. The distance from the lamp to the unit should be kept at 1 inch. Erase time increases with the square of the distance from the light (if the distance is doubled the erase time increases by a factor of 4). Lights weaken with age. When a lamp is replaced the distance changes or the lamp ages, the system should check to make sure that a full erase is in progress. Incomplete erasing can lead to potentially misleading symptoms. Programmers, components and even system designs are wrongly suspected when incomplete erasure is the problem. System consideration of the power switching characteristics of EPROMs requires attention to device decoupling. The supply current ICC has three segments of interest to the system designer: the standby current level, the active current level, and the peak transient current generated by voltage transitions on the input pins. The magnitude of these transient current peaks depends on the device output capacitive load. Transient voltage spikes can be suppressed by appropriate selection of the associated VCC decoupling capacitor. Recommended at least 0.1µF at VCC and ground. This should be a high frequency capacitor inductor with a low natural frequency. Also, at least one 4.7µF block electrolytic capacitor should be used between VCC and GND for every eight devices. This bulk capacitor should be located near the power supply connected to the array. The purpose of bulk capacitors is to overcome PC board traces.

Mode Selection Table 1 lists the operating modes of the FM27C512. A 5V power supply is required in read mode. All inputs are TTL levels except VPP and A9 for the device.