General Instructions
The V385A transmitter converts 28-bit 3.3V from CMOS/TTL to 4 low-voltage differential signaling (LVDS) data streams, while sending the transmit clock input in parallel with the data stream through a fifth LVDS link.
Compared to the V385, the V385A offers an extended clock frequency range of 12-90mhz instead of 20-85mhz. Other performance improvements have also been incorporated.
The V385A can be programmed for a rising or falling edge clock via pin RúFB.

feature
Extended clock frequency range of 12 to 90 MHz Pin and function compatible with National DS90C385 , TI SN65LVDS93 and THC63LVDM83 , but with extended clock frequency and operating temperature range Convert 28-bit 3.3V CMOS/TTL to 4 LVDS streams up to Up to 2.52Gbps throughput or 315Mbytes /sec bandwidth Spread Spectrum Compatible Supports SD, HD and VGA graphics applications
On-chip PLL requires no external components Single 3.3V low-power CMOS design operates from 0 to +70°C
Programmable rising or falling edge strobe power-down control function Compliant with TIA/EIA-644 LVDS standard in 56-pin TSSOP package (lead-free)

external components
The V385A requires no external components.
Stresses with absolute maximum ratings higher than those listed below can cause permanent damage to the V385A. These ratings are standard for ICS commercial grade parts and are stress ratings only. No functional operation of the device is implied under the above or any other conditions indicated in the operating section of this specification. Prolonged exposure to absolute maximum rating conditions can affect product reliability. Electrical parameters can only be guaranteed within the recommended operating temperature range.

AC timing diagram

Figure AC1. Transmitter setup/hold and high/low time (falling edge strobe or R_FB=0)

Figure AC2. Clock input to clock output delay (rising edge strobe or R_FB=1)

Figure AC3. PLL setting time

Figure AC4. Transmitter device transition time and load

Figure AC5. Transmitter LVDS output pulse position measurement Package outline and package size (56-pin TSSOP)

Package dimensions are consistent with JEDEC Publication No. 95