The ADT7476A is a dBCool™ Remote Thermal Controller and Voltage Monitor Price & Stock

2022-09-23 11:12:17

The ADT7476A is a dBCool™ Remote Thermal Controller and Voltage Monitor

feature

Monitors up to five voltages; improved RPM and PWM performance; controls and monitors up to four fans; high and low frequency fan drive signals; one chip and two remote temperature sensors; extended temperature measurement range to 191 °C; automatic Fan Speed Control Mode Control System; Cooling Based on Measured Temperature; Enhanced Acoustic Mode Greatly Reduces User Sensation; Changes Fan Speed Sensation; Thermal Protection Feature Through Thermal Output; Monitors Intel Pentium 4 Processor Performance Impact; Thermal Input Thermal Control Circuit; 3-wire and 4-wire fan speed measurement; limit comparison of all monitored values; 5V support for all speed and PWM channels; SMBus 2.0 electrical specification compliant.

General description

The DBCOOL controller is a thermal monitor and multiple PWM FAN controllers for noise sensitive or power sensitive applications requiring active system cooling. Tea can drive fans with low frequency or high frequency. The drive signal and the ability to monitor the two upper temperature sensing diodes and their internal temperature tea another part measures and controls the speed of the four fans, so the fans run at the lowest possible speed Acoustic noise Automatic fan speed control loop optimizes fan speed for a souvenir temperature. The effectiveness of the system thermal solution can be monitored by heat input. The ADT7476A also provides a critical thermal protection system using bidirectional tropical pine as the output to prevent overheating of the system or components.

Product Description

The ADT7476A is a complete thermal monitor and multi-fan controller for any system requiring thermal monitoring and cooling. Devices communicate with the system through the serial system management bus. The serial bus controller has a serial data line (pin 1) for reading and writing addresses and data and an input line (pin 2) for the serial clock. All control and programming functions of the ADT7476A are performed over the serial bus. Additionally, the pin can be reconfigured to output SMBALERT to signal out of limit conditions.

Comparison of characteristics between ADT776A and ADT768

(1) Dynamic T, dynamic operating point and related registers are no longer provided in ADT7476A. The following related registers disappear: o Calibration Control 1 (0x36) o Calibration Control 2 (0x37) o Operating Point (0x33, 0x34, and 0x35) Minimum.

(2), Previously (in the ADT7468), T defines the slope of the automatic fan control algorithm. T now defines a true temperature range (in the ADT7476A). range range.

(3) Sonic filtering is now assigned to the temperature zone instead of the fan. For better acoustic performance, the available smoothing time has been increased.

(4) Now use two switch currents instead of three. SRC is not available in the ADT7476A.

(5) High frequency PWM can now be enabled/disabled individually for each PWM output.

(6), THERM can now be enabled/disabled on each temperature channel separately.

(7), ADT7476A does not support fully shutdown mode.

(8), ADT7476A can improve the temperature accuracy of all temperature channels.

(9) ADT7476A defaults to double-compensation temperature measurement mode.

(10), some pins have been swapped/added functions.

(11) The power-on procedure of ADT7476A is simplified.

The ADT776A has a higher maximum input voltage TACH/PWM specification to support a wider range of fans.

V has been reassigned to bit 7 core low enable of configuration register 1 (0x40).

recommended implementation

Configuring the ADT7476A as shown in Figure 13 allows the system designer to use the following features:

(1) Two PWM outputs for fan control of up to three fans (front and rear chassis fans are connected in parallel).

(2), three tachometer fan speed measurement input.

(3), V is measured internally through pin 4. cocos islands

(4) Use the remote 1 temperature channel to measure the CPU temperature.

(5) The remote temperature area measured by the remote 2 temperature channels.

(6) The local temperature area measured by the internal temperature channel.

(7) Two-way hot pins. This feature allows Intel Pentium 4 Prochhot monitoring and can be used as an overheat output. It can also be programmed as an SMBALERT system interrupt output.

serial bus interface

The ADT7476A management bus (SMBus) is controlled using the serial system. The ADT7476A is connected to this bus as a slave device, under the control of the master controller. The ADT7476A has a 7-bit serial bus address. The default SMBus address of the ADT7476A is 0101110 or 0x2E when the device is powered up with pin 13 (PWM3/ADDREN) high. The read/write bits must be added to get an 8-bit address. If more than one ADT7476A is to be used in a system, each ADT7476AADT7476A enters ADDR select mode by bundling Pin 13 too low on power-up. The logic state of pin 14 then determines the SMBus address of the device. Their logic pins are sampled at power up. The device address is sampled at power-up and latched on the first valid SMBus transaction, more precisely on the low-to-high transition at the beginning of the eighth SCL pulse, when the serial bus address byte matches the selected slave machine address match. Use the ADDREN pin to select the selected slave address/address select pin. Any attempted changes in the address have no effect after this.

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The ability to hardwire changes to the SMBus slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if multiple ADT7476As are used in the system.

The serial bus protocol operates as follows:

1. The host initiates a data transfer by establishing a start condition, which is defined as a high-to-low transition on the serial data line SDA, while the serial clock line SCL remains high. This means that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and toggle the bits for the next eight working days, consisting of a 7-bit address (MSB first) plus the R/W bit, R The /W bit determines the direction of data transfer, that is, whether data is written to the slave device or read from the device.

The peripheral whose address corresponds to the address sent responds by pulling the data line low during the low cycle before the ninth clock pulse (called the acknowledge bit). All other devices on the bus are now idle while the selected device is waiting to read or write data from it. If the R/W bit is 0, the master device writes to the slave device. If the R/W bit is 1, the master device reads from the slave device.

2. The data is sent in the sequence of 9 clock pulses through the serial bus, and the 8-bit data is followed by the confirmation bit of the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period. When the clock is high, a low-to-high transition can be interpreted as a stop signal. The number of bytes of data transferred over the serial bus in one read or write operation is only limited by what the master and slave devices can handle.

3. A stop condition is established when all data bytes are read or written. In write mode, the master asserts a stop condition by pulling the data line high during 10 clock pulses. In read mode, the master passes the low period before the ninth clock pulse. This is called non-recognition. The master then asserts the stop condition by taking the data line low during the low period before the 10 clock pulses and then high during the 10 clock pulses.

Any byte of data can be transferred over the serial bus in one operation. However, you cannot mix reads and writes in one operation, because the type of the operation is determined at the beginning and cannot be subsequently changed without starting a new operation. In the ADT7476A, write operations consist of one or two bytes, and reads consist of one byte.

To write data to or read data from one of the device data registers, the address pointer register must be set up so that the correct data register is addressed. Data can then be written to or read from this register. The first byte of a write operation always contains the address stored in the address pointer register. If data is to be written to the device, the write operation consists of writing the second data byte of the register selected by the address pointer register.

This write operation is shown in Figure 18. The device address is sent over the bus, then R/W is set to 0. Followed by two data bytes. The first data byte is the address of the internal data register to be written, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register.

When reading data from a register, there are two possibilities:

1. If the address pointer register value of the ADT7476A is unknown or not the desired value, it must be set to the correct value before data can be read from the desired data register. This is done by performing a write operation to the ADT7476A as before, but only sending the data byte containing the register address because no data is written to the register (see Figure 19).

A read operation is then performed, which is determined by the bus address; the R/W bit is set to 1, followed by the data byte read from the data register (see Figure 20)

2. If the address pointer register is known to be at the desired address, data can be read from the corresponding data register without first writing to the address pointer register (see Figure 20).

If the value of the address pointer register is already correct, a data byte can be read from the data register without first writing to the address pointer register. However, it is not possible to write data to the address pointer register without writing to the address pointer register, because the first data byte written is always written to the address pointer register.

In addition to supporting the Send Bytes and Receive Bytes protocols, the ADT7476A also supports the Read Bytes protocol. See Intel System Management Bus Specification Revision.

If multiple read or write operations must be performed in succession, the host can send a repeated START condition instead of a STOP condition to start a new operation.

write operation

The SMBUS specification defines several protocols for different types of read and write operations. Those used in the ADT7476A are discussed below. The following abbreviations are used in the chart:

8226 ;S – start

•P – stop

• R – read

• W – write

• A – Confirmation

• A – not admitted

The ADT7476A uses the following SMBus write protocol.

send bytes

In this operation, the master sends a single command byte to the slave as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave asserts an ACK on SDA.

4. The host sends the command code.

5. The slave asserts ACK on SDA.

6. The primary server declares a stop condition on SDA and the transaction ends.

For the ADT7476A, the send byte protocol is used to write a register address to RAM so that subsequent single bytes can be read from the same address. This operation is shown in Figure 21.

If the host is required to read data from the register immediately after setting the address, it can assert a Repeated Start condition immediately after the final ACK and perform a single-byte read without asserting an Intermediate Stop condition.

write bytes

In this operation, the master device sends a command byte and a data byte to the slave device as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave asserts an ACK on SDA.

4. The host sends the command code.

5. The slave asserts ACK on SDA.

6. The host sends a data byte.

7. The slave asserts ACK on SDA.

8. The primary server declares a stop condition on SDA and the transaction ends. This operation is shown in Figure 22.

read operation

The ADT7476A uses the following SMBus read protocol.

receive bytes

This operation is useful when reading a single register repeatedly. The register address is preset. In this operation, the master device receives a single byte from the slave device as follows:

1. The master asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the read bit (high).

3. The addressed slave asserts an ACK on SDA.

4. The host receives a data byte.

5. The captain did not confirm on SDA.

6. The primary server declares a stop condition on SDA and the transaction ends.

In the ADT7476A, the receive byte protocol is used to read a single byte of data from a register whose address was previously set by a send byte or write byte operation. This operation is shown in Figure 23.

Alert response address

The Alarm Response Address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices are present on the same bus.

The SMBALERT output can be used as an interrupt output or as a SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the main server. If the device's SMBALERT line goes low, the following process occurs:

1. SMBALERT is pulled low.

2. The host initiates a read operation and sends an alarm response address (ARA=0001 100). This is a general calling address that cannot be used as a specific device address.

3. The device whose SMBALERT output is low responds to the alarm response address, and the host reads its device address. The address of this device is now known and can be queried routinely.

4. If multiple devices have low SMBALERT outputs, the device with the lowest device address has a priority consistent with normal SMBus arbitration.

5. Once the ADT7476A responds to the alert response address, the host must read the status register and clear SMBALERT only when the error condition disappears.

SMBus timeout

The ADT7476A includes an SMBus timeout function. If there is no SMBus activity for 35 ms, the ADT7476A assumes the bus is locked and releases the bus. This prevents the device from locking up or holding onto data required by SMBus. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled if desired.

CONFIGURATION REGISTER 1 (0x40) CONFIGURATION REGISTER 1 (0x40)[6] TODIS=0, SMBus timeout enabled (default).

[6] TODIS=1, SMBus timeout disabled.

virus protection

To prevent malicious programs or viruses from accessing the ADT7476A register settings, the lock bit can be set. Setting Bit 1 (0x40) of Configuration Register 1 sets the lock bit and locks the key registers. In this mode, some registers can no longer be written to until the ADT7476A is powered down and powered up again.

Voltage measurement input

The ADT7476A has four external voltage measurement channels. It can also measure its own supply voltage, V.

Pins 20 to 23 can measure 5 V, 12 V, and 2.5 V supplies, as well as the processor core voltage VCCP (0 V to 3 V input). The VCC supply voltage measurement is made through the VCC pin (pin 4). The 2.5V input can be used to monitor the supply voltage of the chipset in a computer system.

analog to digital converter

All analog inputs are multiplexed into an on-chip, successive approximation, analog-to-digital converter with 10-bit resolution. The basic input range is 0 V to 2.25 V, but the inputs have built-in attenuators that allow measurement of 2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP without any external components. To allow for tolerances on these supply voltages, the ADC produces a full-scale (768 dec or 300 hex) output for the nominal input voltage, giving it enough headroom to handle overvoltages.

input circuit

The internal structure of the analog input is shown in Figure 24. The input circuit consists of input protection diodes, attenuators, and capacitors, forming a first-order low-pass filter that makes the input immune to high-frequency noise.

Voltage Measurement Register

read

Voltage Limit Register

Associated with each voltage measurement channel is a high and low limit register. Exceeding the programmed upper or lower limit sets the corresponding status bit. Exceeding the limit can also generate SMBALERT interrupts.

Table 9 shows the input range of the analog input and output codes for the 10-bit ADC.

When the ADC is running, it samples and converts a voltage input in 0.7ms, averaging 16 conversions to reduce noise; nominally the measurement takes 11ms.

Extended Resolution Register

Voltage measurements can be made with greater accuracy using the extended resolution registers (0x76 and 0x77). Whenever an extended resolution register is read, the corresponding data in the voltage measurement registers (0x20 to 0x24) is locked until its data is read. That is, if extended resolution is required, the extended resolution register must be read first, followed by the corresponding voltage measurement register.

Additional ADC functions for voltage measurement

There are many other features on the ADT776A for system designers to add flexibility.

off average

For each voltage/temperature measurement read from the value register, 16 readings are taken internally and the results are averaged before placing the result into the value register. When faster conversions are required, setting Bit 4 (0x73) of Configuration Register 2 will turn off averaging. This effectively makes the read 16 times faster, but the read may be louder. The default loop cycle time is 146.5 milliseconds.

Bypass all voltage input attenuators

Setting Bit 5 of Configuration Register 2 (0x73) removes the attenuation circuit from the 2.5 V, VCCP, VCC, 5 V, and 12 V inputs. This allows the user to directly connect external sensors or rescale the analog voltage measurement input for other applications. The input range of the ADC without the attenuator is 0v to 2.25v.

Bypass individual voltage input attenuators

Bits[7:4] of Configuration Register 4 (0x7D) can be used to bypass the individual voltage channel attenuators.

Single channel ADC conversion

While single-channel mode is a test mode that can be used to increase the sampling time of a particular channel, thus helping to analyze the performance of that channel in more detail, it can also have other applications.

Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7476A in single-channel ADC conversion mode. In this mode, the ADT7476A can only read one voltage channel. The selected voltage input is read every 0.7 ms. Select the appropriate ADC channel by writing to Bits[7:5] of the TACH1 Minimum High Byte register (0x55).

Video encoding monitoring

The ADT7476A has five dedicated voltage ID (video code) inputs. These are digital inputs and can be read through the VID/GPIO register (0x43) to determine the required processor voltage or the system used. Five video code inputs support VRM9.x solutions. Additionally, Pin 21 (12v input) can be reconfigured as a sixth VID input to meet future VRM requirements.

VID/GPIO register (0x43)

[0] = video 0, reflecting the logic state of pin 5. [1]=VID1, reflecting the logic state of pin 6.

[2] = Video 2, reflecting the logic state of pin 7.

[3] = Video 3, reflecting the logic state of pin 8.

[4]=VID4, reflecting the logic state of pin 19.

[5] = Segment 5, reconfigurable 12 V input. This bit reads 0 when pin 21 is configured as a 12 V input. This reflects the logic of the state of pin 21 when the pin is configured as VID5.

Video Encoding Input Threshold Voltage

The switching threshold of the VID code input is approximately 1V. For future compatibility, the VID code input threshold can be lowered to 0.6V. Bit 6 (THLD) of the VID/GPIO register (0x43) controls the VID input threshold voltage.

VID/GPIO register (0x43)

[6]THLD=0, VID switch threshold=1v, VOL<0.8v, VIH>1.7v, VMAX=3.3v.

[6]THLD=1, VID switching threshold=0.6V, VOL<0.4V, VIH>0.8V, VMAX=3.3V.

Reconfigure pin 21 as VID5 input

Pin 21 can be reconfigured as the sixth VID code input (VID5) for VRM10 compatible systems. Since the pin is configured as VID5, the 12 V supply cannot be monitored.

Bit 7 of the VID/GPIO register (0x43) determines the function of pin 21. The system or BIOS software can read the status of bit 7 to determine if the system is designed to monitor 12v or the sixth VID input.

VID/GPIO register (0x43)

[7] Wedel = 0, pin 21 is used as 12 V measurement input. Software can read this bit to determine that five video inputs are being monitored. Bit 5 of the VID/GPIO register (0x43) always reads back 0. Bit 0 of Interrupt Status Register 2 (0x42) reflects the 12 V out of limit measurement.

[7] Videl = 1, pin 21 is used as the sixth video code input (VID5). Software can read this bit to determine that six video inputs are being monitored. Bit 5 of Register 0x43 reflects the logic state of pin 21. Bit 0 of Interrupt Status Register 2 (0x42) reflects the change in VID code.

Video encoding change detection function

The ADT7476A has a VID code change detection function. When pin 21 is configured as a VID5 input, changes to the VID code are detected and reported by the ADT7476A in Interrupt Status Register 2 (0x42). Bit 0 is the 12V/VC bit and when set represents a change in VID. The VID code change bit is set when the logic state of the VID input is different from the previous 11 μs. Changes to the VID code are used to generate the SMBALERT interrupt. If the SMBALERT interrupt is not required, setting Bit 0 of the Interrupt Mask Register 2 (0x75) prevents SMBALERT from occurring on VID code changes.

Interrupt Status Register 2 (0x42)

[0] 12V/VC=0, if pin 21 is configured as VID5, a logic 0 means that the VID code has not changed in the last 11µs.

[0] 12V/VC=1, if pin 21 is configured as VID5, a logic 1 means in the last 11µs. If this feature is enabled, an SMBALERT is generated.

Programming GPIOs

The ADT7476A follows the upgrade path from the ADM1027 to the ADT7476A. For consistency between versions, the reference to GPIO5 must be omitted. Therefore, there are six GPIOs as follows: GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 and GPIO6.

Setting Bit 4 of Configuration Register 5 (0x7C) to 1 enables GPIO functionality. This converts all pins configured as VID inputs to general purpose outputs. Write the corresponding VID bit in the VID/GPIO register (0x43) to set the polarity of the corresponding GPIO. GPIO6 can be individually programmed as input or output using Bits[3:2] of Configuration Register 5 (0x7C).

temperature measurement method

Local temperature measurement

The ADT7476A contains an on-chip bandgap temperature sensor whose output is digitized by an on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the temperature registers (Addresses 0x25, 0x26, and 0x27). Since both positive and negative temperatures can be measured, temperature data is stored in offset 64 format or two's complement format, as shown in Table 10 and Table 11. In theory, the temperature sensor and ADC can measure temperatures from -63°C to +127°C (or -61°C to +191°C in the extended temperature range) with 0.25°C resolution. However, this is outside the operating temperature range of the device, so it is not possible over the ADT7476A operating temperature range.

Remote temperature measurement

The ADT7476A can measure the temperature of two remote diode sensors or diode-connected transistors connected to pins 17 and 18, or pins 15 and 16.

The forward voltage of diodes or diode-connected transistors operating at constant current shows a negative temperature coefficient of about -2 mV/°C. Unfortunately, the absolute value of V varies from device to device and requires individual calibration to remove this. Therefore, this technique is not suitable for mass production. The technique used in the ADT7476A is to measure the change in V when the device is operated at two different currents.

This is given by: ΔV=KT/q×1n(N)

in:

K is the Boltzmann constant. q is the charge on the carrier.

T is the absolute temperature in Kelvin. N is the ratio of the two currents.

Figure 25 shows the input signal conditioning used to measure the output of a remote temperature sensor. This image shows an external sensor as a substrate transistor mounted on some microprocessors for temperature monitoring. It can also be discrete transistors like 2N3904/2N3906.

If a discrete transistor is used, the collector is ungrounded and connected to the base. If using a PNP transistor, connect the base to the D- input and the emitter to the D+ input. If using an NPN transistor, the transmitter is connected to the D- input and the base is connected to the D+ input. Figure 26 and Figure 27 show how to connect the ADT7476A to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative side of the sensor is not referenced to ground, but is biased to ground by an internal diode at the D- input.

To measure ΔV, the sensor switches between I and N x I operating currents. The resulting waveform was passed through a 65 kHz low-pass filter to remove noise and passed through a chopper-stabilized amplifier. The amplifier amplifies and corrects the waveform to produce a DC voltage proportional to ΔV. This voltage is measured by the ADC, which outputs the temperature in 10-bit 2's complement format. To further reduce the effect of noise, digital filtering is performed by averaging the results over 16 measurement cycles. It usually takes 38ms to become a remote temperature measurement.

As shown in Table 10, the results of the remote temperature measurement are stored in 10-bit two's complement format. Additional resolution for temperature measurements is stored in Extended Resolution Register 2 (0x77). This will give a temperature reading with a resolution of 0.25°C.

noise filtering

For temperature sensors operating in a noisy environment, it was previously practice to place a capacitor between the D+ and D- pins to help eliminate the effects of noise. However, the large capacitance affects the accuracy of temperature measurements, resulting in a recommended maximum capacitance value of 1000 pF.

Such capacitors reduce noise, but do not eliminate it, which makes it difficult to use the sensor in a noisy environment. In most cases, capacitors are not required because the differential input is inherently highly immune to noise.

Factors Affecting Diode Accuracy

Remote sensing diode

The ADT7476A is designed for substrate transistors or discrete transistors built into processors. Substrate transistors are usually of the PNP type, with the collector connected to the substrate. The discrete type can be a PNP or NPN transistor connected as a diode (base to collector shorted). If an NPN transistor is used, the collector and base are connected to D+ and the emitter is connected to D-. If a PNP transistor is used, the collector and base are connected to D- and the emitter is connected to D+.

To reduce errors due to variations in substrate transistors and discrete transistors, several factors should be considered:

The ideality factor n of a transistor is a measure of the thermal diode's deviation from ideal behavior. The ADT7476A is trimmed to an n value of 1.008. When using a transistor with n not equal to 1.008, calculate the error introduced at the temperature T (°C) using the following formula (see the processor's data sheet for the n value): ΔT=(n−1.008)×(273.15 K+T)

To take this into account, the user can write the ΔT value to the offset register. The ADT7476A then automatically adds or subtracts it to the temperature measurement.

Some CPU manufacturers specify high and low current levels for substrate transistors. The ADT7476A has a high current level of 180µA and a low current level of 11µA. If the current level of the ADT7476A does not match the current level specified by the CPU manufacturer, the offset may need to be removed. The CPU's datasheet suggests if this offset needs to be removed and how to calculate it. This offset can be programmed into the offset register. The caveat is that if multiple offsets must be considered, the algebraic sum of those offsets must be programmed into the offset register. high and low

If discrete transistors are used with the ADT7476A, select the device based on the following criteria for best accuracy:

(1) At the highest operating temperature, the base-emitter voltage is greater than 0.25 V (11 μA).

(2) At the lowest operating temperature, the base-emitter voltage is less than 0.95 V at 180 μA.

(3), the base resistance is less than 100Ω.

(4) Small changes in current gain H (about 50 to 150), indicating tight control of V characteristics. Iron becomes a transistor, such as the equivalent in the 2N3904, 2N3906 or SOT-23 package, which are suitable devices to use.

Eliminate temperature errors

Since the CPU runs faster, it is more difficult to avoid high frequency clocks when routing D+/D- traces around the system board. Even if the recommended layout guidelines are followed, some temperature errors can still be attributed to noise coupled onto the D+/D- lines. Constant high frequency noise usually attenuates or increases the temperature measurement by a linear constant value.

The ADT7476A has temperature offset registers (0x70 and 0x72) for the Remote 1 and Remote 2 temperature channels. By performing a one-time calibration of the system, the user can determine the offset caused by system board noise and zero it out using the offset register. The offset register automatically adds two 8-bit readings to each temperature measurement.

Changing Bit 1 of Configuration Register 5 (0x7C) changes the resolution, so the temperature offset can range from -63°C to +127°C with a resolution of 1°C, or with a resolution of 0.5 °C -63°C to +64°C range. This temperature offset can be used to compensate for linear temperature errors caused by noise.

Temperature Offset Register

ADT7463/ADT7476A Backward Compatibility Mode

All temperature measurements are stored in the zone temperature read registers (0x25, 0x26 and 0x27) in two's complement with a range of -63°C to +127°C by setting Bit 0 of Configuration Register 5 (0x7C) . The temperature limits must be reprogrammed in two's complement.

If a two's complement temperature below -63°C is entered, the temperature is clamped to -63°C. In this mode, the diode fault state remains -128°C=1000 0000, while in the extended temperature range (-63°C to +191°C) the fault state is represented by -64°C=0000 0000.

temperature reading register

[7:6] TDM2 standard, remote 2 temperature LSBs.

[5:4] LTMP, local temperature LSB.

[3:2] TDM1 type, remote 1 temperature LSB.

temperature limit register

Associated with each temperature measurement channel are high and low limit registers. Exceeding the programmed upper or lower limit sets the corresponding status bit. Exceeding the limit can also generate a SMBALERT interrupt (depending on how the interrupt mask register is programmed and assuming SMBALERT is set as an output on the corresponding pin).

Register 0x51, local temperature upper limit = 0x7F default register 0x52, remote 2 temperature lower limit = 0x81 default

Reading temperature from ADT7476A

It is important to note that the temperature can be read from the ADT7476A as an 8-bit value (with 1°C resolution) or as a 10-bit value (with 0.25°C resolution). If only 1°C resolution is required, temperature readings can be taken at any time and in any particular order.

If a 10-bit measurement is required, a 2-bit register needs to be read per measurement. Extended resolution register 2 (0x77) should be read first. This will cause all temperature reading registers to freeze until all temperature reading registers are read from. This will prevent the MSB read from being updated when both lsbs of the MSB are read and vice versa.

Additional ADC function for temperature measurement

There are many other features on the ADT776A for system designers to add flexibility.

off average

For each temperature measurement read from the value register, 16 readings are actually taken internally and the results are averaged before being put into the value register. Sometimes a quick measurement is required. Setting Bit 4 of Configuration Register 2 (0x73) turns off averaging. The default loop cycle time is 146.5 milliseconds.

Single channel ADC conversion

Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7476A in single-channel ADC conversion mode. In this mode, the ADT7476A can only read a single temperature channel. Select the appropriate ADC channel by writing to Bits[7:5] of the TACH1 Minimum High Byte register (0x55).

overtemperature event

Overtemperature events on any temperature channel can be automatically detected and handled in automatic fan speed control mode. Register 0x6A to Register 0x6C are temperature limits. All PWM outputs operate at their maximum value when the temperature exceeds their temperature limit.

PWM duty cycle (Register 0x38, Register 0x39, and Register 0x3A). This effectively runs the fan at the fastest speed allowed.

Bits[7:5] of Configuration Register 5 (0x7C) can be used. THERM can also be disabled by:

(1) Write -64°C to the appropriate thermal temperature limit in offset 64 mode. The fans run at this speed until the temperature drops below the thermal lag. This can be disabled by setting Bit 2 (boost bit) in Configuration Register 3 (0x78). The hysteresis value for the thermal temperature limit is the value programmed into the hysteresis registers (0x6D and 0x6E). The default hysteresis value is 4°C.

(2) Write -128°C to the appropriate thermal temperature limit in two's complement mode.

Limits, Status Registers and Interrupts

limit value

Associated with each measurement channel on the ADT7476A are high and low limits. These can form the basis for system status monitoring; status bits can be set for any violation of limits and detected by polling the device. Alternatively, an SMBALERT interrupt can be generated to flag an out-of-limit condition to the processor or microcontroller.

8 bit limit

Below is a list of the 8-bit limitations on the ADT7476A.

Voltage Limit Register

temperature limit register

Thermal Timer Limit Register

16-bit limit

The fan speed measurement is a 16-bit result. The fan speed limit is also 16 bits, consisting of a high byte and a low byte. Because the fan running at speed or stall is usually the only condition of interest, there is only a high limit to the fan speed.

Because the fan speed cycle is actually measured, exceeding this limit indicates a slow or stalled fan.

Fan Limit Register

Compare out of limit

After all limits have been programmed, the ADT7476A can be enabled for monitoring. The ADT7476A measures all voltage and temperature measurements in loop mode and sets the appropriate status bits for the limit violation. Tachometer measurements are not part of the loop cycle. The comparison is done differently depending on whether the measured value is compared to an upper or lower limit.

upper limit:> for comparison

Lower limit: ≤ for comparison

The voltage and temperature channels use window comparators for error detection and therefore have high and low limits. Only the low limit is used for fan speed measurement. This fan limit is only required in manual fan control mode.

Analog monitoring cycle time

The analog monitor cycle begins when a 1 is written to the start bit (bit 0) of configuration register 1 (0x40). The ADC measures each analog input in turn, and after each measurement is completed, the results are automatically stored in the corresponding value registers. This loop monitoring loop will continue unless disabled by writing 0 of Configuration Register 1 to Bit 0.

Since ADCs typically run freely in this manner, the time it takes to monitor all analog inputs is usually not critical, as the latest measurement for any input can be read out at any time.

For applications where monitoring cycle time is important, it can be easily calculated.

The total number of channels measured is

• Four dedicated supply voltage inputs

• Supply voltage (V pin) cocos

• local temperature

• Two remote temperatures

As mentioned earlier, the ADC performs cyclic conversions, taking 11 ms for each voltage measurement, 12 ms for local temperature readings, and 39 ms for remote temperature readings. Therefore, the total monitoring cycle time for average voltage and temperature monitoring is nominally: (5 × 11) + 12 + (2 x 39) = 145 ms, the fan speed measurement is done in parallel and out of sync with the analog measurement.

status register

The result of the limit comparison is stored in Interrupt Status Register 1 and Interrupt Status Register 2. The status register bits for each channel reflect the status of the last measurement and limit comparison on that channel. If the measured value is within the limits, the corresponding status register bit is cleared to 0. If the measurement exceeds the limit, the corresponding status register bit is set to 1.

The status of the various measurement channels can be polled by reading the status register over the serial bus. In Interrupt Status Register 1 (0x41), Bit 7 (OOL), a 1 indicates that an out-of-limit event was flagged in Interrupt Status Register 2. This means that the user also needs to read the Interrupt Status Register 2. Alternatively, pin 10 or pin 14 can be configured as an SMBALERT output.

This hard interrupt automatically notifies the system supervisor that the limit is exceeded. Whenever the error condition that caused the interrupt is cleared, reading the status register clears the corresponding status bit. Status register bits are sticky. Whenever a status bit is set, indicating that a limit condition has been exceeded, it remains set even if the event that caused it has disappeared (until read).

The only way to clear the status bits is to read the status register after the event disappears. The interrupt mask registers (0x74 and 0x75) allow masking of a single interrupt source to cause SMBALERT. However, if one of the masked interrupt sources exceeds the limit, its associated status bit will be set in the status register.

Interrupt Status Register 1 (0x41)

Bit 7 (OOL) = 1, indicating that a bit in Interrupt Status Register 2 is set and Interrupt Status Register 2 should be read.

Bit 6 (R2T) = 1, the remote 2 temperature upper or lower limit has been exceeded.

Bit 5 (LT) = 1, the local temperature upper or lower limit has been exceeded.

Bit 4 (R1T) = 1, the remote 1 temperature upper or lower limit has been exceeded.

Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded.

Bit 2 (VCC) = 1, V upper or lower limit has been exceeded. cocos islands

Bit 1 (VCCP) = 1, V upper or lower limit has been exceeded. central counterparty

Bit 0 (2.5 V) = 1, the 2.5 V high or low limit has been exceeded If the 2.5 V input is configured as THERM, this bit indicates

thermal state.

Interrupt Status Register 2 (0x42)

Bit 7 (D2) = 1, indicating that the D2+/D2- input is open or shorted.

Bit 6 (D1) = 1, indicating that the D1+/D1- input is open or shorted.

Bit 5 (F4P) = 1, indicating that fan 4 has dropped below the minimum speed. Alternatively, indicate thermal limits. Exceeds if using THERM function. Alternatively, indicate the state of GPIO6.

Bit 4 (Fan 3) = 1, indicating that Fan 3 has dropped below the minimum speed.

Bit 3 (FAN2) = 1, indicating that fan 2 has dropped below the minimum speed.

Bit 2 (FAN1) = 1, indicating that Fan 1 has dropped below the minimum speed.

Bit 1 (OVT) = 1, indicating that the overtemperature limit has been exceeded.

Bit 0 (12V/VC) = 1, indicating that the 12 V high or low limit has been exceeded. If the VID code change function is used, this bit indicates a VID code change on the VID0 to VID4 inputs.

SMBALERT interrupt behavior

The ADT7476A can be polled for status and can also generate a SMBALERT interrupt for a limit exceeded condition. It is important to pay attention to the behavior of the SMBALERT output and status bits when writing interrupt handler software.

Figure 29 shows the behavior of the SMBALERT output and sticky status bits. Once the limit is exceeded, the corresponding status bit will be set to 1. The status bits remain set until the error condition disappears and the status register is read. Status bits are called sticky bits because they remain set until they are read by software. This ensures that if the software periodically polls the device, events that exceed the limit are not missed. Notice:

(1) The SMBALERT output remains low for the entire duration of the read out-of-limit until the status register is read. This has implications for how software handles interrupts.

(2), the overheating event is not sticky. They reset as soon as the overtemperature condition ceases.

Handling SMBALERT interrupts

To prevent the system from being tied by interrupt servicing, it is recommended to handle the SMBALERT interrupt as follows:

1. Detect the SMBALERT assertion.

2. Enter the interrupt handler.

3. Read the status register to identify the source of the interrupt.

4. Mask the interrupt source by setting the appropriate mask bits in the interrupt mask registers (0x74 and 0x75).

5. Take the appropriate action for the given interrupt source.

6. Exit the interrupt handler.

7. Periodically poll the status register. If an interrupt status bit is cleared, reset the corresponding interrupt mask bit to 0. This results in the behavior of the SMBALERT output and status bits as shown in Figure 30.

Mask interrupt sources

Interrupt Mask Register 1 (0x74) and Interrupt Mask Register 2 (0x75) allow masking of individual interrupt sources to prevent SMBALERT interrupts. Note: Masking the interrupt source only prevents the SMBALERT output from being asserted; set the appropriate status bits normally.

Interrupt Mask Register 1 (0x74)

Bit 7 (OOL) = 1, masks SMBALERT for any alert condition flagged in Interrupt Status Register 2.

Bit 6 (R2T) = 1, mask SMBALERT for remote 2 temperature.

Bit 5 (LT) = 1, mask SMBALERT for local temperature.

Bit 4 (R1T) = 1, mask SMBALERT for remote 1 temperature.

Bit 3 (5 V) = 1, shields the SMBALERT of the 5 V channel.

Bit 2 (VCC) = 1, mask the SMBALERT of the V channel. cocos islands

Bit 1 (VCCP) = 1, mask the SMBALERT of the V channel. Central opponent azimuth 0 (2.5V) = 1, shield the SMBALERT of 2.5V/THERM.

Interrupt Mask Register 2 (0x75)

Bit 7 (D2) = 1, SMBALERT for shield diode 2 error. Bit 6 (D1) = 1, SMBALERT for shield diode 1 error.

Bit 5 (Fan 4) = 1, shields the SMBALERT for Fan 4 failure.

If the TACH4 pin is used as a thermal input, this bit masks SMBALERT for thermal events. If the TACH4 pin is used as GPIO6, setting this bit will mask the interrupts associated with GPIO6.

Bit 4 (Fan 3) = 1, shields the SMBALERT of Fan 3.

Bit 3 (FAN2) = 1, shields the SMBALERT of fan 2.

Bit 2 (FAN1) = 1, shields the SMBALERT of Fan 1.

Bit 1 (OVT) = 1, shields SMBALERT from overheating (over thermal temperature limit).

Bit 0 (12V/VC) = 1, mask 12 V channel or SMBALERT for video code change, depending on the function used.

Enable SMBALERT interrupt output

By default, the SMBALERT interrupt function is disabled. Pin 10 or pin 14 can be reconfigured as an SMBALERT output to signal an out-of-limit condition.

Pin Assignment Thermal Function

Pin 14 on the ADT7476A has four possible functions:

SMBALERT, THERM, GPIO6 and TACH4. The user selects the desired function by setting Bit 0 and Bit 1 of Configuration Register 4 (0x7D).

If THERM is enabled on bit 1, configure register 3 (0x78):

(1), the pin 22 becomes hot.

(2) If pin 14 is configured as THERM on bit 0 and bit 1 of configuration register 4 (0x7D), THERM is enabled on that pin.

If THERM is not enabled:

(1), Pin 22 becomes 2.5 V measurement input.

(2) If pin 14 is configured as THERM, THERM on this pin is disabled.

heat as input

When THERM is configured as an input, the user can time the assertion on the THERM pin. This is useful for connecting to the CPU's PROCHOT output to measure system performance.

The user can also set the ADT7476A to run the fan at 100% speed when the external drive thermal pin is low. Fans run around to stay 100% for the time the hot plug is pulled low.

This is done by setting the BOOST bit (bit 2) in configuration register 3 (0x78) to 1. This function only works when the fan is already running (eg in manual mode, when the current duty cycle is above 0x00) or in auto mode when the temperature is above T. Min If the temperature is below T or the manual duty cycle min mode is set to 0x00, the external pull-down heat has no effect. See Figure 31 for more information.

hot timer

The ADT7476A has an internal timer to measure the thermal assertion time. For example, the THERM input can be connected to the PROCHOT output of a Pentium 4 CPU to measure system performance. The thermal input can also be connected to the output of the trigger point temperature sensor.

The timer starts when the thermal input to the ADT7476A is asserted and stops when the thermal is de-asserted. The timer counts heat times cumulatively, i.e. the timer continues to count on the next heat assertion. The THERM timer continues to accumulate the THERM assertion time (if cleared) before the timer is read, or until full scale is reached. If the counter reaches full scale, it stops at that reading until cleared.

The 8-bit thermal timer status register (0x79) is designed as follows:

In the first THERM assertion, bit 0 is set to 1. Once the accumulated thermal assertion time exceeds 45.52 ms, bit 1 of the thermal timer is set, and bit 0 now becomes the LSB of the timer with a resolution of 22.76 ms (see Figure 32).

When using the heat timer, please note the following: After the heat timer is read (0x79)

1. The content of the timer is cleared when it is read.

2. Bit 0 of the thermal timer is set to 1 because a thermal assertion is occurring.

3. The heat timer increments from zero.

4. If the thermal timer limit register (0x7A) = 0x00, set the F4P bit.

Generate SMBALERT interrupt from hot timer event

The ADT7476A can be programmed when the thermal timer limit has been exceeded. This allows system designers to ignore short, uncommon THERM assertions when capturing longer THERM timer events. Register 0x7A is the thermal timer limit register. This 8-bit register allows setting a limit from 0 seconds (the first THERM assertion) to 5.825 seconds before generating the SMBALERT. Compare the THERM timer value with the contents of the THERM timer limit register. If the hot timer value exceeds the hot timer limit value, then the F4P bit (bit 5) of the Interrupt Status Register 2 is set and an SMBALERT is generated.

Note: Depending on which pins are configured as thermocouple timers, set mask register 2 (0x75) or bit 0 of the F4P bit (bit 5) of mask register 1 (0x74) if the timer limit is exceeded.

Figure 33 is a functional block diagram of the thermal timer, limits and associated circuitry. Writing a value of 0x00 to the thermal timer limit register (0x7A) causes an SMBALERT to be generated on the first THERM assertion. The thermal timer limit value of 0x01 cumulatively generates a SMBALERT thermal assertion for more than 45.52ms.

Configuration related thermal behavior

1. Configure the desired pins as thermal timer inputs.

Setting Bit 1 (Thermal Timer Enable) of Configuration Register 3 (0x78) enables the thermal timer monitoring function. This feature is disabled on pins 14 and 22 by default. Setting Bit 0 and Bit 1 of the Configuration (PIN14FUNC) register 4 (0x7D) enables the thermal timer output function on pin 22 (bit 1 of the Configuration Register 3, THERM must also be set). Pin 14 can also be used as tachometer 4 .

2. Select the desired fan behavior for the thermal timer event.

Assuming the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (0x78) causes all fans to run at 100% duty cycle when THERM is asserted. This allows for cooling of the failsafe system. If this bit is 0, the fan operates at its current setting and is not affected by thermal events. If the fan is not already running when THERM is asserted, the fan will not run at full speed.

3. Select whether the THERM timer event should generate a SMBALERT interrupt.

Set bit 5 (F4P) of mask register 2 (0x75) or bit 0 of mask register 1 (0x74) (depending on which pins are configured as thermal timers) to mask SMBALERTs when the thermal timer limit is exceeded . This bit should be cleared if SMBALERTs based on THERM events are required.

4. Select the appropriate thermal limit value.

This value determines whether a SMBALERT is generated on the first THERM assertion, or just beyond the cumulative THERM assertion time limit. A value of 0x00 causes a SMBALERT to be generated on the first THERM assertion.

5. Select the thermal monitoring time.

This value specifies how often the software at the operating system or BIOS level checks the THERM timer. For example, the BIOS can read the THERM timer every hour to determine the thermal assertion time. For example, if the total thermal assertion time is <22.76 ms at hour 1, >182.08 ms at hour 2, and >5.825 s at hour 3, the system performance is degrading. Important because THERM asserts more frequently per hour. Alternatively, operating system or BIOS level software can be used when the system is powered on. If a SMBALERT is generated due to exceeding the THERM timer limit, another timestamp can be taken. The time difference can be calculated as a fixed thermal timer limit time. For example, if it takes a week to exceed the thermal timer limit of 2.914 seconds, and the next time it only takes 1 hour, then system performance will be severely degraded.

By configuring the THERM pin as an output, in addition to monitoring thermal as an input, the ADT7476A has the option to drive thermal low as an output. When PROCHOT is bidirectional, it is possible to use THERM to limit the processor by asserting PROCHOT. The user can pre-program critical system thermal limits. The thermal assertion is low if the temperature exceeds the thermal limit by 0.25°C. If the temperature is still above the thermal limit for the next monitoring cycle, THERM remains low. The heat is kept low until the temperature is at or below the thermal limit. Because the temperature of this channel is measured only once per monitoring cycle, the THERM claim is guaranteed to remain low for at least one monitoring cycle.

The thermal pin can be configured to assert low if the remote 1, local or remote 2 thermal temperature limit exceeds 0.25°C. The thermal temperature limit registers are located in Register 0x6A, Register 0x6B, and Register 0x6C. Setting Bits[5:7] of Configuration Register 5 (0x7C) enables Remote 1, Local and Remote 2 temperature channels respectively. Figure 34 shows the occurrence of critical overtemperature.

Another way to disable THERM is to program the THERM temperature limit to -63°C or lower in offset 64 mode, or -128°C or lower in two's complement mode; that is, for respectively less than THERM temperature limit of -63°C or -128°C, THERM disabled.

Enable and disable THERM on a single channel

THERM can be enabled/disabled for individual or combined temperature channels using Bits[7:5] of Configuration Register 5 (0x7C).

thermal hysteresis

Thermal hysteresis is disabled by setting Bit 0 of Configuration Register 7 (0x11).

If thermal hysteresis is enabled and thermal is disabled (Configuration Register 4, Bit 2, 0x7D), the thermal pin will not be asserted low when a thermal event occurs. If thermal hysteresis is disabled, and thermal is disabled (bit 2 of Configuration Register 4 0x7D), and assuming the appropriate pins are configured for thermal, the thermal pin is asserted low when a thermal event occurs.

If both thermal hysteresis and thermal hysteresis are enabled, the thermal output will be asserted as expected.

Hot operation in manual mode

In manual mode, a thermal event will not cause the fan to run at full speed unless Bit 3 of Configuration Register 6 (0x10) is set to 1.

Alternatively, Bit 3 of Configuration Register 4 (0x7D) can be used to select the PWM speed on a THM event (100% or maximum PWM).

Bit 2 in Configuration Register 4 (0x7D) can be set to disable the effect of thermal events on the fan.

Fan drive with PWM control

The ADT7476A uses pulse width modulation (PWM) to control the fan speed. This relies on changing the duty cycle (or on/off ratio) of the square wave applied to the fan to change the fan speed. The external circuitry required to drive the fan using PWM control is very simple. For a 4-wire fan, the PWM driver may only need a pull-up resistor. In many cases, the 4-wire fan PWM input has a built-in pull-up resistor.

The PWM frequency of the ADT7476A can be set to a choice of low frequency or a single high PWM frequency. The low frequency option is used for 3-wire fans, while the high frequency option is usually used for 4-wire fans.

For a 3-wire fan, only one N-channel MOSFET driver is required. The specification of the MOSFET depends on the maximum current required by the fan being driven and the input capacitance of the FET. Since a 10 kΩ (or larger) resistor must be used for the PWM pull-up, a FET with a larger input capacitance can cause distortion of the PWM output and adversely affect the fan control range. This is only required when using high frequency pulse width modulation mode.

A typical laptop fan is rated at 170mA, so SOT devices can be used where board space is a concern. In desktops, fans typically pump 250mA to 300mA each. If driving multiple fans in parallel or driving larger server fans from one PWM output, the MOSFETs must handle the higher current requirements. The only other stipulation is that the MOSFET should have gate voltage drive, V<3.3 V, for direct connection to the PWM output pins. The MOSFET should also have low on-resistance to ensure that there is no significant voltage drop across the FET, which will reduce the voltage applied to the fan and thus reduce the maximum operating speed of the fan. Figure 35 shows how to drive a 3-wire fan using PWM control.

Figure 35 uses a 10 kΩ pull-up resistor as the tachometer signal. This assumes the tach signal is an open collector from the fan. In all cases, the TACH signal from the fan must be kept below 5.5 V to prevent damage to the ADT776A.

Figure 36 shows a fan drive circuit using NPN transistors such as the general purpose MMBT2222. While these devices are inexpensive, they tend to have lower current handling capabilities and higher on-resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the current requirements of the fan. Make sure the base resistor is chosen so that the transistor saturates when the fan is powered on.

Since the fan drive circuit in a 4-wire fan doesn't turn on or off like in previous PWM driven/powered fans, the internal drive circuit is always on and uses the PWM input as a signal instead of a power supply. This allows the internal fan drive circuitry to outperform 3-wire fans, especially for high frequency applications.

Figure 37 shows a typical drive circuit for a 4-wire fan.

Drive two fans from PWM3

The ADT7476A has four tachometer inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is used in the system, it should be paralleled with the third fan, driven from the PWM3 output.

Figure 38 shows how to drive two fans in parallel using low-cost NPN transistors. Figure 39 shows the equivalent circuit, since the MOSFET can handle up to 3.5A, the user can directly connect another fan in parallel with the first fan. When designing driver circuits with transistors and FETs, care should be taken to ensure that the PWM outputs do not require current sources and that they sink less than the 5mA maximum specified on the datasheet.

Drive up to three fans from PWM3

Fan speed measurement and PWM channel; for example, TACH1 is synchronized with PWM1. Both TACH3 and TACH4 are synchronized with PWM3, so PWM3 can drive both fans. Alternatively, PWM3 can be programmed to synchronize Tach 2, Tach 3, and Tach 4 to the PWM3 output. This allows the PWM3 to drive two or three fans. In this case, the driver circuit looks the same, as shown in Figure 38 and Figure 39. The sync bit in Register 0x62 enables this feature. Use MOSFETs. (SYNC) Enhanced Acoustics Register 1 (0x62)[4] SYNC=1 to synchronize Tach2, Tach3 and Tach4 with PWM3.

When used with 4-wire fans, no synchronization is required in high frequency mode.

Arrangement of 3-wire fans

Figure 40 shows how to lay out the common circuit for a 3-wire fan.

Tachometer input

Pin 9, Pin 11, Pin 12, and Pin 14 (when configured as tachometer inputs) are high impedance inputs for fan speed measurement.

Signal conditioning in the ADT7476A adjusts the slow rise and fall times of the typical output of a fan tachometer. The maximum input signal range is 0 V to 5.5 V, even if V is 3.3 V. In cases where these inputs are supplied from fan outputs in excess of 0 V to 5.5 V, resistive attenuation or diode clamping of the fan signal must be included to keep the inputs within acceptable limits.

Figure 41 through Figure 44 show the circuits for the most common fan tachometer outputs.

If the fan tachometer output has a resistor pulled up to V, it can be connected directly to the fan input, as shown in Figure 41.

If the fan output has a resistive puller up to 12V or other voltages greater than 5.5V, the fan output can be clamped using a Zener diode, as shown in Figure 42. The Zener diode voltage should be chosen so that it is greater than the V of the tachometer input, but less than 5.5 V, allowing a voltage tolerance for the Zener. A value between 5 V and 5.5 V is suitable.

If the fan has a strong pull-up (less than 1kΩ) to the 12V or totem pole output, a series resistor can be added to limit the zener current as shown in Figure 43.

Alternatively, resistive attenuators can be used, as shown in Figure 44. The choice of R1 and R2 should ensure that:

2 V < VPULL-UP × R2 / (RPULL-UP + R1 + R2) < 5.5 V

The input resistance of the fan input to ground is nominally 160 kΩ and should be taken into account when calculating the resistance value.

When the pull-up voltage is 12v and the pull-up resistor is less than 1kΩ, suitable values for R1 and R2 are 100kΩ and 40kΩ, respectively. This produces a high input voltage of 3.42V.

The fan counter does not directly count the fan speed output pulse, as the fan speed may be less than 1000 rpm and it will take several seconds to accumulate a fairly large and accurate count. Instead, the period of the fan speed is measured by gating a 90 kHz on-chip oscillator to the input of a 16-bit counter for N cycles of the fan speed output (Figure 45), so the accumulated count is actually the same as the fan speed period proportional to the fan speed.

N, the number of pulses counted is determined by the setting of the tachometer pulse register (0x7B) per revolution. This register contains two bits per fan, allowing one, two (default), three or four tach pulses to be counted.

Fan Tachometer Read Register

The fan tachometer reads as a 16-bit value consisting of 2 bytes read from the ADT7476A.

Read fan speed from ADT7476A

The measurement of fan speed consists of reading a 2 register per measurement. The low byte should be read first. This causes the high byte to be frozen until both the high and low byte registers are read, preventing false tachometer readings. The fan tachometer reading register reports the 11.11 μs period clock (90 kHz) gated to the fan speed counter from the rising edge of the first fan tachometer pulse to the rising edge of the third fan tachometer pulse (assuming two pulses per revolution are counted) oscillator) number.

Because the device is basically measuring fan RPM cycles, the higher the count, the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates that the fan has stalled or is running very slowly (<100 rpm).

upper limit:> for comparison

Since the actual fan speed cycle is being measured, falling below the fan speed limit of 1 will set the appropriate status bits and can be used to generate SMBALERT.

There are the following considerations for measuring fan speed: When the ADT7476A starts up, the speed measurement locks. In fact, an internal read of the low byte has been done for each tachometer input. The net result is that all tachometer readings are locked until the high byte is read from the corresponding tachometer register. All tachometer related interrupts will also be ignored until the appropriate high byte is read.

Once the corresponding high byte is read, the tachometer measurement is unlocked and interrupts are handled normally.

Fan Speed Limit Register

The Fan Speed Limit Register is a 16-bit value consisting of two bytes.

Fan speed measurement rate

Fan tachometer readings are usually updated every second.

Once set, the fast bit (bit 3) of configuration register 3 (0x78) updates the fan tachometer reading every 250 ms.

DC bit

If any fans are not driven by a PWM channel, but are powered directly by 5v or 12v, their relevant dc bits should be set in Configuration Register 3. This allows fans connected directly to the DC power source to take continuous tachometer readings. After enabling high frequency mode in a 4-wire fan, there is no need to set the DC bit as this is done automatically internally.

Calculate fan speed

Assuming the fan has two pulses per revolution and the ADT7476A is programmed to measure two pulses per revolution, the fan speed is given by

Fan speed (RPM) = (90000×60)/fan tachometer reading, where the fan tachometer reading is a 16-bit fan tachometer reading.

example:

TACH1 high byte (0x29) = 0x17 TACH1 low byte (0x28) = 0xFF

What is the speed of fan 1 at rpm?

Fan 1 RPM reading = 0x17FF = 6143 (decimal)

RPM = (f x 60) / Fan 1 RPM reading

Speed = (90000×60)/6143 Fan speed = 879 rpm

tach pulse/rev

Different models of fans can output one, two, three or four speed pulses per revolution. Once the number of fan tach pulses is determined, it can be programmed into each fan's tach pulse register (0x7B). Alternatively, this register can be used to determine the number of pulses output per revolution for a given fan. By plotting fan speed measurements at 100% speed at different pulse per revolution settings, the smoothest graph with the least ripple determines the correct pulse per revolution value.

Fan Pulse Register per Revolution

[1:0] Fan 1 default = 2 pulses per revolution.

[3:2] Fan 2 default = 2 pulses per revolution.

[5:4] Fan 3 default = 2 pulses per revolution.

[7:6] Fan 4 default = 2 pulses per revolution.

00 = 1 pulse per revolution.

01 = 2 pulses per revolution.

10 = 3 pulses per revolution.

11 = 4 pulses per revolution.

fan rotation

The ADT7476A has a unique fan rotation feature. It spins the fan with a 100% PWM duty cycle until two tachometer pulses are detected at the tachometer input. Once two tach pulses are detected, the PWM duty cycle will reach the expected operating value, eg 33%. Fans have different rotational characteristics and require different times to overcome inertia. The advantage of the ADT7476A is that it runs the fan fast enough to overcome inertia and is quieter when spinning than a fan programmed to spin for a given amount of time.

Fan startup timed out

To prevent spurious interrupts when the fan starts up (because it is below operating speed), the ADT7476A includes a fan-on time-out function. During this time, the ADT7476A looks for two tach pulses. An interrupt is generated if two tach pulses are not detected.

The fan startup timeout can be disabled by setting Bit 5 (fspdi) of Configuration Register 1 (0x40).

PWM1, PWM2, PWM3 configuration (0x5C, 0x5D, 0x5E)

[2:0] Rotation, PWM1=0x5C, PWM2=0x5D, PWM3=0x5E start timeout.

000=No startup timeout

001=100ms

010=250ms default value

011=400ms

100 = 667 milliseconds

101 = 1 second

110 = 2 seconds

111 = 4 seconds

Disable fan startup timeout

While fan start makes fan spin quieter than static time spin, there is an option to use a fixed spin rise time. Setting Bit 5 (fspdi) in Configuration Register 1 (0x40) to 1 will disable acceleration for both tachometer pulses. Instead, the fan spins for a fixed time period selected in Register 0x5C to Register 0x5E.

PWM logic state

The PWM output can be programmed to be 100% duty cycle high (no inversion) or 100% duty cycle low (inversion).

Program the automatic fan speed control loop

For a more efficient understanding of the automatic fan speed control loop, it is recommended that you use the ADT7476A evaluation board and software while reading this section.

This section provides system designers with an understanding of the automatic fan control loop and provides step-by-step guidance for effective evaluation and selection of key system parameters. To optimize system characteristics, designers need to consider system configuration, including the number of fans, their locations, and the temperatures measured in a particular system.

The mechanical or thermal engineer responsible for the thermal characterization of the system should also be involved at the beginning of the system development process.

Overview of Manual Fan Control

In unusual circumstances, it may be necessary to manually control the speed of the fan. Since the ADT7476A has an SMBus interface, the system can read all necessary voltage, fan speed, and temperature information and use this information to control the fan speed by writing to the corresponding fan's PWM current duty cycle registers (0x30, 0x31, and 0x32). Bits[7:5] of the PWMx configuration registers (0x5C, 0x5D, 0x5E) are used to set the fan for manual control.

Hot operation in manual mode

In manual mode, if the temperature is above the pro-temperature limit, the fans automatically speed up to max PWM or 100% PWM, whichever configures the appropriate fan channel.

Overview of Automatic Fan Control

The ADT7476A can automatically control the fan speed based on the measured temperature. Once the initial parameters are set, this can be done independently of CPU intervention.

The ADT7476A has a local temperature sensor and two remote temperature channels that can be connected to thermal diodes on the CPU chip (available on Intel Pentium class and other CPUs). These three temperature channels serve as the basis for automatic fan speed control that uses pulse width modulation (PWM) to drive fans.

Automatic fan speed control reduces noise by optimizing fan speed based on precisely measured temperature. Lowering the fan speed can also reduce system current consumption. The automatic fan speed control mode is very flexible due to the number of programmable parameters including T and min

T. The T and T values of the temperature channel, therefore, for a given fan, are critical as they define the thermal characteristics of the system. Thermal validation of the system is one of the most important steps in the design process, so these values should be chosen carefully. RANGE MIN RANGE Figure 47 gives a top-level overview of the automatic fan control circuit on the ADT7476A. From a system-level perspective, up to three system temperatures can be monitored and used to control three PWM outputs. Three PWM outputs can be used to control up to four fans. The ADT7476A allows monitoring of the speed of the four fans. Each temperature channel has a thermal calibration block that allows designers to individually configure the thermal characteristics of each temperature channel. For example, the designer can decide to run the CPU fan when the CPU temperature exceeds 60°C, and the case fan when the local temperature rises above 45°C.

At this stage, the designer has not assigned these thermal calibration settings to specific fan drive (PWM) channels. The right side of Figure 47 shows the fan-specific controls. Designers can individually control parameters such as minimum PWM duty cycle, fan speed fault threshold, and even ramp control of the PWM output. Thus, automatic fan control finally allows for elegant fan speed changes that the system user cannot perceive.

The ADT7476A is...

The ADT7476A is a dBCool™ Remote Thermal Controller and Voltage Monitor

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