It shows that a reliable and compact high-performance configuration bitstream storage and transmission solution is essential for high-density FPGAs. Platform Flash XL is the industry's highest performance configuration and storage device optimized for high performance FPGA configurations. Platform Flash XL integrates 128 Mb of in-system programmable flash storage and performance capabilities, configurable in a small footprint FT64 package. A power-up burst read mode and dedicated I/O power supplies enable the platform Flash XL to work seamlessly with the native SelectMAP configuration interface. A wide 16-bit data bus transfers the FPGA configuration bit stream at up to 800mb/s without wait states.
Platform Flash XL is only supported for use with Virtex-5 or Virtex-6 FPGAs. Not supported for use with older Virtex series, Spartan® series or AES encrypted bitstreams.
Platform Flash XL is a non-volatile flash storage solution optimized for FPGA configuration. The device provides a ready-to-wait signal to synchronize the initiation of the FPGA configuration process, improving system reliability and simplifying board design. Platform Flash XL can download an XC5VLX330 bit stream (79704832 bits) in less than 100 milliseconds, making Platform Flash XL's configuration performance ideal for PCI Express endpoints and other high-performance applications.
Platform Flash XL is a single-chip configuration solution with additional system-level functionality. The standard NOR flash interface (Figure 2) and support for Common Flash Interface (CFI) queries provide industry-standard access to the device memory space. The 128mb capacity of the platform Flash XL can typically hold one or more FPGA bitstreams. Any memory space not used for bitstream storage can be used to hold general purpose data or embedded processor code.

notes:
one. System considerations can reduce the configuration clock frequency below the device's maximum clock frequency. To determine the maximum configuration clock frequency, check the selected I/O voltage range (V), the clock high output active time (T), and the minimum clock period (T) that the FPGA chooses to map the setup time. KH DDT KHQV Corporation Platform Flash XL Provides Reliable, High-Performance FPGA Configuration Platform Flash XL Supports Integration with Xilinx X-Ref Targets -
Design and debug tool suite. The iMPACT application is included in the ISE software and supports indirect in-system programming of the platform Flash XL via the IEEE Standard 1149.1 (JTAG) port on the FPGA for prototyping

Flash Architecture Overview Platform Flash XL is a 128 Mb (8 Mb x 16) non-volatile flash memory. The device uses a 1.8V core (V) power supply for in-system programming. A separate I/O (V) supply allows the I/O to operate at 3.3V or 2.5V. An optional 9V power supply speeds up factory programming. Due Diligence DDT PP Common Flash Interface (CFI) provides access to device memory. In addition, the platform Flash XL supports multiple read modes. The 23-bit address bus provides random read access to each 16-bit word. Accelerated page mode reading with four words occupying each page. The device is powered up in synchronous burst read mode, capable of continuous reading at rates up to 54MHz.
The platform Flash XL has a multi-bank architecture. An array of 131 individually erasable blocks is divided into groups of 168mb. 15 main blocks contain a uniform block of 64 Kwords, 1 parameter block contains 7 main blocks of 64 Kwords, plus 4 parameter blocks of 16 Kwords.
Note: The device is electronically erasable at the block level and programmable word by word.
The multi-bank architecture allows for dual operations - a read operation can take place in one bank, while a program or erase operation takes place in the other bank. However, only one bank is allowed to be in program or erase mode at a time. Burst reads are allowed to cross bank boundaries.

Address Input (A22-A0)
The address input selects the word in the memory array to be accessed during a bus read operation. During bus write operations, they control the commands sent to the program/erase controller's command interface.
Data Input/Output (DQ15-DQ0)
Data I/O outputs the data stored at the selected address during bus read operations, or input commands or data to be programmed during bus write operations.
Chip Enable (E)
The chip enable input activates memory control logic, input buffers, decoders, and sense amplifiers. When chip enable is V and reset is V, the device is in active mode. When chip enable is V, the memory is deselected, the output is high impedance, and power consumption is reduced to standby levels. Illinois IH IH Output Enable (G)
During a bus read operation of the memory, the output enable input controls the data output. Before the first address latch sequence (FALS) begins, the output enable input must be held low until the clocks begin toggling.
Write Enable (W)
The Write Enable input controls bus write operations for the memory command interface. Data and address inputs are latched on the rising edge of chip enable or write enable, whichever occurs first.

notes:
one. For more information, see Waveforms in the DC and AC Parameters section.
Clock (K)
The clock input synchronizes the memory to the FPGA during synchronous read operations. When Latch Enable is V, the address is latched on the clock edge (rising or falling depending on the configuration setting). During asynchronous read and write operations, the clock is ignored. Illinois Ready/Waiting (Ready/Waiting)
Note that the safe-ready wait requires an external pull-up resistor to VDDQ. The external pull-up resistor must be strong enough to ensure a clean, low-to-high transition in less than a microsecond (TRWRT) when the ready-wait pin is released to a high-impedance state.
Ready-waiting can perform one of two functions. By default, READY_WAIT is an input/open-drain ready signal that coordinates the initiation of device-synchronous read operations and the initiation of the FPGA configuration sequence. Optionally, READY_WAIT can be dynamically configured to output a wait signal indicating a wait condition during a synchronous read operation.
On a power-on reset (POR) or RP pin reset event, the device driver READY_ waits for V until the device is ready to initiate a synchronous read or receive a command. When the device reaches the internal ready state from the reset state, the ready wait is released to a high impedance state (an external pull-up resistor to V is required to externally pull the ready wait signal to a valid input high). The device will wait for the ready input to become a valid high input before allowing a synchronous read or accepting a command. Connect READY_WAIT to the FPGA INIT_B pin in the wire and circuit to create a handshake that coordinates the initiation of the device synchronous read and the initiation of the FPGA configuration sequence. Illinois DDT When READY_WAIT is an input/open-drain ready signal, the system can drive READY_WAIT to V to restart a synchronous read operation. A valid address must be provided to the device for reinitialized synchronous read operations. Illinois Optionally, READY_WAIT can be configured as an output that signals a wait condition during a synchronous read operation. A wait condition represents a clock cycle in which the output data is invalid. When configured as output wait signal, ready wait is high impedance when chip enable is V or output enable is V. Ready-wait can be configured to activate on a wait cycle or one clock cycle earlier, and ready-wait polarity can be configured only when configured as a wait signal. IH Company IH Company
VDD supply voltage
V provides power to the internal core of the memory device and is the main power source for all operations (read, program, and erase). due diligence
VDDQ supply voltage
V provides power to the I/O pins and keeps all outputs powered independently of V. DDT Due Diligence
VPP Program Supply Voltage
V is the control input or power supply pin, selected by the voltage range applied to the pin. Polypropylene If V remains in the low voltage range (0V to V), V is considered a control input. In this case, voltages below V provide absolute protection for program or erase, while V in the range of V enables these functions. V is only sampled at the beginning of a program or erase - changes to its value after the operation has started will have no effect, and all program or erase operations will continue. Polypropylene DDT Polypropylene PPLK Company Polypropylene Page 1 Polypropylene If V is in the range of V, this signal acts as a power supply pin. In this case, V must be stable until the program/erase algorithm is complete. Polypropylene PPH Company Polypropylene
VSS ground
V ground is the reference for the core power supply and must be connected to system ground. SS
VSSQ grounded
V ground is the reference for the input/output circuits driven by V. V must be connected to V. SSQ DDT SSQ SS Note: Every device in the system should have VDD, VDDQ and VPP separated from 0.1µF ceramic capacitors close to the pins (high frequency, inherently low inductance capacitors should be as close to the package as possible). The track width of the PCB should be sufficient to carry the required VPP program and erase currents.
Field Programmable Gate Array Configuration Overview Platform Flash XL supports rich FPGA configuration features without the need for additional glue logic. The device transmits FPGA bitstreams at data rates of up to 800mb/s over a 16-bit data bus at power-up. The FPGA can also be configured from one of many design/modification bitstreams stored in the device. These revision bitstreams are accessed using the multi-boot addressing and fallback capabilities of the FPGA provided by the platform Flash XL in specific system configurations. For a detailed description of the FPGA configuration features and configuration process, see the appropriate FPGA Configuration User Guide.
At a high level, the general process for FPGA configuration of the platform Flash XL is as follows:
1. A system event (such as power-up) initiates the FPGA configuration process. While clearing the configuration memory, the FPGA drives its INIT_B pin low. Platform Flash XL pulls its ready-wait pin low during reset.
2. When ready, the FPGA and platform Flash XL release their respective INIT_B and ready_wait pins. The external resistor will synchronously initiate the FPGA configuration process from a low-to-high INIT_B-READY_ wait signal.
3. At the beginning of the configuration process, the FPGA samples its mode pins to determine its configuration mode. For master BPI up mode, the FPGA outputs an address read from flash. For Slave SelectMAP mode, the onboard resistor sets the initial flash read address.
4. The Platform Flash XL latches the initial address from the FPGA or on-board resistor settings into its internal address counter, and the Platform Flash XL outputs the first 16-bit word.
5. The bitstream is synchronously transferred from the platform Flash XL to the FPGA. On each successive FPGA CCLK cycle, the Platform Flash XL increments its internal address counter and outputs the next 16-bit word of the bitstream for use by the FPGA.
6. At the end of the configuration process, the FPGA starts to operate on the loaded bitstream and executes the driver high or releases it to high, indicating that the configuration process is complete.

notes:
1. The rate of 800mb/s is achieved using Virtex-5fpga and external 50mhz configuration clock source. Specific speed grades or system-level considerations for Virtex-6fpga can limit configuration performance to less than 800mb/s.
2. Bandwidth is based on an example Virtex-5fpga considering F and BitGen configuration rate = 31mhz (nominal frequency). McCorto
3. Bandwidth is based on an example Virtex-5fpga considering F and BitGen configuration rate=17mhz (nominal frequency), bpi_page_size=4 and bpi_1st_read_cycle=4. First word access time = 110 ns; page word access time = 25 ns. McCorto
4. See XAPP973 for indirect programming of BPI PROMs using Virtex-5 FPGAs.
Platform Flash XL can be configured with FPGA in Slave SelectMAP (X16) (recommended for maximum performance), Master SelectMAP (X16) or Master BPI UP (X16) configuration mode. See Table 4 for a summary of properties for different configuration modes and memories.
From SelectMAP Configuration Mode The Platform Flash XL achieves maximum configuration performance when the FPGA is in Slave SelectMAP configuration mode. In Slave SelectMAP mode, a stable external clock source can drive a synchronous bit stream from the device to the FPGA up to the maximum burst read frequency (t). See the SelectMAP Configuration Interface section in the respective FPGA for CLK Alternate Configuration Modes
Platform Flash XL is optimized for Slave SelectMAP configuration mode. Alternatively, the platform Flash XL can configure the FPGA via master select map or master BPI up mode, albeit with a compromise in configuration speed. For more information on Master SelectMAP mode or Master BPI Up mode, refer to the appropriate FPGA Configuration User Guide.
See UG438, Platform Flash XL Configuration and Storage Device User Guide for more information on using Platform Flash XL with FPGAs in Master Select Mapped or Master BPI Up mode.
Configure User Guide for details on Slave SelectMAP mode.
Note: FPGA fallback is disabled in Slave SelectMAP mode.
Programming Overview Platform Flash XL provides programming solutions to meet the requirements of each product stage. ISE software provides integrated programming support for FPGA design engineers in a prototyping environment. Third-party programming support is also available for manufacturing environment needs.
Shock programming solution for prototyping FPGA designs
Xilinx-ISE software provides complete support for in-system programming, enabling rapid development programs and test cycles for prototyping FPGA designs. The software can compile the FPGA design into a configuration bitstream and program the bitstream through the Xilinx JTAG cable into the platform Flash XL in the system.
The iMPACT software tool in the ISE software suite formats the FPGA user design bitstream into a flash image file and programs the device via a Xilinx JTAG cable connected to the FPGA's JTAG port. For the programming process, iMPACT software first downloads a pre-built bitstream containing an in-system programming engine into the FPGA. Then, the iMPACT software indirectly programs the bitstream designed by the FPGA user into the platform Flash XL through the in-system programming engine downloaded in the FPGA.
Note: In order to indirectly support iMPACT software in system programming, a specific set of connections needs to be established between the FPGA and the platform Flash XL. See UG438, Platform Flash XL
Configuration and storage device user guide, recommended connections. iMPACT only supports reading and writing main memory arrays. iMPACT does not support reading or writing special data registers such as electronic signature codes, protection registers or OTP registers.
Production Planning Solutions According to the requirements of the manufacturing environment, there are various solutions for the flash programming platform. Universal production programming platform provides programming support.

Integrated FPGA Design and In-System Programming Solutions for the Flash XL Platform Device programmers require array data in the form of data files in standard PROM format, such as MCS. Bitfiles are not a valid data input format for third-party device programmers. For instructions on preparing programming files, see . Platform Flash XL Configuration and Storage Device User Guide There are six standard bus operations for the bus operation control device: bus read, bus write, address latch, output disable, standby, and reset.
Bus Read Bus read operations are used to output memory arrays, electronic signatures, status registers, and general-purpose flash memory interfaces. In order to perform a read operation, both chip enable and output enable must be at V. The device should be enabled using the chip enable input. Data should be gated to the output using Output Enable. The data read depends on the command previously written to memory (see "Command Interface" on page 14). Illinois Bus Write A bus write operation writes a command to the memory or latch input data to be programmed. When chip enable and write enable start bus write operations at V, output enable starts at V. Commands, incoming data, and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. Addresses can be latched before write operations by toggling latch enable (when chip enable is V). The Illinois IH company Illinois system can also hold the latch enable signal at V, but the system must guarantee that the address lines are stable for at least T. Illinois Terminal Note: Typically, faults less than 5ns on-chip enable or write enable are ignored by memory and do not affect bus write operations.
Address Latch The address latch operation inputs a valid address. During address latch operation, both chip enable and latch enable must be at V. The address is latched on the rising edge of latch enable. Illinois Output Disabled When output enable is V, the output is held at high impedance.
Standby for spares disables most of the internal circuitry, greatly reducing current consumption. When the chip is enabled and reset to V, the memory is in a standby state. The power consumption is reduced to the standby level I, and the output is set to high impedance, independent of output enable or write enable. If the chip enable switches to V during a program or erase operation, the device enters standby mode when the program or erase operation is completed.

read array command
The Read Array command returns the address line to Read Array mode. A bus write cycle is required to issue a Read Array command. After a library is in read array mode, subsequent read operations output data from the memory array.
A read array command can be issued to any bank while programming or erasing in another bank. If a read array command is issued to the bank that is currently performing a program or erase operation, the bank will return to read array mode, but the program or erase operation will continue; however, until the program or erase operation is complete, the bank's data output will be cannot be guaranteed. The read modes of other banks are not affected.
Read Status Register Command The device contains a status register that is used to monitor program or erase operations.
The read status register command is used to read the contents of the status register of the address bank. A bus write cycle is required to issue a read status register command. After the bank is in read status register mode, subsequent read operations will output the contents of the status register.
Status register data is latched on chip enable or output enable. The chip enable or output enable must be toggled to update the status register data.
The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command only changes the read mode of the address bank. The read modes of other banks are not affected. Status registers can only be read using asynchronous read and single synchronous read operations.
A Read Array command is required to return the bank to Read Array mode.
Read Electronic Signature Command The Read Electronic Signature command is used to read manufacturer and device codes, lock status of address banks, protection registers, and configuration registers. A bus write cycle is required to issue a read electronic signature command. After a bank is in read e-signature mode, subsequent reads of the same bank will output the manufacturer code, device code, lock status of the addressed bank, protection registers, or configuration registers (see Table 10 on page 22).
The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during protection register program operations. Double operations between parameter groups and electronic signature locations are not allowed (see Table 17 on page 36 for details).
If a read electronic signature command is issued to the bank performing the program or erase operation, the bank enters read electronic signature mode. Subsequent bus read cycles output the electronic signature data, and the program/erase controller continues to program or erase in the background.
The Read Electronic Signature command only changes the read mode of the address bank. The read modes of other banks are not affected. Electronic signatures can only be read using asynchronous read and single synchronous read operations. A Read Array command is required to return the bank to Read Array mode.
Read CFI query command
The Read CFI Query command is used to read data from the Common Flash Interface (CFI). A bus write cycle is required to issue a Read CFI query command. After a bank is in Read CFI query mode, subsequent bus read operations of the same bank read from the common flash interface. The Read CFI Query command can be issued at any time, even during a program or erase operation.
If a Read CFI inquiry command is issued to the bank performing the program or erase operation, the bank will enter the Read CFI inquiry mode. Subsequent bus read cycles output the CFI data and the program/erase controller continues to program or erase in the background.
The Read CFI Query command only changes the read mode of the address bank. The read modes of other banks are not affected. CFI can only be read using asynchronous read and single synchronous read operations. A Read Array command is required to return the bank to Read Array mode. Double operations between parameter groups and CFI memory space are not allowed.
Clear Status Register Command The Clear Status Register command can be used to reset (set to '0') all error bits in the state (SR1, 3, 4 and 5)
register. A bus write cycle is required to issue a clear status register command. The Clear Status Register command does not affect the bank's read mode.
The error bit in the status register does not automatically return to '0' when a new command is issued. The error bit in the status register should be cleared before attempting a new program or erase command.
Block Erase Command The Block Erase command is used to erase blocks. It sets all bits in the selected block to "1". All previous data in the block will be lost.
If the block is protected, the erase operation is aborted, the data in the block is not changed, and the status register outputs an error.
It takes two bus write cycles to issue this command.
The first bus cycle sets the block erase command.
The second latches the block address and starts the program/erase controller.
If the second bus cycle is not a block erase confirmation code, then the Status Register bits SR4 and SR5 are set and the command is aborted.
After the command is issued, the bank enters read status register mode, and any read operation within the address bank outputs the contents of the status register. A Read Array command is required to return the bank to Read Array mode.
During a block erase operation, only the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and Program/Erase Suspend commands are accepted by the library containing the block to be erased; all other commands will be neglect.
If reset (RP) goes to V, the block erase operation is aborted. Since data integrity cannot be guaranteed when a block erase operation is aborted, the block must be erased again. Illinois Blank Check Order
The Blank Check command is used to check if the block has been completely erased. Only one block can be checked at a time. To use the blank check command, V must be equal to V. If V is not equal to V, the command will be ignored by the device and no error will be displayed in the status register. Polypropylene PPH Corp. Polypropylene PPH Corp. It takes two bus cycles to issue a blank check command:
The first bus cycle writes a blank check command (BCh) to any address in the block to be checked. The second bus cycle writes a blank check acknowledge command (CBh) to any address in the block to be checked and initiates a blank check operation.
If the second bus cycle is not a blank check confirmation, the status register bits SR4 and SR5 are set to "1" and the command is aborted.
After issuing the command, the address bank automatically enters the state registration mode, and further reads the state registration content in the bank.
The only operation allowed during the blank check is to read the status register. Double operations are not supported when doing a null check operation. When the device is in Program/Erase Suspend state, no suspend and blank check operations are allowed.
The SR7 status register bits indicate the status of an ongoing blank check operation:
SR7='0' means that the blank check operation is still in progress.
SR7='1' means the operation is complete.
The SR5 status register bit goes high (SR5='1'), indicating that the blank check operation failed.
At the end of the operation, the bank remains in read status register mode until another command is written to the command interface.
program command
The program command is used to program a single word into a memory array. If the block being programmed is protected, the program operation is aborted, the data in the block is not changed, and the status register outputs an error.
It takes two bus write cycle commands to issue a program.
The first bus cycle sets the program command. The second latches the address and data to be programmed and initiates the program/erase controller.
After programming begins, a read operation of the programmed bank outputs the contents of the status register.
During program operation, the library containing the programmed word only accepts Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and Program/Erase Suspend commands; all other commands are ignored. A Read Array command is required to return the bank to Read Array mode.
If reset (RP) goes to V, program operation is aborted. Since data integrity cannot be guaranteed when program operation is aborted, it must be reprogrammed. Illinois Buffer Program Order
The Buffer Program command uses the device's 32-word write buffer to speed up programming. Up to 32 words can be loaded into the write buffer. Compared with standard unbuffered program commands, buffered program commands greatly reduce system programming time.
There are four sequential steps required to issue a buffer program command:
1. The first bus write cycle sets the buffer program command. The setup code can be addressed anywhere in the target block.
After the first bus write cycle, a read operation outputs the contents of the status register. Status register bit SR7 should be read to check if the buffer is available (SR7=1). If the buffer is not available (SR7=0), the buffer program command must be reissued to update the status register contents.
2. The second bus write cycle sets the number of words to be programmed. The value n is written to the same block address, where n+1 is the number of words to program.
3. A total of n+1 bus write cycles are used to load the address and data of each word into the write buffer. The address must be in the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Best performance is obtained when the starting address corresponds to a 32-word boundary.
4. The last bus write cycle acknowledges the buffer program command and initiates program operation.
All addresses used in buffer program operations must be in the same block. An invalid address combination or failure to follow the correct sequence of bus write cycles will set an error in the status register and abort the operation without affecting the data in the memory array.
If the block being programmed is protected, an error is set in the status register and the operation is aborted without affecting the data in the memory array.
During buffer program operation, the programmed bank accepts only Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and Program/Erase Suspend commands; all other commands are ignored.
Buffer-Enhanced Factory Program Commands The Buffer-Enhanced Factory Program Commands were specially developed to accelerate programming in manufacturing environments where programming time is critical. This command is used to program one or more 32-word write buffers to the block. After the device enters the buffer-enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time.
If the block being programmed is protected, the program operation is aborted, the data in the block is not changed, and the status register outputs an error.
Using the Buffer Enhanced Factory Program command requires specific operating conditions:
V must be set to V. Polypropylene PPH Company
V must be within the operating range. Due diligence ambient temperature T must be 30°C ± 10°C. A target block must be unlocked.
The start address must be aligned with the start address on a 32-word buffer boundary. • The address must remain the starting address throughout the programming process.
Dual operations are not supported during buffer-enhanced factory program operations, and the command cannot be suspended.
Buffer-enhanced factory program commands consist of three phases: setup, program and verify, and exit.
installation phase
The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the command: The first bus write cycle sets the Buffer Enhanced Factory Program command.
A second bus write cycle acknowledges the command.
After issuing the confirm command, read the contents of the operation output status register.
Note that security cannot issue a read status register command as it is interpreted as data to be programmed.
Status Register Program/Erase Controller (P/EC). The SR7 bit should be read to check if the P/EC is ready to go to the next stage.
If an error is detected, SR4 will go high (set to '1') and the program and verify phases The program and verify phases take 32 cycles to program 32 words into the write buffer. Data is stored sequentially, starting at the first address of the write buffer until the write buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh.
The issuing and executing the program and verifying command phases require four sequential steps.
1. A bus write operation is used to lock the start address and the first word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check if the P/EC is ready to go to the next word.
2. Each subsequent word to be programmed is locked with a new bus write operation. When the P/EC increments the address location, the address must remain the starting address. If the given address is not in the same block as the start address, the program and verify phases terminate. Status register bit SR0 should be read between each bus write cycle to check if the P/EC is ready for the next word.
3. After the write buffer is full, the data is sequentially programmed into the memory array. After the program is run, the device automatically verifies the data and reprograms if necessary.
As long as the address remains in the same block, the program and verify phases can be repeated without re-issuing the command to program the location of the additional 32 words.
4. Finally, after programming all words or the entire block, a bus write must be written to any address other than the block containing the start address to terminate the program and verify phase.
Status register bit SR0 must be checked to determine if the program operation is complete. The status register can be checked for errors at any time, but must be checked after the entire block has been programmed.
Exit Phase Status Register P/EC bit SR7 is set to '1' when the device exits buffer enhanced factory program operation and returns to read status register mode. A full status register check should be done to ensure that the block was successfully programmed. See "Status Register" on page 23 for details.
For best performance, buffer-enhanced factory program commands should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded, the internal algorithm will continue to work properly, but performance may be degraded. See Table 21 on page 44 for typical program times.
See Figure 45 on page 79 for a suggested flowchart for using the Buffer Enhanced Factory program commands.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to suspend a program or block erase operation. This order can be sent to any bank.
A Program/Erase Resume command is required to restart a pending operation. A bus write cycle is required to issue a Program/Erase Suspend command. After the program/erase controller is suspended, bits SR7, SR6 and/or SR2 of the status register are set to "1".
The following commands are accepted during program/erase suspend:
Program/Erase Resume Read Array (Invalid data from Erase Suspend Block or Program Suspend Word)
Read Status Register Additionally, if the pending operation is a block erase, the following commands are also accepted:
Clear Status Register Procedure (except Erase Suspended Block)
Buffered routines (except erase pending blocks)
Block Unlock Setting Configuration Register Blocks to be erased can be protected by issuing a block lock or block lock command during erase suspend. The operation is complete when the program/erase resume command is issued.
Multiple pending operations can accumulate. For example, suspend an erase operation, start a program operation, suspend a program operation, and then read the array.
If a program command is issued during Block Erase Suspend, the erase operation cannot be resumed until the program operation is complete.
The Program/Erase Suspend command does not change the read mode of the rank. If the pending bank is in read status register, read electronic signature or read CFI inquiry mode, the bank will remain in that mode and output the corresponding data.
See "Dual Operation and Multi-Bank Architecture" on page 35 for details on allowing simultaneous operations during Program/Erase Suspend.
During program/erase suspend, the device can be put into standby mode by setting the chip enable to V. IH program/erase aborts if reset (RP) goes to V. Illinois Program/Erase Recovery Order
The Program/Erase Resume command is used to restart a program or erase operation that was suspended by the Program/Erase Suspend command. A bus write cycle is required to issue a command and can be sent to any address.
The Program/Erase Resume command does not change the read mode of the rank. If the pending bank is in read status register, read electronic signature or read CFI inquiry mode, the bank will remain in that mode and output the corresponding data.
If a program command is issued during Block Erase Suspend, the erase cannot be resumed until the program operation is complete.
Protection Register Program Commands The Protection Register Program Commands are used to program the protection registers and the user one-time programmable (OTP) section of the two protection register locks.
The device has 16 128-bit OTP segments and one 64-bit OTP segment. These snippets program one word at a time. When transmitting, all bits in the segment are set to '1'. The user can only program bits to '0'.
Two bus write cycles are required to issue a protection register program command:
The first bus cycle sets the protection register program command.
The second latches the address and data to be programmed into the protection registers and initiates the program/erase controller.
A read operation of the bank being programmed outputs the contents of the status register after the program operation begins. Attempting to program a previously protected protected register will result in a status register error.
Failed to suspend protection register program. Double operations between parameter groups and protection register memory spaces are not allowed.
set configuration register command
The Set Configuration Register command is used to write a new value to the configuration register. Two bus write cycles are required to issue the Set configuration register command:
The first loop setup sets the configuration register command and the address corresponding to the content of the configuration register. The second loop writes the configuration register data and acknowledges the command.
During a bus write cycle, the configuration register data must be written as an address, ie A0=CR0, A1=CR1,…,A15= CR15 . Addresses A16–A22 are ignored. The read operation outputs the contents of the array after issuing the Set Configuration Register command.
The read electronic signature command is used to read the updated content of the configuration register.
block lock command
The Block Lock command is used to lock blocks and prevent program or erase operations from changing the contents. All blocks are locked after power up or reset.
It takes two bus write cycles to issue a block lock command:
The first bus cycle sets the block lock command.
The second bus write cycle locks the block address and locks the block.
The lock status of each block can be monitored using the Read Electronic Signature command. Table 18 on page 38 shows the lock status after issuing the Block Lock command.
Once set, the block lock bit remains set even after a hardware reset or power down/power up. They are cleared by the block unlock command.
Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased.
It takes two bus write cycles to issue a block unlock command:
The first bus cycle sets the block unlock command.
The second bus write cycle locks the block address and unlocks the block.
The lock status of each block can be monitored using the Read Electronic Signature command. Table 18 on page 38 shows the protection status after a block unlock command is issued.
See "Block Lock" on page 37 for a detailed description, and Figure 43 on page 77 for a flowchart using the Block Unlock command.
Block Lock Command The block lock command is used to lock a locked or unlocked block.
Locked blocks cannot be programmed or erased. The lock state of a locked block cannot be changed in the following cases
WP is low (under V). When WP is high (V), the lock function is disabled and the locked blocks can be unlocked individually by the block unlock command. Two bus write cycles are required for the Illinois IH Corporation to issue a block lock command:
The first bus cycle sets the block lock command.
The second bus write cycle locks the block address and locks the block.
The lock status of each block can be monitored using the Read Electronic Signature command.
When the device is reset on power loss, the locking block will revert to the locked (not locked) state. Table 18 shows the lock status after the block lock command is issued.

notes:
one. iMPACT software does not support reading or writing protection register locks, OTP fields or unique device numbers.
Protection Registers Memory Mapped Status Registers Status Registers provide information on current or previous program or erase operations. Issue the Read Status Register command to read the contents of the Status Register, see "Read Status Register Command" on page 14 for details. To output the contents, the status register is latched and updated on the falling edge of the chip enable or output enable signal, and can be read until the chip enable or output enable returns to V. IH Corporation can only read the status register using a single asynchronous or synchronous read. A bus read operation from any address within the bank always reads the status register during the program, and if a read array command is not issued, an erase operation is performed.
Status Register Bits Various bits convey information about the status of the operation and any errors. Bits SR7, SR6, SR2 and SR0 provide information about the state of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give error information and are set by the device but must be reset by issuing a clear status register command or a hardware reset.
If the error bit is set to '1', the status register should be reset before issuing another command.

Program/Erase Controller Status Bit (SR7) Program/Erase Controller is active or inactive in any cylinder bank. When this bit is low (set to '0'), the Program/Erase Program/Erase Controller Status bit indicates that the bits in the Status Register are closed.
The controller is active; when the bit is high (set to '1'), the controller is inactive and the device is ready to process new commands.
Immediately after a program/erase suspend command is issued, the program/erase controller status bit goes low until the controller is suspended. After the program/erase controller is suspended, the bit is high.
Erase Suspend Status Bit (SR6)
The Erase Suspended Status bit indicates that the erase operation has been suspended. When this bit is high (set to '1'), a program/erase suspend command is issued and the memory is waiting for a program/erase resume command.
The Erase Pending Status bit should only be considered valid when the Program/Erase Controller Status bit is high (Program/Erase Controller is not active). SR6 sets the Erase Suspend Delay time for a Program/Erase Suspend command being issued; therefore, the memory can still complete operations instead of entering Suspend mode.
When a Program/Erase Resume command is issued, the Erase Suspend Status bit returns low.
Erase/Blank Check Status Bit (SR5)
The erase/blank check status bits are used to identify if an error has occurred during a block erase operation. When this bit is high (set to '1'), the program/erase controller applies the maximum number of pulses to the block, still failing to verify that it erased correctly.
The Erase/Blank Check Status bit should be read after the Program/Erase Controller Status bit is high (Program/Erase Controller is not active).
The Erase/Blank Check Status bit is also used to indicate if an error occurred during a blank check operation. SR5 is set to '1' if the data at one or more locations in the block where the blank check command was issued differs from FFFFh.
Once set high, the erase/blank check status bit must be set low by a clear status register command or a hardware reset before issuing a new erase command; otherwise, the new command will fail.
Program Status Bit (SR4)
Program status bits are used to identify errors during program operation. This bit should be read after the program/erase controller status bit is high (the program/erase controller is not active).
When the program status bit is high (set to '1'), the program/erase controller applies the maximum number of pulses to Word and still cannot verify that it is programmed correctly.
Attempting to program a "1" to the already programmed bit while V=V also sets the program status bit high. If V differs from V, SR4 is held low (set to '0') and no attempt is displayed. After polypropylene PPH is set high, the program status bit must be set low by a clear status register command or a hardware reset before issuing a new program command; otherwise, the new command will fail.
VPP Status Bit (SR3)
The V status bits are used to identify invalid voltages on the V pin during program and erase operations. The V pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if V becomes invalid during operation. Polypropylene Polypropylene Polypropylene The voltage on the V pin is sampled at the active voltage when the V status bit is low (set to '0'). Polypropylene When the V status bit is high (set to '1'), the voltage on the V pin is below the V lock voltage (V). Memory is protected from program and erase operations. Once set high, the V status bit must be set low by a clear status register command or a hardware reset before issuing a new program or erase command; otherwise, the new command will fail. PP Program Suspend Status Bit (SR2)
The Program Suspend Status bit indicates that program operation is suspended. This bit should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive).
When the program suspend status bit is high (set to '1'), a program/erase suspend command is issued and the memory is waiting for a program/erase resume command.
SR2 is set within the Program Suspend delay time when the Program/Erase Suspend command is issued; therefore, the memory can still complete the operation instead of entering Suspend mode.
When a program/erase resume command is issued, the program suspend status bit returns low.
Block Protection Status Bit (SR1)
The block protection status bits are used to identify whether a program or block erase operation is attempting to modify the contents of a locked or locked block. When this bit is high (set to '1'), an attempt is made to perform a program or erase operation on a locked or locked block.
When set high, the block protection status bit must be set low by a clear status register command or a hardware reset before issuing a new program or erase command; otherwise, the new command appears to fail.
Bank Write/Multiword Program Status Bit (SR0)
The Bank Write Status bit indicates whether the address bank is busy performing a write operation or is ready to accept a new write command (program or erase command). In buffer-enhanced factory program mode, the multiword program bit indicates whether the device is ready to accept new words to be programmed into the memory array.
The bank write status bit should be considered valid (set to '0') only when the program/erase controller status SR7 is low.
When both the program/erase controller status bit and the rank write status bit are low (set to '0'), the addressed rank is performing a program or erase operation. When the program/erase controller status bit is low (set to '0') and the rank write status bit is high (set to '1'), a program or erase operation is being performed on the addressed rank .
In buffer-enhanced factory program mode, if the multiword program status bit is low (set to '0'), the device is ready for the next word; if the multiword program status bit is high (set to '1'), then The device is not ready for the next word.
For more details on how to use the status register, see the flowchart and pseudocode provided in “Appendix C: Flowchart and Pseudocode” on page 71.
Configuration Registers The configuration registers are used to configure the type of bus access performed by the memory. For more information on read operations, see "Read Modes" on page 34.
Use the set Configuration Register command to set the configuration registers through the command interface. After reset or power-up, the device is configured to read synchronously (CR15=0). Configuration register bits specify the burst length, burst type, burst X delay, and selection of read operations.