feature

Charge-balanced ADC; 24-bit no missing code; 0.0015% nonlinearity; five-channel programmable gain front end; gain 1 to 128 ; configurable as three fully differential; inputs or five pseudo-differential inputs; three-wire serial interface; SPI 8482 ; , QSPI™, MICROWIRE™ and DSP compatible; 3V (AD7714-3) or 5 V (AD7714-5) operation; low noise (<150 nV rms); low current ( 350 9251 ; mA type) power down (5 mA type) ) AD7714Y grades:; +2.7 V to 3.3 V or +4.75 V to +5.25 V operation; 0.0010% linearity error; –40 8C to +1058C temperature range; Schmitt trigger on SCLK and DIN; low current ( 226 ␣ when powered down (4 mA); lower power consumption than standard AD7714; available in 24-lead TSSOP package; low-pass filter with programmable filter cutoff; ability to read/write calibration coefficients.

application

Portable Industrial Instruments; Portable Scales; Loop Powered System Pressure Sensors.

General Instructions

The AD7714 is a complete analog front end for low frequency measurement applications. The device receives a low level signal directly from the sensor and outputs a serial digital word. It uses sigma-delta conversion technology for up to 24 bits of missing code performance. The input signal is applied to a proprietary programmable gain front end based on an analog modulator. The modulator output is processed by an onchip digital filter. The first notch of this digital filter can be programmed via on-chip control registers, allowing adjustment of the filter cutoff and setup times.

This part features three differential analog inputs (which can also be configured as five pseudo-differential analog inputs) and a differential reference input. It operates from a power supply (+3␣V) or +5␣V). Therefore, the AD7714 performs all signal conditioning and conversion for systems consisting of up to five channels.

The AD7714 is ideal for use in microcontroller- or DSPBA-based intelligent systems. It has a configurable serial interface* protected by US Patent No. 5,134,401.

Three-wire operation. Gain settings, signal polarity and channel selection can be configured in software using the serial port. The AD7714 offers self-calibration, system calibration, and background calibration options, and also allows the user to read and write on-chip calibration registers.

The CMOS structure ensures very low power consumption, while the power-down mode reduces the standby power consumption to 15␣uW typ. The part is available in a 24-pin, 0.3-inch wide plastic dual in-line package (DIP); 24-lead Small Outline (SOIC), 28-lead Shrink Small Outline (SSOP), and 24-lead Thin Shrink Small Outline (TSSOP) .

Product Highlights

1. In addition to the standard AD7714, the AD7714Y has the following features: wider temperature range, Schmitt trigger on SCLK and DIN, operating voltage below 2.7V, lower power consumption, better linearity and 24 Leaded TSSOP package availability.

2. The total supply current consumption of AD7714 is less than 500 microamps (fCLK-IN=1␣MHz) or 1 mA (fCLK-IN=2.5␣MHz), so it is very suitable for use in loop power supply systems.

3. The programmable gain channel allows the AD7714 to directly accept input signals from strain gages or sensors, thereby eliminating extensive signal conditioning.

4. Ideal for microcontroller or DSP processor applications, the AD7714 has a three-wire serial interface that reduces the number of interconnects and reduces the number of optocouplers required in an isolated system. This section contains on-chip registers that allow control of filter cutoff, input gain, channel selection, signal polarity and calibration mode.

5. The part has excellent static performance specifications, 24 bits without missing codes, an accuracy of ±0.0015%, and low rms noise (140 nV). On-chip self-calibration eliminates the effects of endpoint errors and temperature drift, eliminating zero and full-scale errors.

the term*

Integral nonlinearity

This is the maximum deviation of any code from the straight line of the transfer function endpoints. The endpoint of the transfer function is zero scale (not to be confused with bipolar zero), 0.5lsb lower than the first code transition (000). . . 000 to 000. . . 001) and full scale, 0.5 LSB point above the last code transition (111). . . 110 to 111. . . 111 pages). Error is expressed as a percentage of full scale.

Positive full-scale error

Positive full-scale error is the deviation of the last code transition (111). . . 110 to 111. . . 111) from the ideal AIN(+) voltage (AIN(–) + VREF/Gain – 3/2 LSB). It is available for unipolar and bipolar analog input ranges.

Unipolar offset error

Unipolar offset error is the deviation of the first code transition from the ideal AIN+ voltage (AIN(–) + 0.5 LSB) when operating in unipolar mode.

Bipolar Zero Error

This is the bias of the mesoscale transformation (0111). . . 111 to 1000. . . 000) from the ideal AIN+ voltage (AIN(–)–0.5 LSB) when operating in bipolar mode.

gain error

This is a measure of ADC span error. It includes full-scale error, but not zero-scale error. For unipolar input ranges, it is defined as (full-scale error - unipolar offset error), and for bipolar input ranges, it is defined as (full-scale error - bipolar zero error).

*AIN (–) refers to the negative input of a differential input pair, or to AIN6 in a pseudo differential input configuration.

Bipolar negative full-scale error

This is the deviation of the first code transition from the ideal AIN+ voltage (AIN(–)–VREF/Gain+0.5␣LSB) when operating in bipolar mode.

Positive full-scale overrange

Positive full-scale overrange is an input voltage that can be used to handle input voltages on the AIN(+) input greater than AIN(–) + VREF/gain without introducing errors due to analog modulator overload or digital filter overflow amount of overhead (for example, noise spikes or overvoltages due to system gain errors in system calibration routines).

Negative full-scale overrange

This is the amount of overhead available to handle the voltage on AIN(+) below AIN(–) – VREF/Gain without overloading the analog modulator or overflowing the digital filter. Note that even in unipolar mode, the analog input will accept negative voltage spikes, provided that AIN+ is greater than AIN(–) and greater than AGND – 30␣mV.

Offset calibration range

In system calibration mode, the AD7714 calibrates its offset relative to the analog input. The offset calibration range specification defines the voltage range over which the AD7714 can accept and still accurately calibrate the offset.

Full-scale calibration range

This is the voltage range that the AD7714 can accept in system calibration mode and still correctly calibrate full scale.

input range

In the system calibration scheme, the analog input range is defined by two voltages sequentially applied to the AD7714 analog inputs. The input span specification defines the minimum to maximum input voltage, from zero to full scale, that the AD77 can accept and still accurately calibrate the gain.

AD7714-5 output noise

Table Ia shows the output rms noise and effective resolution for some typical notches and -3␣dB frequencies of the AD7714-5, where fCLK␣IN=2.4576␣MHz, and Table Ib gives fCLK IN=1␣MHz Information. The numbers given are for a bipolar input range where VREF is +2.5␣V and the buffer is 0. These numbers are typical and generated at an analog input voltage of 0␣V. The numbers in parentheses in each table are for the effective resolution of the part (rounded to the nearest 0.5␣LSB). The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale (ie, 2 × VREF/gain). It should be noted that it is not calculated using the peak-to-peak output noise number. The peak-to-peak noise number can be as high as 6.6 times the rms number, and the effective resolution number based on peak-to-peak noise can be 2.5 bits lower than the effective resolution based on rms noise quoted in the table.

The output noise of the part comes from two sources. The first is electrical noise (device noise) in semiconductor devices used for modulator implementation. Second, convert the analog input signal to the digital domain and add quantization noise. Equipment noise levels are low and largely independent of frequency. Quantization noise starts at a low level, but rises rapidly as the frequency increases, becoming the dominant noise source. Therefore, lower filter notch settings (around 100 Hz below FLCK=2.4576 MHz and below about 40 Hz for FLCK=1 MHz) tend to be dominated by device noise, while higher notch settings are primarily affected by Domination of quantization noise. As shown in Table 1, changing the filter notch and cutoff frequencies in the quantization noise control region results in a greater improvement in noise performance than changing the filter notch and cutoff frequencies in the device noise control region. Also, quantization noise is added after the PGA, so for higher filter notch frequencies, the effective resolution is largely independent of gain. At the same time, device noise is added to the PGA, so for lower notch frequencies, the effective resolution decreases at high gains. Also, in the device noise control region, the output noise (in μV) is largely independent of the reference voltage, while in the quantization noise control region, the noise is proportional to the reference value. The device can be post-filtered to increase the output data rate for a given -3␣dB frequency and further reduce output noise.

At lower filter notch settings (below 60␣Hz for fCLK IN=2.4576␣MHz; below 25␣Hz for fCLK IN=1␣MHz), the device's no-missing performance is at the 24-bit level . At higher settings, more code will be lost until the 1␣kHz notch setting of fCLK␣IN=2.4576␣MHz (400␣Hz at fCLK IN=1␣MHz) only guarantees 12-bit level No lost code performance.

AD7714-3 output noise

Table IIa shows some typical notches and output rms noise and effective resolution at -3␣dB frequency of AD7714-3, where fCLK␣IN=2.4576␣MHz, and Table IIb gives fCLK IN=1␣MHz Information. The numbers given are for a bipolar input range where VREF is +1.25␣V and the buffer is 0. These numbers are typical and generated at an analog input voltage of 0␣V. The numbers in parentheses in each table are for the effective resolution of the part (rounded to the nearest 0.5␣LSB). The effective resolution of the device is defined as the ratio of the output rms noise to the input full scale (ie, 2 × VREF/gain). It should be noted that it is not calculated using the peak-to-peak output noise number. The peak-to-peak noise number can be as high as 6.6 times the rms number, and the effective resolution number based on peak-to-peak noise can be 2.5 bits lower than the effective resolution based on rms noise quoted in the table.

The output noise of the part comes from two sources. The first is electrical noise (device noise) in semiconductor devices used for modulator implementation. Second, convert the analog input signal to the digital domain and add quantization noise. Equipment noise levels are low and largely independent of frequency. Quantization noise starts at a low level, but rises rapidly as the frequency increases, becoming the dominant noise source. Therefore, lower filter notch settings (around 100 Hz below FLCK=2.4576 MHz and below about 40 Hz for FLCK=1 MHz) tend to be dominated by device noise, while higher notch settings are primarily affected by Domination of quantization noise. As shown in Table 2, changing the filter notch and cutoff frequencies in the quantization noise control region results in a more significant improvement in noise performance than changing the filter notch and cutoff frequencies in the device noise control region. Furthermore, quantization noise is added after the PGA, so for higher filter notch frequencies, the effective resolution is largely independent of gain. At the same time, device noise is added to the PGA, so for lower notch frequencies, the effective resolution suffers somewhat at high gains. Also, in the device noise control region, the output noise (in μV) is largely independent of the reference voltage, while in the quantization noise control region, the noise is proportional to the reference value. The device can be post-filtered to increase the output data rate for a given -3␣dB frequency and further reduce output noise.

At lower filter notch settings (below 60␣Hz for fCLK IN=2.4576␣MHz; below 25␣Hz for fCLK IN=1␣MHz), the device's no-missing performance is at the 24-bit level . At higher settings, more code will be lost until the 1␣kHz notch setting of fCLK␣IN=2.4576␣MHz (400␣Hz at fCLK IN=1␣MHz) only guarantees 12-bit level No lost code performance.

buffer mode noise

Typical output rms noise and effective resolution -5 for some typical notches and -3␣dB frequencies of the AD7714, fCLK␣IN = 2.4576␣MHz, buffer = +5 V. Table IV again gives the information for the AD7714-3, fCLK IN = 2.4576 MHz, buffer = +5␣V. The numbers given are for bipolar input ranges and are generated with a differential analog input voltage of 0␣V. For the AD7714-5, the VREF voltage is +2.5␣V, while for the AD7714 the VREF voltage is +1.25␣V. The numbers in parentheses in each table are for the effective resolution of the part (rounded to the nearest 0.5 LSB). An effective solution device is defined as the ratio of the output rms noise to the input full scale (ie, 2 × VREF/gain). It should be noted that it is not calculated using the peak-to-peak output noise number. The peak-to-peak noise number can be as high as 6.6 times the rms number, and the effective resolution number based on peak-to-peak noise can be 2.5 bits lower than the effective resolution based on rms noise quoted in the table.

On-chip registers

The AD7714 contains eight on-chip registers that are accessible through the part's serial port. The first is the communication register, which controls the channel selection, decides whether the next operation is a read or write, and also decides which register the next read or write accesses. All communications with the part must begin with a write to the communications register. After power-up or reset, the device expects a write to its communication register. The data written to this register determines whether the next operation of the part is a read or write operation, and also determines which register the read or write operation occurs in. Therefore, a write access to any other register on the part starts with a write to the communications register, followed by a write to the selected register and a read from any other register on the part (including the output data register) from the communications register starts with a write operation of the selected register, followed by a read operation with the selected register. The communication register also controls the channel selection, and the DRDY status can also be obtained by reading from the communication register. The second register is the mode register that determines the calibration mode and gain settings. The third register is labeled Filter High register, this determines the word length, bipolar/unipolar operation, and contains the upper 4 bits of the Filter selection word. The fourth register is labeled the Filter Low register and contains the lower 8 bits of the Filter select word. The fifth register is the test register that is accessed when testing the device. The sixth register is the data register for accessing the output data of the part. The final register allows access to the part's calibration registers. The zero-scale calibration registers allow access to the zero-scale calibration coefficients for the selected input channel, while the full-scale calibration registers allow access to the full-scale calibration coefficients for the selected input channel. The following sections discuss these registers in more detail.

Communication register (RS2-RS0=0, 0, 0)

The communication register is an 8-bit register from which data can be read or written. All communications with the part must begin with a write to the communications register. The data written to the communication register determines whether the next operation is a read or write operation, and on which register the operation occurs. Once a subsequent read or write to the selected register is complete, the interface returns to where it expected a write to the communications register. This is the default state of the interface, and after power-up or reset, the AD7714 is in this default state, waiting for a write to the communication register. In the event of a loss of interface sequence, the AD7714 will return to this default state if a write operation of a sufficiently long duration (comprising at least 32 serial clock cycles) occurs with DIN high. Table 5 summarizes the bit names of the communication registers.

Test register (RS2–RS0=1, 0, 0)

This section contains test registers for testing equipment. The user is advised not to change the state of any bit in this register from the default (power on or reset) state of all 0s to 0 as the part will be put into one of its test modes and will not function properly. If the part enters one of its test modes, performing a reset will exit the part of that mode. Another way to get the part out of its test mode is to reset the interface by writing 32 consecutive 1s to the part and then all 0s to the test register.

Data register (RS2–RS0=1, 0, 1)

The data register on the part is a read-only register that contains the most recent conversion result from the AD7714. The registers can be programmed to be 16-bit or 24-bit wide, depending on the state of the WL bit in the mode register. If the communications register data sets the part for a write to that register, the write must actually be performed in order to return the part to where it expected a write to the communications register (the default state of the interface). However, 16 or 24 bits of data written to the part will be ignored by the AD7714.

Zero-scale calibration register (RS2–RS0=1, 1, 0); power-on/reset state: 1F4000␣hex

The AD7714 contains three zero-scale calibration registers, labeled Zero-Scale Calibration Register 0 through Zero-Scale Calibration Register ␣ 2. These three registers are completely independent of each other, so in fully differential mode, each input channel has a zero-scale register. Each of these registers is a 24-bit read/write register, and when writing to a register, 24 bits must be written; otherwise, no data is transferred to the register. The registers are used with the associated full-scale calibration register to form a register pair. These register pairs are associated with input channel pairs.

When the part is set up to allow access to these registers via the digital interface, the part itself no longer has access to the register coefficients to properly scale the output data. Therefore, after accessing the calibration register (read or write operation), the first output data read from the part may contain incorrect data. Also, while calibrating, no attempt should be made to read or write the calibration registers. These possibilities can be avoided by setting the SYNC input low or FSYNC bits of the mode register high before the calibration register operation and setting them high or low respectively after the operation is complete.

Full-scale calibration register (RS2–RS0=1, 1, 1); power-on/reset state: 5761AB␣hex

The AD7714 contains three full-scale calibration registers, labeled Full-Scale Calibration Register 0 to Full-Scale Calibration Register 2. These three registers are completely independent of each other, so in fully differential mode, each input channel has a full-scale register. Each of these registers is a 24-bit read/write register, when writing to a register, 24 bits must be written, otherwise no data will be transferred to the register. This register is used with the associated zero-scale calibration register to form a register pair. As shown in Table 7, these register pairs are associated with pairs of input channels.

When a part is set up to allow access to these registers via the digital interface, the part itself no longer has access to the coefficients to properly scale the output data. Therefore, after accessing the calibration register (read or write operation), the first output data read from the part may contain incorrect data. Also, while calibrating, no attempt should be made to read or write the calibration registers. These possibilities can be avoided by setting the SYNC input low or FSYNC bits of the mode register high before the calibration register operation and setting them high or low respectively after the operation is complete.

Calibration operation

The AD7714 includes a number of calibration options, as previously described. Table XI summarizes the calibration types, operations involved, and duration of operations. There are two ways to determine the end of calibration. The first is to monitor when DRDY returns low at the end of the sequence. DRDY not only indicates when the sequence is complete, but also indicates that there is a valid new sample in the part's data register. This valid new sample is the result of a normal transformation in the calibration sequence. The second way to determine when calibration is complete is to monitor the MD2, MD1, and MD0 bits of the Mode Register. When these bits return to 0, 0, 0 after the calibration command, the calibration sequence is complete. This method does not indicate whether a valid new result exists in the data register. However, it gives an indication that the calibration was done earlier than DRDY. The time for the mode bits (MD2, MD1, and MD0) to return to 0, 0, 0 indicates the duration of the calibration. The sequence when DRDY goes low also includes normal conversion and pipeline delay tP (2000 × tCLK IN) to properly scale the result of the first conversion. The times for both methods are given in the table.

Circuit Description

The AD7714 is a sigma-delta A/D converter with on-chip digital filtering for measuring low frequency signals with a wide dynamic range, such as those in weighing scales, pressure sensors, industrial control, or process control applications. It contains a sigma-delta (or charge balance) ADC, a calibrated microcontroller with on-chip static RAM, a clock oscillator, digital filters, and a bidirectional serial communication port. The part consumes only 500µA of supply current and features a standby mode that requires only 10µA, making it ideal for battery-powered or loop-powered instruments. There are two versions of this part, the AD7714-5, which is specified for operation from a nominal +5␣V analog supply (AVDD), and the AD7714-3, which is specified for operation from a nominal +3.3␣V analog supply. Both versions can operate from a digital power (DVD) voltage of +3.3␣V or +5␣V. The AD7714Y-grade parts are rated for AVDD of 3 V or 5 V, and can operate from digital supply voltages of 3 V or 5 V.

This section contains three programmable gain fully differential analog input channels that can be reconfigured to five pseudo-differential inputs. The gain range on all channels is 1 to 128, allowing the part to accept unipolar signals between 0 mV to +20 mV and 0 V to +2.5 mV. In bipolar mode, the part processes true bipolar signals of ±20 mV, and quasi-bipolar signals of ±2.5 V when the reference input voltage is equal to +2.5␣V. In unipolar mode, the input range is 0 mV to +10 mV to 0 V to +1.25␣V with a reference voltage of +1.25␣V, while in bipolar mode the part handles true bipolar of ±10 mV signals and quasi-bipolar signals up to ±1.25 V.

This part uses sigma-delta conversion technology to achieve up to 24 bits of missing code performance. A sigma-delta modulator converts a sampled input signal into a digital pulse train whose duty cycle contains digital information. A programmable gain function on the analog input is also included in this sigma-delta modulator, the input sampling frequency of the modulator is modified to provide higher gain. The sinc3 digital low-pass filter processes the output of the sigma-delta modulator and updates the output register at a rate determined by the filter's first notch frequency. Output data can be read randomly or periodically from the serial port at any rate up to the output register update rate. The first notch of this digital filter, its -3␣dB frequency and its output rate are programmable through the filter high and filter low registers. With a master clock frequency of 2.4576MHz, this first notch frequency and output rate are programmable from 4.8␣Hz to 1.01 kHz, giving a programmable range of -3␣dB frequencies from 1.26 Hz to 265␣Hz.

The basic connection diagram of the parts is shown in Figure 2. It is shown that both the AVDD and DVD pins of the AD7714 are driven by an analog +3␣V or +5␣V supply. Some applications will have AVDD and DVDD drivers from different supplies. In the connection diagram shown, the analog inputs of the AD7714 are configured as three fully differential inputs. This section is set up for unbuffered mode on these analog inputs. The AD780 precision +2.5V reference voltage provides the reference source for the part. On the digital side, the part is configured for three-wire operation, with CS tied to DGND. A quartz crystal or ceramic resonator provides the main clock source for the part. Capacitors may need to be attached to the crystal or resonator to ensure it does not oscillate at overtones of its fundamental operating frequency. The value of the capacitor will vary according to the manufacturer's specifications.

analog input

Analog input range

The AD7714 contains six analog input pins (labeled AIN1 to AIN6) that can be configured as three fully differential input channels or five pseudo-differential input channels. Bits CH0, CH1, and CH2 of the communication register configure the analog input configuration, and the channel selection is as described in Table VII above. Input pairs (differential or pseudo-differential) provide programmable gain, and the input channels can handle unipolar or bipolar input signals. It should be noted that bipolar input signals are referenced to the corresponding AIN(–) inputs of the input pair.

In unbuffered mode, the common-mode range of these inputs is from AGND to AVDD, provided that the absolute value of the analog input voltage is between AGND␣–␣30␣mV and AVDD+30␣mV. This means that in unbuffered mode, the part can handle unipolar and bipolar input ranges for all gains. In buffered mode, the analog input can handle a larger source impedance, but the absolute input voltage range is limited to AGND␣+50␣mV to AVDD–1.5␣V, which also limits the common-mode range. This means that in buffered mode there is some limit to the allowable gain of the bipolar input range. Care must be taken when setting the common-mode voltage and input voltage range so as not to exceed the above limits, which will result in degraded linearity performance.

In unbuffered mode, the analog input directly observes the 7␣pF input sampling capacitor CSAMP. The DC input leakage current in this unbuffered mode is 1 nA maximum. As a result, the analog input sees a dynamic load that switches at the input sample rate (see Figure 3). This sample rate depends on the master clock frequency and the selected gain. CSAMP charges to AIN+ and discharges to AIN (–) every input sampling cycle.

The effective on-resistance RSW of the switch is usually 7␣kΩ.

CSAMP must be charged during each input sampling period through RSW and any external source impedance. Therefore, in unbuffered mode, the source impedance means that the CSAMP takes longer to charge, which can cause some gain errors. Table XII shows the allowable external resistor/capacitor values in unbuffered mode, so this section does not introduce gain errors at the 16-bit level. Table 13 again shows the allowable external resistor/capacitor values for unbuffered mode so that 20-bit gain errors are not introduced.

In buffered mode, the analog input looks at the high impedance input stage of the on-chip buffer amplifier. The CSAMP is charged through this buffer amplifier so that the source impedance does not affect the charging of the CSAMP. The bias leakage current of this buffer amplifier is 1␣nA. In this buffered mode, a larger source impedance results in a DC offset voltage from the source impedance, but no gain error.

input sample rate

The modulator sampling frequency of the AD7714 remains at fCLK␣IN/128 (19.2␣kHz@fCLKIN=2.4576␣MHz), regardless of the selected gain. However, gains greater than 1 are achieved by combining multiple input samples per modulator cycle and scaling the ratio of reference capacitance to input capacitance. As a result of multiple sampling, the input sampling rate of the device varies with the selected gain (see Table XIV). In buffered mode, the input is buffered before the input sampling capacitor. In unbuffered mode, the analog input directly observes the sampling capacitor, and the effective input impedance is 1/CSAMP × fS, where CSAMP is the input sampling capacitor and fS is the input sampling rate.

burnout current

The AD7714 contains two 1µA currents, one sourced from AVDD to AIN+ and one sink from AIN(–) to AGND. The current depends on whether the BO bit of the mode register is on or off. These currents can be used to check if the sensor is burned out or open circuited before attempting to measure that channel. If the current is turned on, the sensor allows flow, and the input voltage is measured at the analog input. The measured voltage is full scale, which means the sensor is open; if the measured voltage is zero, the sensor is shorted. For normal operation, these burn-out currents are turned off by writing a 0 to the BO bit. For the source current to work properly, the applied voltage on AIN+ should not be within 500␣mV of AVDD. For the receiver current to work properly, the voltage applied on the AIN(–) input should not be within 500␣mV of AGND.

Bipolar/Unipolar Input

The analog inputs on the AD7714 can accept unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can handle negative voltages on its analog inputs, as negative voltages on the analog inputs cannot exceed -30␣mV to ensure proper operation of the part. Input channels can be either fully differential or pseudo differential (all other channels reference AIN6). In both cases, the input channels are paired with AIN(+) and AIN(–). Therefore, the voltage referenced by the unipolar and bipolar signals on the AIN+ input is the voltage on the corresponding AIN(–) input. For example, if AIN(–) is +2.5␣V and the AD7714 is configured for unipolar operation with a gain of 2 and VREF is +2.5␣V, the input voltage range on the AIN(–) input is +2.5 V to +3.75 ␣ V. If AIN(–) is +2.5␣V and the AD7714 is configured in bipolar mode with a gain of 2 and VREF is +2.5␣V, the analog input range on the AIN+ input is +1.25␣V to +3.75 V (that is, 2.5␣V ±1.25␣V). If AIN (–) is at AGND, the part cannot be configured for a bipolar range exceeding ±30␣mV.

The bipolar or unipolar option is selected by programming the B/U bits of the filter high register. This will program the selected channel for unipolar or bipolar operation. Programming a channel for unipolar or bipolar operation does not change any input signal conditioning; it just changes the data output encoding and the point on the transfer function where calibration occurs.

reference input

The reference inputs of the AD7714 (REF␣IN(+) and REF␣IN(–)) provide differential reference input capability. The common-mode range of these differential inputs is from AGND to AVDD. The nominal reference voltage VREF of the AD7714-3 (REF␣IN(+␣–REF␣IN(–)). This part operates with VREF down to 1V, but due to output noise (in terms of LSB size) will becomes larger, so the performance is degraded. REF␣IN(+) must always be greater than REF␣IN(-) for the AD7714 to work properly.

The two reference inputs provide a high impedance, dynamic load similar to the analog input in unbuffered mode. The maximum DC input leakage current is ±1 nA over temperature, and the supply resistance can cause gain errors in the device. In this case, the sampling switch resistance is of the 5␣kΩ type, and the reference capacitor (CREF) varies with gain. The sampling rate on the reference input is fCLK IN/64 and does not vary with gain. For gains of 1 to 8, CREF is 8 pF; for gain of 16, CREF is 5.5 pF; for gain of 32, CREF is 4.25 pF; for gain of 64, CREF is 3.625 pF; for gain of 128, CREF is 3.3125 pF.

The output noise performance listed in Tables 1 through 4 applies to an analog input of 0 V and is not affected by noise on the reference. To obtain the same noise performance as shown in the noise table over the entire input range, the AD7714 requires a low noise reference source. Excessive reference noise in the bandwidth of interest can degrade the performance of the AD7714. In applications where the excitation voltage of the bridge sensor on the analog input is also derived from the reference voltage of the component, the effect of noise in the excitation voltage will be eliminated since the application is a ratiometric measurement. The recommended reference voltage sources for AD7714-5 and AD7714Y grades with AVDD=5V include AD780, REF43 and REF192, while the recommended reference voltage sources for AD7714-3 and AD7714Y with AVDD=3V include AD589 and AD1580. Decoupling the output of these reference signals is generally recommended to further reduce noise levels.

digital filtering

The AD7714 contains an on-chip low-pass digital filter to process the output of the part's sigma-delta modulator. Therefore, this section provides not only the analog-to-digital conversion function, but also some degree of filtering. There are a number of system differences that users should be aware of when providing filtering in the digital rather than the analog domain.

First, since digital filtering occurs after the AD conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, digital filters are easier to program than analog filters. Depending on the design of the digital filter, this gives the user the ability to program the cutoff frequency and output update rate.

Analog filtering, on the other hand, removes noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this, even if the average value of the signal is within limits, noise peaks multiplying on a signal close to full scale can potentially saturate the analog modulator and digital filter. To alleviate this problem, the AD7714 has overrange margin built into the sigma-delta modulator and digital filter, allowing an overrange offset of 5% beyond the analog input range. If the noise signal is larger than this value, then consider analog input filtering, or reduce the input channel voltage so that its full scale is half the full scale of the analog input channel. This will provide greater than 100% overrange capability at the cost of reducing the dynamic range by 1 bit (50%).

Furthermore, digital filters do not provide any suppression at integer multiples of the digital filter sampling frequency. However, the input samples for this portion provide attenuation at multiples of the digital filter sampling frequency, so that unattenuated frequency bands actually occur around multiples of the input sampling frequency fS (as defined in Table XIV). Therefore, the unattenuated band appears at n × fS (where n = 1, 2, 3). . .). At these frequencies, there is a ±f3 dB wide band (f3db is the cutoff frequency of the digital filter) on either side of the noise passing unattenuated to the output.

Filter characteristics

The digital filter of the AD7714 is a low-pass filter with a (sinx/x)3 response (also called sinc3). The transfer function of this filter is described in the z-domain by:

In the frequency domain:

Figure 4 shows the filter frequency response with a cutoff frequency of 2.62␣Hz, corresponding to the first filter notch frequency of 10␣Hz. Shown is DC to 65␣Hz. The response repeats on either side of the input sampling frequency and multiples of the input sampling frequency.

The filter's response is similar to the averaging filter, but with sharper attenuation. The output rate of the digital filter corresponds to the location of the first notch of the filter's frequency response. Therefore, for the graph in Figure 4 with an output rate of 10␣Hz, the first notch of the filter is at 10␣Hz. The notch of this (sinx/x)3 filter is repeated in multiples of the first notch. The filter provides greater than 100dB of attenuation at these notches. For the given example, if the first notch is at 10␣Hz, there will be notches at both 50␣Hz and 60␣Hz (so greater than 100␣Hz) dB suppression).

The cutoff frequency of the digital filter is determined by the value of bits FS0 through FS11 loaded into the Filter High and Filter Low registers. Programming different cutoff frequencies via FS0–FS11 does not change the profile of the filter response; it changes the notch frequencies outlined in the Filter Registers section. The output update corresponds to the first notch and is determined by the following relationship:

Output rate = fCLK IN/(N.128) where N is the decimal equivalent of the word loaded into the FS0 to FS11 bits of the filter register, and the -3␣dB frequency is determined by the relationship: –3␣dB frequency = 0.262 ×Filter first notch frequency

The filter provides a linear phase response with a group delay determined by:

Group delay = –3π, where N is the decimal equivalent of the word loaded into bits FS0 to FS11 of the filter register, fMOD = fCLK IN/128 (Nf/fMOD).

Because the AD7714 includes this on-chip low-pass filtering, there is a settling time associated with the step function input, and after a step change, the data on the output will be invalid until the settling time has elapsed. The fixed time depends on the output rate selected for the filter. The settling time of the filter to a full-scale step input can be four times the period of the output data. For synchronous step inputs (using the SYNC or FSYNC function), the adjustment time is three times the period of the output data. When changing part of the channel, the change from one channel to the other is synchronized, so the output settling time is also three times the output data period. Therefore, in switching between channels, the output data register is not updated until the settling time of the filter has elapsed.

post filter

The on-chip modulator provides samples at an output rate of 19.2␣kHz, and fCLK-IN is 2.4576␣MHz. An on-chip digital filter decimates these samples, providing data at an output rate that corresponds to the filter's programmed output rate. Since the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth will satisfy most application needs. However, there may be some applications that require higher data rates for a given bandwidth and noise performance. Applications requiring higher data rates will require some post-filtering after the part's digital filter.

For example, if the desired bandwidth is 7.86␣Hz, but the desired update rate is 100␣Hz, data can be acquired from the AD7714 at 100␣Hz, giving a -3 dB bandwidth of 26.2␣Hz. Post-filtering can be applied to reduce the bandwidth and output noise to the 7.86␣Hz bandwidth level, while maintaining the 100␣Hz output rate.

Post-filtering can also be used to reduce output noise from devices with bandwidths below 1.26␣Hz. When the gain is 128 and the bandwidth is 1.26␣Hz, the output rms noise is 140␣nV. This is essentially device noise or white noise, which has a substantially flat frequency response due to the truncated input. By reducing the bandwidth below 1.26␣Hz, the noise in the resulting passband can be reduced. A 2x reduction in bandwidth results in a reduction in output RMS noise of about 1.25. This additional filtration will result in longer settling times.

Analog filtering

As mentioned earlier, digital filters do not provide any rejection at integer multiples of the input sampling frequency. However, due to the high oversampling rate of the AD7714, these bands occupy only a small portion of the spectrum, and most of the broadband noise is filtered out. This means that the analog filtering requirements in front of the AD7714 are greatly reduced compared to traditional converters without on-chip filtering. Furthermore, since the common-mode rejection of this part extends 100␣dB to several kHz, the common-mode noise in this frequency range will be greatly reduced.

However, depending on the application, it may be necessary to provide attenuation before the AD7714 in order to remove unwanted frequencies from these bands that the digital filter will pass. In some applications, it may also be necessary to provide analog filtering in front of the AD7714 to ensure that differential noise signals outside the frequency band of interest do not saturate the analog modulator.

If passive components are placed in front of the AD7714 in unbuffered mode, care must be taken to ensure that the source impedance is low enough to not introduce gain errors into the system. This significantly limits the amount of passive antialiasing filtering that can be provided in front of the AD7714 when using it in unbuffered mode. However, when the part is used in buffered mode, the larger source impedance results in only a small DC offset error (a 10␣kΩ source resistance will result in an offset error of less than 10␣μV). Therefore, if the system requires any significant source impedance to provide passive analog filtering in front of the AD7714, it is recommended to operate the part in buffered mode.

calibration

The AD7714 offers a number of calibration options, programmable through the MD2, MD1, and MD0 bits of the mode register. The different calibration options are outlined in the Mode Register and Calibration Sequence section. A calibration cycle can be initiated at any time by writing to these bits of the mode register. Calibration on the AD7714 removes the offset and gain errors of the device. A calibration procedure should be initiated on the device when the ambient operating temperature or supply voltage changes. It should also activate if the selected gain, filter notch, or bipolar/unipolar input range is changed.

The AD7714 allows the user to access on-chip calibration registers, allowing the microprocessor to read the device's calibration coefficients, or to write its own calibration coefficients to the part from pre-stored values in E2PROM. This gives the microprocessor greater control over the calibration process of the AD7714. This also means that the user can verify that the device has performed the calibration correctly by comparing the calibrated coefficients with pre-stored values in the E2PROM. The values in these calibration registers are 24 bits wide. In addition, the user can adjust the span and offset of the part.

The values of these coefficients vary significantly at different output update rates, gains, and unipolar/bipolar operation. Inside the AD7714, these coefficients are normalized before being used to scale the words output from the digital filter. The offset calibration register contains a value that is subtracted from all conversion results when normalizing. The full-scale calibration register contains a value that, when normalized, is multiplied by all conversion results. The offset calibration factor is subtracted from the result before multiplying by the full-scale factor. This means that the full scale factor is actually the span or gain factor.

The AD7714 provides self-calibration, system calibration, and background calibration equipment. For full calibration on the selected channel, the on-chip microcontroller must record the modulator output for two different input conditions. These are the "zero scale" and "full scale" points. These points are obtained by converting the different input voltages supplied to the modulator input during calibration. Therefore, the accuracy of the calibration can only be as good as the noise level provided by the part in normal mode. The result of the "zero-scale" calibration conversion is stored in the zero-scale calibration register for the appropriate channel. The result of the "full-scale" calibration conversion is stored in the corresponding channel's full-scale calibration register. Using these readings, the microcontroller can calculate the offset and gain slope of the converter's input-output transfer function. Internally, the section uses 33-bit resolution to determine its 16-bit or 24-bit conversion result.

self-calibration

Self-calibration is initiated on the AD7714 by writing the appropriate values (0, 0, 1) to the MD2, MD1, and MD0 bits of the mode register. In self-calibration mode with a unipolar input range, the zero used to determine the calibration factor is internally shorted to the input of the differential pair on the part (ie, AIN+=AIN(–)=internal bias voltage). Sets the PGA for the selected gain (according to the G2, G1, G0 bits in the mode register) for this zero-scale calibration conversion. A full-scale calibration conversion is performed on the internally generated voltage VREF/selected gain at the selected gain.

The calibration duration is 6×1/output rate. This consists of 3×1/output rate (for zero-scale calibration) and 3×1/output rate (for full-scale calibration). At this time, the MD2, MD1 and MD0 bits in the mode register return to 0, 0, 0. This provides the earliest indication that the calibration sequence has been completed. The DRDY line goes high when calibration begins and does not return low until there is a valid new word in the data register. The duration from when the calibration command is issued to when DRDY goes low is 9×1/output rate. This consists of 3×1/output rate (for zero-scale calibration), 3×1/output rate (for full-scale calibration), and 3×1/output rate (for analog input conversion). If DRDY is low before (or during) a calibration command is written to the mode register, one modulator cycle (MCLK␣IN/128) may be required before DRDY is high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register.

For bipolar input ranges in self-calibration mode, the sequence is very similar to the sequence just outlined. In this case, the two points are exactly the same as above, but since the part is configured for bipolar operation, the output code for a zero differential input is 800000 Hex in 24-bit mode.

This section also provides ZS self-calibration and FS self-calibration options. In these cases, the part only performs a zero-scale or full-scale calibration, respectively, rather than a full calibration of the part. Full-scale calibration should not be performed unless the part contains a valid zero-scale factor. These calibrations are initiated on the AD7714 by writing the appropriate values (1, 1, 0 for ZS self-calibration, 1, 1 for FS self-calibration) into the MD2, MD1 and MD0 bits of the mode register. Zero-scale or full-scale calibration is exactly as described for full self-calibration. In these cases, the calibration duration is 3×1/output rate. At this time, the MD2, MD1 and MD0 bits in the mode register return to 0, 0, 0. This provides the earliest indication that the calibration sequence has been completed. The DRDY line goes high when calibration begins and does not return low until there is a valid new word in the data register. The time from when the calibration command is issued to when DRDY goes low is 6×1/output rate. This consists of 3×1/output rate (for zero-scale or full-scale calibration) and 3×1/output rate (for analog input conversion). If DRDY is low before (or during) a calibration command is written to the mode register, one modulator cycle (MCLK␣IN/128) may be required before DRDY is high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register.

The fact that self-calibration can be performed as a two-step calibration provides another feature. After the full self-calibration sequence is complete, additional offset or gain calibrations can be performed on their own to adjust the zero or gain of the part. Calibrating one of the parameters (offset or gain) does not affect the other.

System calibration

System calibration allows the AD7714 to compensate for system gain and offset errors as well as its own internal errors. System calibration performs the same slope factor calculations as self-calibration, but uses the system-supplied voltage values as the AIN input for the zero and full-scale points. Full system calibration requires a two-step process, one is ZS system calibration, followed by FS system calibration.

For a full system calibration, the zero point must first be shown to the converter. It must be applied to the converter before starting the calibration step and stabilized until the step is complete. Once the system zero scale has been set on the analog input, the ZS system calibration is initiated by writing the appropriate values (0, 1, 0) to the MD2, MD1 and MD0 bits of the mode register. Perform zero-scale system calibration at the selected gain. The calibration time is 3×1/output rate. At this point, the MD2, MD1, and MD0 bits in the mode register return to 0, 0, 0. This provides the earliest indication that the calibration sequence has been completed. The DRDY line goes high when calibration begins and does not return low until there is a valid new word in the data register.

The time from when the calibration command is issued to when DRDY goes low is 4×1/output rate. This consists of 3 x 1/output rate (for zero-scale system calibration) and 1/output rate (for analog input conversion). This conversion on the analog input is the same as the zero-scale system calibration voltage, so the word in the data register resulting from this conversion should be a zero-scale reading. If DRDY is low before (or during) a calibration command is written to the mode register, one modulator cycle (MCLK␣IN/128) may be required before DRDY is high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register.

After calibrating the zero point, apply the full-scale point to AIN and start the second step of the calibration process by writing the appropriate values (0, 1, 1) to MD2, MD1, and MD0 again. Again, the full-scale voltage must be set before starting the calibration and must remain stable throughout the calibration steps. Performs a full-scale system calibration at the selected gain. The calibration time is 3×1/output rate. At this point, the MD2, MD1, and MD0 bits in the mode register return to 0, 0, 0. This provides the earliest indication that the calibration sequence has been completed. The DRDY line goes high when calibration begins and does not return low until there is a valid new word in the data register.

The time from when the calibration command is issued to when DRDY goes low is 4×1/output rate. This is composed of 3 × 1/output rate (for full-scale system calibration) and 1/output rate (for analog input conversion). This conversion on the analog input is the same as the full-scale system calibration voltage, so the word in the data register resulting from this conversion should be a full-scale reading. If DRDY is low before (or during) a calibration command is written to the mode register, one modulator cycle (MCLK␣IN/128) may be required before DRDY is high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register.

In unipolar mode, a system calibration is performed between the two endpoints of the transfer function; in bipolar mode, a system calibration is performed between midscale (zero differential voltage) and positive full scale.

The fact that the system calibration is a two-step calibration provides another feature. After the full system calibration sequence is complete, additional offset or gain calibrations can be performed on their own to adjust the system zero reference point or system gain. Calibrating one of the parameters (system offset or system gain) does not affect the other. Full-scale calibration should not be performed unless the part contains a valid zero-scale factor.

System calibration can also be used to remove any errors in the analog input source impedance when using the part in unbuffered mode. A simple R,C antialiasing filter on the front end may introduce gain error on the analog input voltage, but system calibration can be used to remove this error.

System offset calibration

System offset calibration is a variation of system calibration and self-calibration. In this case, the zero point is determined in exactly the same way as the ZS system calibration. The system zero-scale point is displayed at the input of the drive. It must be applied to the converter before starting the calibration step and stabilized until the step is complete. Once the system zero scale is set, system offset calibration is then initiated by writing the appropriate values (1, 0, 0) to the MD2, MD1 and MD0 bits of the mode register. Perform zero-scale system calibration at the selected gain.

The full-scale calibration is performed in exactly the same way as the FS self-calibration. A full-scale calibration conversion is performed on the internally generated voltage VREF/selected gain at the selected gain. This is a one-step calibration procedure with a calibration time of 6×1/output rate. At this point, the MD2, MD1, and MD0 bits in the mode register return to 0, 0, 0. This provides the earliest indication that the calibration sequence has been completed. The DRDY line goes high when calibration begins and does not return low until there is a valid new word in the data register. The duration from when the calibration command is issued to when DRDY goes low is 9×1/output rate. This consists of 3×1/output rate (for zero-scale system calibration), 3×1/output rate (for full-scale self-calibration), and 3×1/output rate (for analog input conversion). This conversion on the analog input is the same as the zero-scale system calibration voltage, so the word in the data register resulting from this conversion should be a zero-scale reading. If DRDY is low before (or during) a calibration command is written to the mode register, one modulator cycle (MCLK␣IN/128) may be required before DRDY is high to indicate that calibration is in progress. Therefore, DRDY should be ignored for up to one modulator cycle after the last bit of the calibration command is written to the mode register.

In unipolar mode, the system offset calibration is performed between the two endpoints of the transfer function; in bipolar mode, the system offset calibration is performed between midscale and positive full scale.

background calibration

The AD7714 also offers a background calibration mode in which the part interleaves its calibration process with the normal conversion sequence. In background calibration mode, the part provides continuous zero-scale self-calibration; it does not provide any full-scale calibration. In this mode, the zero point used to determine the calibration coefficients is exactly the same as the zero point used for ZS self-calibration. Background calibration mode is invoked by writing 1, 0, 1 to the MD2, MD1, MD0 bits of the mode register. When invoked, the background calibration mode performs a zero-scale self-calibration after each output update, which reduces the output data rate of the AD7714 by a factor of 6. The advantage is that the part is continuously offset calibrated and automatically updates its zero-scale calibration coefficients. The results automatically eliminate the effects of temperature drift, power supply sensitivity, and time drift on zero-scale error. When background calibration mode is on, the part will remain in this mode until bits MD2, MD1 and MD0 of the mode register are changed.

Since background calibration does not perform a full-scale calibration, a self-calibration should be performed before placing the part in background calibration mode. In this mode, eliminating offset drift makes gain drift the only source of error not eliminated from the part. The typical gain drift of the AD7714 over temperature is 0.2␣ppm/°C. Sync input or FSYNC bit-ground calibration mode should not be used when the part is in the back.

Span and Offset Limits

Whenever the system calibration mode is used, there are limits to the offset and span that can be accommodated. The most important requirement when determining the amount of offset and gain a part can accommodate is a positive full-scale calibration limit of ≤ 1.05 × VREF/gain. This allows the input range to be 5% higher than the nominal range. The built-in headroom of the AD7714 analog modulator ensures that the part will function properly when the positive full-scale voltage exceeds 5% of the nominal value.

The input span range in unipolar and bipolar modes is 0.8×VREF/gain minimum and 2.1×VREF/gain maximum. However, the range (that is, the difference between the bottom of the AD7714's input range and the top of the input range) must account for the limitation of positive full-scale voltage. The amount of offset that can be accommodated depends on whether unipolar or bipolar mode is used. Again, the offset must account for the limit of positive full-scale voltage. In unipolar mode, there is considerable flexibility in dealing with negative (relative to AIN(-)) offsets. In both unipolar and bipolar modes, the range of positive offsets that the part can handle depends on the range selected. Therefore, when determining the limits of the system's zero-scale and full-scale calibration, the user must ensure that the offset range plus the span range does not exceed 1.05 × VREF/gain. This is well illustrated by looking at a few examples.

If the part is used in unipolar mode and the desired range is 0.8×VREF/gain, the offset range that can be handled by the system calibration is -1.05×VREF/gain to +0.25×VREF/gain. If the part is used in unipolar mode and the desired range is VREF/gain, the offset range that can be handled by the system calibration is -1.05×VREF/gain to +0.05×VREF/gain. Likewise, if the part is used in unipolar mode and the offset of 0.2×VREF/gain needs to be canceled, the range that can be handled by the system calibration is 0.85×VREF/gain.

If the part is used in bipolar mode and the desired range is ±0.4×VREF/gain, the offset range that can be handled by the system calibration is -0.65×VREF/gain to +0.65×VREF/gain. If the part is used in bipolar mode and the desired range is ±VREF/gain, the offset range that can be handled by the system calibration is -0.05×VREF/gain to +0.05×VREF/gain. Likewise, if the part is used in bipolar mode and the offset of ±0.2×VREF/gain needs to be canceled, the range that can be handled by the system calibration is ±0.85×VREF/gain.

Power up and calibrate

On power-up, the AD7714 performs an internal reset, setting the contents of the internal registers to a known state. After power-up or reset, all registers are loaded with default values. The default value contains the nominal calibration coefficients for the calibration registers. However, to ensure proper calibration of the device, the calibration procedure should be performed after power up.

The AD7714 has low power dissipation and temperature drift, and requires no warm-up time before performing an initial calibration. However, if an external reference is used, it must be stable before calibration can begin. Similarly, if the part's clock source is generated by a crystal or resonator across the MCLK pin, the start-up time of the oscillator circuit should elapse before the part begins calibration (see below).

Using AD7714

Clock and Oscillator Circuits

The AD7714 requires a master clock input, which can be an external CMOS compatible clock signal applied to the MCLK␣ input pin, leaving the MCLK␣ output pin unconnected. Alternatively, in this case, a crystal or ceramic resonator of the correct frequency can be connected between MCLK␣IN and MCLK␣OUT. The clock circuit will act as an oscillator, providing the clock source for the part. Input sampling frequency, modulator sampling frequency, -3␣dB frequency, output update rate and calibration time are all directly related to the master clock frequency fCLK␣IN Reducing the master clock frequency by a factor of 2 will halve the above frequency and update rate, and the calibration time double. The current drawn from the DVDD power supply is also directly related to fCLK␣IN. Decreasing fCLK␣IN by a factor of 2 will halve the DVDD current, but will not affect the AVDD supply current.

Using a part with a crystal or ceramic resonator between the MCLK input and MCLK output pins often results in more current being drawn from the DVD than when the part is clocked from the drive clock signal at the MCLK input pin . This is because the on-chip oscillator circuit is active in the case of a crystal or ceramic resonator. Therefore, the lowest possible current on the AD7714 is at the MCLK IN pin, with MCLK OUT unconnected and unloaded.

The amount of additional current drawn by the oscillator depends on many factors, first, the larger the value of capacitors placed on the MCLK␣ input and MCLK␣ output pins, and then the greater the DVDD current consumption on the AD7714. Care should be taken not to exceed the capacitance values recommended by the crystal and ceramic resonator manufacturers to avoid drawing unnecessary DVDD current. Typical values recommended by crystal or ceramic resonator manufacturers are in the range of 30␣pF to 50␣pF, and if the MCLK input and MCLK output capacitance values are kept within this range, it will not cause any excessive DVD D current. Another factor that affects DVDD current is the effective series resistance (ESR) of the crystal that appears between the MCLK input and MCLK output pins of the AD7714. In general, the lower the ESR value, the less current the oscillator circuit will draw.

When operating with a clock frequency of 2.4576␣MHz, when operating with a DVD D of +3␣V, there is no noticeable difference in DVD D current between the externally applied clock and the crystal resonator. When DVD D=+5␣V and fCLK in=2.4576␣MHz, for the clock provided by the crystal/resonator, the typical DVDD current increases by 50μA compared to the clock of the external application. Crystals and resonators tend to have low ESR values at this frequency, so there is little difference between different crystal and resonator types.

When operating at a clock frequency of 1␣MHz, the ESR values of different crystal types vary widely. As a result, the current leakage of DVDDs varies across different crystal types. When using a crystal with an ESR of 700Ω or using a ceramic resonator, the typical DVDD current increase on the external clock is 50Ωa when DVDD=+3ΩV, and 175Ωa when DVDD=+5ΩV. When using a crystal with an ESR of 3ΩkΩ, the typical DVDD current increase is again 50␣A when DVDD=+3␣V compared to the external application clock, and 300␣A when DVDD=+5␣V .

The on-chip oscillator circuit also has a start-up time associated with it before it oscillates at the correct frequency and voltage level. The typical startup time of this circuit is 10␣ms, +5␣V for DVDD, 15␣ms, and +3␣V for DVDD. With a 3␣V supply, depending on the load capacitance on the MCLK pin, a 1␣MΩ feedback resistor on the crystal or resonator may be required to keep the startup time around 15␣ms.

The master clock of the AD7714 appears on the MCLK OUT pin of the device. The maximum recommended load on this pin is a CMOS load. When a crystal or ceramic resonator is used to generate the clock to the AD7714, it may be necessary to use this clock as the clock source for the system. In this case, it is recommended to buffer the MCLK OUT signal with a CMOS buffer before applying it to the rest of the circuit.

System synchronization

The sync input (or FSYNC bit) allows the user to reset the modulator and digital filter without affecting any set conditions on the part. This allows the user to start sampling the analog input from a known point in time (i.e. a synchronous rising edge) or when a 1 is written to FSYNC.

A sync input can also be used to allow the other two functions. If multiple AD7714s are operating from a common master clock, they can be synchronized to update their output registers simultaneously. A falling edge on the sync input (or writing a 1 to the FSYNC bit of the mode register) resets the digital filter and analog modulator and places the AD7714 in a consistent known state. The AD7714 will remain in this state when the sync input is low (or FSYNC is high). On the rising edge of sync (or when a 0 is written to the FSYNC bit), the modulator and filter are taken out of this reset state, and on the next clock edge, the part starts collecting input samples again. In systems using multiple AD7714s, a common signal on the sync input will synchronize their operation. This is usually done after each AD7714 has performed its own calibration or loaded the calibration coefficients. The maximum possible difference between the output update and the output update of a single AD714S is then synchronized to one MCLK cycle.

The sync input can also be used as a start conversion command, allowing the AD7714 to be operated in a conventional converter fashion. In this mode, the rising edge of SYNC starts the conversion and the falling edge of DRDY indicates when the conversion is complete. The disadvantage of this scheme is that the settling time of the filter is considered every time the data register is updated. This means that the data registers are updated three times as fast in this mode.

Since the sync input (or the FSYNC bit) resets the digital filter, the full settling time of 3×1/output rate must elapse before the new word is loaded into the part's output register. When SYNC returns high (or FSYNC), if the DRDY signal is low and goes to 0), the DRDY signal will not be reset to high by the SYNC (or FSYNC) command. This is because the AD7714 recognizes that there is a word in the data register that has not been read. The DRDY line will remain low until the data register is updated, at which point it will go high at 500 × tCLK IN and then return low again. A read from the data register resets the DRDY signal high and does not return low until the filter's setup time (via a SYNC or FSYNC command) has elapsed and there is a valid new word in the data register. If the DRDY line is high when a SYNC (or FSYNC) command is issued, the DRDY line will not return low until the filter's setup time has elapsed.

reset input

The reset input on the AD7714 resets all logic, digital filters, and analog modulators, while all on-chip registers are reset to their default states. DRDY is driven high, and when the reset input is low, the AD7714 ignores all communications with any register. When the reset input returns high, the AD7714 begins processing data, and DRDY will return low at a rate of 3 × 1/output, indicating a valid new word in the data register. However, the AD7714 operates with its default settings after reset, and it is often necessary to set all registers and perform calibration after a reset command.

The on-chip oscillator circuit of the AD7714 continues to operate even when the reset input is low. The master clock signal continues to be available on the MCLK OUT pin. Therefore, in applications where the system clock is provided by the AD7714's clock, the AD7714 generates an uninterrupted master clock during reset commands.

Standby mode

A standby input on the AD7714 allows the user to place the part in power-down mode when conversion results are not required. The AD7714 retains the contents of all its on-chip registers, including the data registers, in standby mode. In standby mode, the digital interface is reset and DRDY is reset to logic 1. Data cannot be accessed from the component in standby. When released from standby mode, the part starts processing data, and when the standby input goes high, a new word is available in the data register at a rate of 3×1/output.

Placing the part in standby mode reduces the total current to 5␣μA when the part is operating from an external master clock, provided that master clock is stopped. If the external clock continues to run in standby mode, the standby current increases to 150␣µA (typically 150␣µA for a 5V supply) and 75µA for a 3.3V supply. If a crystal or ceramic resonator is used as the clock source, the total current in standby mode is 400␣μa, typically a 5 V supply, and 90μa a 3.3 V supply. This is because the on-chip oscillator circuit continues to run while the part is in standby mode. This is important in applications where the system clock is provided by the AD7714 clock so that the AD7714 can generate an uninterrupted master clock even in standby mode.

Accuracy 2

Like VFCs and other integrated ADCs, Sigma-Delta ADCs do not contain any sources of non-monotonicity and inherently do not provide the missing code performance. The AD7714 achieves excellent linearity through the use of high-quality on-chip capacitors, which have a very low capacitance/voltage coefficient. The device also achieves low input drift through the use of chopper stabilization techniques in the input stage. To ensure excellent performance over time and temperature, the AD7714 uses digital calibration techniques to minimize offset and gain errors.

Drift factor

The AD7714 uses a chopper stabilization technique to minimize input offset drift. Charge injection in the analog switch and DC leakage current at the sampling node are the main sources of offset voltage drift in the converter. The DC input leakage current is inherently independent of the selected gain. Gain drift within the converter is primarily dependent on the temperature tracking of the internal capacitors. It is not affected by leakage current.

Measurement errors caused by offset drift or gain drift can be eliminated at any time by recalibrating the converter or operating the part in background calibration mode. Using the system calibration mode also minimizes offset and gain errors in the signal conditioning circuit. Integral and differential linearity errors are not significantly affected by temperature changes.

power supply

The AD7714 does not require a specific power supply sequence; the AVDD or DVD power supply can start first. Although the latching performance of the AD7714 is good, it is important to power up the AD7714 before a signal at the REF␣IN, AIN, or logic input pins to avoid latching. If this is not possible then the current flowing in these pins should be limited. If separate power supplies are used for the AD7714 and the system digital circuits, the AD7714 should be powered up first. If this cannot be guaranteed then a current limiting resistor should be placed in series with the logic input to limit the current again.

Supply current

The current consumption on the AD7714 is specified for supplies in the range of +3␣V to +3.6␣V and +4.75␣V to +5.25␣V. The part operates over a +2.85␣V to +5.25␣V supply range, and the IDD of the part varies as the supply voltage changes over this range. Figure 5 shows typical IDD versus VDD voltage for a 1 MHz external clock and a 2.4576 MHz external clock at +25°C. The AD7714 operates in unbuffered mode with the internal boost bit on the part turned off. This relationship shows that IDD can be minimized by operating parts with a lower VDD voltage. IDD on the AD7714 is also minimized by using an external master clock or by optimizing external components when using the on-chip oscillator circuit. Y-class parts are specified for 2.7 V to 3.3 V and 4.75 V to 5.25 V.

Grounding and Arrangement

Since the analog input and reference input are differential, most voltages in the analog modulator are common-mode voltages. Excellent common mode rejection section will eliminate common mode noise on these inputs. The analog and digital power supplies for the AD7714 are independent and fixed separately to minimize coupling between the analog and digital parts of the device. The digital filter will reject broadband noise on the power supply, except for integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs, provided these noise sources do not saturate the analog modulator. Therefore, the AD7714 is more susceptible to noise interference than conventional high-resolution converters. However, due to the high resolution of the AD7714 and the low noise level of the AD7714, care must be taken with respect to grounding and layout.

The design of the printed circuit board housing the AD7714 should keep the analog and digital sections separate and confined to certain areas of the board. This facilitates the use of easily separated ground planes. The minimum etch technique is usually best for the ground plane because it provides the best shielding. Digital and analog ground can only be connected in one place. If the AD7714 is the only device that requires an AGND to DGND connection, the ground plane should be connected at the AGND and DGND pins of the AD7714. If the AD7714 is in a system where multiple devices require an AGND to DGND connection, it should still only be connected at one point, as close to the AD7714 as possible to establish a star ground point.

Avoid running digital lines under the device as this will couple noise onto the die. The analog ground plane should allow operation under the AD7714 to avoid noise coupling. The power lines to the AD7714 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to the rest of the board, and clock signals must not run near the analog inputs. Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This will reduce feedthrough effects through the board. Microstrip technology is by far the best, but not always possible on double-sided panels. In this technique, the component side of the board is dedicated to the ground plane, while the signals are placed on the solder side.

Good decoupling is very important when using high resolution ADCs. All analog supplies should be separated from 10µF tantalum and in parallel with 0.1µF capacitors to AGND. To get the best results from these decoupling components, they must be placed as close to the device as possible, ideally facing the device. All logic chips should be decoupled to DGND with 0.1␣uF disc ceramic capacitors. In systems that use a common supply voltage to drive the AD7714's AVDD and DVD, it is recommended to use the system's AVDD supply. This supply should have the recommended analog supply decoupling capacitor between the AVDD pin of the AD7714 and AGND and the recommended digital supply

DVDD pin and DGND of the AD7714.

Evaluating AD7714 Performance

The recommended layout for the AD7714 is outlined in the evaluation board for the AD7714. The evaluation board package includes a fully assembled and tested evaluation board, documentation, software for controlling the board's printer port on the PC, and software for analyzing the performance of the AD7714 on the PC. For the AD7714-5, the evaluation board order number is EVAL-AD7714-5EB, and for the AD7714-3, the order number is EVAL-AD7714-3EB.

The noise level in the signal applied to the AD7714 can also affect the performance of the part. The AD7714 allows the true performance of the part to be evaluated using two techniques that are independent of the analog input signal. These schemes should be used after the part has been calibrated.

The first step is to select the AIN6/AIN6 input channel arrangement. In this case, the differential inputs of the AD7714 are internally shorted together, providing zero differential voltage to the analog modulator. External to the device, the AIN6 input should be connected to a voltage within the allowable common-mode range of the part.

The second option is to evaluate the part near the input full-scale voltage with a gain of 1. To do this, the reference voltage of the part should be applied to the analog input. This will give a fixed full-scale reading of the device. If the zero-scale calibration factor is now read from the device, a number equivalent to about 200 decimal is added, and the value is reloaded into the zero-scale calibration register, the input range will be shifted such that a voltage equal to the reference voltage no longer corresponds to full scale reading. This allows the user to evaluate the noise performance of the part at voltages close to full scale.

digital interface

As mentioned earlier, the programmable functions of the AD7714 are controlled by a set of on-chip registers. Data is written to these registers through the part's serial interface, which also provides read access to on-chip registers. All communications with the part must begin with a write to the communications register. After power-up or reset, the device expects a write to its communication register. The data written to this register determines whether the next operation of the part is a read or write operation, and also determines which register the read or write operation occurs in. Therefore, a write access to any other register on the part begins with a write to the communications register, followed by a write to the selected register. A read from any register on the part, including the output data register, is a write to the communications register A write operation followed by a read operation from the selected register.

The serial interface of the AD7714 consists of five signals: CS, SCLK, DIN, DOUT, and DRDY. The DIN line is used to transfer data to the on-chip registers, while the DOUT line is used to access data from the on-chip registers. SCLK is the serial clock input to this device, and all data transfers (via DIN or DOUT) are relative to this SCLK signal. The DRDY line is used as a status signal to indicate when data can be read from the AD7714's data register. DRDY will go low when a new data word is available in the output register. It is reset high when the read operation of the data register is complete. It also goes high before updating the output register to indicate when not to read from the device, to ensure that no attempt is made to read data while the register is being updated. CS is used to select a device. It can be used to decode the AD7714 in systems where multiple components are connected to a serial bus.

The AD7714 serial interface can operate in three-wire mode by connecting the CS input low. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the AD7714, and the status of DRDY can be obtained by interrogating the MSB of the communication register.

Figure 6 and Figure 7 show the timing diagrams for interfacing with the CS for the decoding part to the AD7714. Figure 6 shows a read operation of the AD7714 output shift register, while Figure 7 shows a write operation to the input shift register. Both figures are for the POL input at logic high; for POL input operation at logic low, simply invert the SCLK waveform shown in the figures. Even though the DRDY line returns high after the first read operation, the same data can be read from the output register twice. However, care must be taken to ensure that the read operation is complete before the next output update is about to occur.

The serial interface can be reset by applying a reset input to the part. It can also be reset by writing a series of 1s to the DIN input. The serial interface is reset if a logic 1 is written to the AD7714 data line for at least 32 serial clock cycles. This ensures that in a three-wire system, if an interface is lost, either due to a software bug or some failure in the system, it can be reset to a known state. This status returns the interface where the AD7714 expects a write to the communication register. This operation itself does not reset the contents of any registers, but since the interface is lost, the information written to any registers is unknown, and it is recommended to reset all registers.

Configuring the AD7714

The AD7714 contains eight on-chip registers accessible through the serial interface. Communication with any of these registers is first initiated by writing to the communication register. Figure 8 outlines a flowchart of a sequence used to configure all registers after power-up or reset. The flow chart also shows two different read options, the first option polls the DRDY pin to determine when an update of the data register has occurred, and the second option queries the DRDY bit of the communication register to see if an update of the data register has occurred . The flow chart also includes a series of words that should be written to registers to meet specific operating conditions. These conditions are test channel (4000), gain of 1, burnout current, no filter sync, bipolar mode, 24-bit word length, boost and maximum filtered word (10 decimal places).

Microcomputer/Microprocessor Interface

The flexible serial interface of the AD714 allows simple interfacing with most microcomputers and microprocessors. The flowchart in Figure 8 outlines the sequence to be followed when connecting a microcontroller or microprocessor to the AD7714. Figures 9, 10 and 11 show some typical interface circuits.

The serial interface on the AD7714 operates from only three wires and is compatible with the SPI interface protocol. Three-wire operation makes this part ideal for isolation systems where the number of interface wires is minimized and the number of opto-isolators required is minimized. The rise and fall times of the digital inputs of the AD7714 (especially the SCLK input) should not exceed 1␣us.

Most of the registers on the AD7714 are 8-bit registers to facilitate interfacing with the microcontroller's 8-bit serial port. Some registers are up to 24 bits, but data transfers to these 24-bit registers can consist of a full 24-bit transfer or three 8-bit transfers to the microcontroller's serial port. DSP processors and microprocessors typically transfer 16-bit data in serial data operations. Some of these processors, such as the ADSP-2105, have the ability to program the number of serial transfer cycles. This allows the user to customize the number of bits in any transfer to match the register length of the desired register in the AD7714.

Although some of the registers on the AD7714 are only 8 bits in length, communication with two of these registers in consecutive write operations can be handled as a single 16-bit data transfer if desired. For example, if the mode register is to be updated, the processor must first write to the communication register (i.e. the next operation is to write to the mode register) and then write 8 bits to the mode register. This can all be done in one 16-bit transfer if desired, since this part is immediately set up for the mode register write operation as soon as the 8 serial clocks of the communication register write operation are complete.

AD7714 to 68HC11 interface

Figure 9 shows the AD7714 and 68HC11 microcontrollers. The figure shows the minimum (three-wire) interface to CS on the AD7714 hardwired low. In this scheme, the DRDY bit of the communication register is monitored to determine when to update the data register. Another option is to monitor the DRDY output line from the AD7714, which increases the number of interface lines to four. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the 68HC11's port bits (eg PC0), which is configured as an input. This port bit is then polled to determine the status of DRDY. The second option is to use an interrupt-driven system, in which case the DRDY output is connected to the IRQ input of the 68HC11. For interfaces that need to control the CS input on the AD7714, a port bit of the 68HC11 (eg PC1) (configured as an output) can be used to drive the CS input.

The 68HC11 is configured in master mode with its CPOL bit set to logic zero and its CPHA bit set to logic one. When the 68HC11 is configured this way, its SCLK line idles low between data transfers. Therefore, the POL input of the AD7714 should be hardwired low. For systems where SCLK idle high is preferable, the CPOL bit of the 68HC11 should be set to logic 1 and the POL input of the AD7714 should be hardwired to logic high.

The AD7714 is not capable of full duplex operation. If the AD7714 is configured for a write operation, no data will appear on the data output lines even if the SCLK input is active. Similarly, if the AD7714 is configured for a read operation, the data presented to the part on the data line will be ignored even when SCLK is active.

The coding of the interface between the 68HC11 and the AD7714 is shown in Table XV. In this example, the DRDY output line of the AD7714 is connected to the PC0 port bit of the 68HC11 and polled to determine its status.

AD7714 to 8051 interface

The interface circuit between the AD7714 and the 8XC51 microcontroller is shown in Figure 10. This figure shows the minimum number of interface connections to CS on the AD7714 hardwired low. For the 8XC51 interface, the minimum number of interconnects is only two. In this scheme, the DRDY bit of the communication register is monitored to determine when to update the data register. Another option is to monitor the DRDY output line from the AD7714, which increases the number of interface lines to three. The monitoring of the DRDY line can be done in two ways. First, DRDY can be connected to one of the port bits of the 8XC51 configured as an input (eg P1.0). This port bit is then polled to determine the status of DRDY. The second option is to use an interrupt-driven system, in which case the DRDY output is connected to the INT1 input of the 8XC51. For interfaces that need to control the CS input on the AD7714, the 8XC51 (eg P1.1) configured as an output can be used. A port bit to drive the CS input.

The 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a data line. Therefore the data output and data input pins of the AD7714 should be connected together. The serial clock on the 8XC51 idles high between data transfers, so the POL input of the AD7714 should be hardwired to logic high. In a write operation, the 8XC51 outputs the LSB first, while the AD7714 expects the MSB to be output first, so the data to be transmitted must be rearranged before being written to the output serial register. Similarly, during a read operation, the AD7714 outputs the MSB first, while the 8XC51 requires the LSB. Therefore, the data read into the serial buffer needs to be rearranged before the correct data word from the AD7714 is available in the accumulator.

AD7714 to ADSP-2103/ADSP-2105 Interface

Figure 11 shows the interface between the AD7714 and the ADSP-2103/ADSP-2105 DSP processors. In the interface shown, the DRDY bit of the communication register is again monitored to determine when to update the data register. Another option is to use an interrupt-driven system, in which case the DRDY output is connected to the IRQ2 input of the ADSP-2103/ADSP-2105 The RFS and TFS pins of the ADSP-2103/ADSP-2105 are configured as active low Output, the ADSP-2103/ADSP-2105 serial clock line SCLK is also configured as an output. The POL pin of the AD7714 is hardwired low. Since the SCLK from the ADSP-2103/ADSP-2105 is a continuous clock, once the transfer is complete, the CS of the AD7714 must be used to shut down the clock. The CS of the AD7714 is activated when the RFS or TFS outputs of the ADSP-2103/ADSP-2105 are activated. The serial clock rate on the ADSP-2103/ADSP-2105 should be limited to 3␣MHz to ensure proper operation of the AD7714.

Code to set up the AD7714

Table XV presents a set of C code read and write routines for interfacing the 68HC11 microcontroller to the AD7714. The sample program sets various registers on the AD7714 and reads 1000 samples from the part to the 68HC11. The setup conditions on the part are exactly the same as shown in the flowchart of Figure 8. In the example code given here, the DRDY output is polled to determine if a new valid word is available in the output register.

The sequence of events in this program is as follows:

1. Write the communication register to set the channel.

2. Write the filter high register, set the 4 MSBs of the filter word, and set this part to 24-bit read, bipolar mode, boost off.

3. Write the filter low register to set the 8 LSBs of the filter word.

4. Write to the mode register, set the section to gain 1, deplete current shutdown, no filter synchronization, and start self-calibration.

5. Poll the DRDY output.

6. Read data from the data register.

7. Repeat steps 5 and 6 until the specified number of samples are completed.

application

The on-chip PGA allows the AD7714 to handle an analog input voltage range down to 10 mV full-scale, with VREF=+1.25␣V. The differential inputs of the part allow this analog input range to have an absolute value anywhere between AGNC and AVDD when the part is operating in unbuffered mode. It allows the user to connect sensors directly to the inputs of the AD7714. The programmable gain front end on the AD7714 allows the part to handle unipolar analog input ranges from 0 mV to +20 mV to 0 V to +2.5 mV and bipolar input ranges from ±20 mV to ±2.5 V. Because the part operates from a single supply, these bipolar ranges are relative to the biased upper differential input.

pressure measurement

A typical application for the AD7714 is pressure measurement. Figure 12 shows the AD7714 used with a pressure sensor (BP01 from Sensym). The pressure sensors are arranged in a bridge network and provide a differential output voltage between their output (+) and output (-) terminals. At rated full-scale pressure (300 mmHg in this case) on the sensor, the differential output voltage is 3 mV/V of the input voltage (that is, the difference between its in(+) and in(–) terminals Voltage). Assuming an excitation voltage of 5 V, the full-scale output range of the sensor is 15 mV. The excitation voltage of the bridge is also used to generate the reference voltage for the AD7714. Therefore, changes in the excitation voltage do not introduce errors into the system. Choose the resistor values 24␣kΩ and 15kΩ according to the chart, when the excitation voltage is 5V, the reference voltage of AD7714 is 1.92V. Using the part with a programmed gain of 128, the AD7714 has a full-scale input range of 15 mV, which corresponds to the sensor's output range.

temperature measurement

Another area of application for the AD7714 is temperature measurement. Figure 13 outlines the connections from the thermocouple to the AD7714. In this application, the AD7714 operates in its buffered mode to allow the large decoupling capacitors on the front end to eliminate any noise pickup that may be present in the thermocouple leads. When the AD7714 operates in buffered mode, its common-mode range is reduced. To place the thermocouple's differential voltage at the appropriate common-mode voltage, the AIN2 input of the AD7714 is biased at the reference voltage +2.5␣V.

RTD measurement

Figure 14 shows another temperature measurement application for the AD7714. In this case the sensor is an RTD (resistance temperature device), a PT100. The device is a 4-lead resistance temperature detector configuration. There is a voltage drop across the wire resistances RL1 and RL4, but this just changes the common mode voltage. Since the input current to the AD7714 is very low, there is no voltage drop across the wire resistances RL2 and RL3. The source impedance of the lead resistance is small, so it is usually not necessary to turn on the buffer on the AD7714.

If a buffer is required, the common-mode voltage should be set accordingly by inserting a small resistor between the bottom of the RTD and AGND of the AD7714. In the application shown, an external 400µA current source provides the excitation current for the PT100 and generates the reference voltage for the AD7714 through a 6.25 kΩ resistor. Changes in field current do not affect the circuit because the input voltage and reference voltage vary proportionally with field current. However, the 6.25␣kΩ resistor must have a low temperature coefficient to avoid errors due to over temperature of the reference voltage.

data collection

The AD7714 has three differential channels (or five pseudo-differential channels) and is suitable for low bandwidth, high resolution data acquisition systems. Additionally, the three-wire digital interface allows the data acquisition front end to be isolated with only three opto-isolators. As long as the input signals to the AD7714's analog inputs are all positive, the entire system can be operated from a +3␣V or +5V supply. The low power operation of the AD7714 ensures that very little power is passed through the isolation barrier. Figure 15 shows the AD7714 in a stand-alone data acquisition system.

Smart Transmitter

Another area of advantage for the low-power, single-supply, three-wire interface capability is smart transmitters. Here, the entire smart transmitter must work in a 4␣mA to 20␣mA loop. Tolerance in the loop means that the amount of current available to power the transmitter is as low as 3.5␣mA.

The AD7714 consumes only 500␣µA, and the rest of the transmitter still has 3␣mA available. Figure 16 shows a block diagram of a smart transmitter that includes the AD7714. The isolated power required to power the front end is not shown in Figure 16.