feature

PLL generated or direct master clock; low EMI design; 108 dB DAC/107 dB ADC dynamic range and signal-to-noise ratio; -94 dB THD+N; kHz to 192 kHz sample rates; differential ADC input; single-ended DAC output; log volume control with scalable SPI functionality; software-controlled no-click mute; software shutdown; right, left, I2S, and TDM modes; master /Slave mode up to 16 channels in/out; 48-lead LQFP package; suitable for automotive applications.

application

Car audio systems; home theater systems; set-top boxes; digital audio effects processors.

General Instructions

The AD1938 is a high-performance single-chip codec that provides four analog-to-digital converters (ADCs) with inputs and eight digital-to-analog converters (DACs) with single-ended outputs, using analog Devices, Inc. .'s patented multi-bit sigma-delta (Σ-Δ) architecture. An SPI port is included, allowing the microcontroller to adjust volume and many other parameters. The AD1938 is powered by 3.3V digital and analog supplies. The AD1938 is available in a 48-lead (single-ended output) LQFP package. Other members of this family include differential DAC output and IC® control port versions.

The AD1938 is designed for low electromagnetic interference. This consideration is evident in both system and circuit design architectures. By deriving the master clock from the LR clock or from an external crystal using an on-board PLL, the AD1938 eliminates the need for a separate high frequency master clock and can also be used with suppressed bit clocks. The dac and adc use the latest analog device continuous time structure design to further reduce EMI. By using a 3.3V power supply, power consumption is minimized, further reducing emissions.

Typical performance characteristics

theory of operation

Analog-to-Digital Converter (ADC)

There are four ADC channels in the AD1938, configured as two stereo pairs with differential inputs. ADCs can work at nominal sample rates of 48khz, 96khz or 192khz. The ADCs include onboard digital antialiasing filters with 79dB stopband attenuation and linear phase response, operating at an oversampling rate of 128 (48khz, 96khz and 192khz modes). Digital outputs are provided through two serial data output pins (one for each stereo pair) and a common frame clock (ALRCLK) and bit clock (ABCLK). Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line.

The ADC must be driven from a differential signal source for best performance. The input pins of the ADC are connected to internal switched capacitors. To isolate the externally driven op amp from faults caused by the internal switched capacitors, each input pin should be isolated with an external 100Ω resistor in series and a 1 nF capacitor to ground from each input. Such capacitors must be of high quality, such as ceramic NPO or polypropylene film.

The nominal common-mode voltage of the differential inputs is 1.5 V. The voltage at the common-mode reference pin (CM) can be used to bias an external op amp to buffer the input signal (see the Power Supply and Voltage Reference section). The input can also be AC coupled and does not require an external DC bias to cm.

Under serial control, a digital high-pass filter can be switched with an analog-to-digital converter (ADC) to remove residual DC offset. It has a 1.4 Hz, 6 dB per octave cutoff at 48 kHz sampling rate. The cutoff frequency is proportional to the sampling frequency.

Digital-to-Analog Converter (DAC)

The AD1938 DAC channels are arranged as a single-ended, four-stereo pair, providing eight analog outputs for minimal external components. The DAC includes an on-board digital reconstruction filter with 70dB stopband attenuation and linear phase response, operating at an oversampling rate of 4 (48khz or 96khz mode) or 2 (192khz mode). Each channel has its own independently programmable attenuator, adjustable in 0.375dB increments in 255 steps. Digital inputs are provided through four serial data input pins (one for each stereo pair), a common frame clock (DLRCLK), and a bit clock (DBCLK). Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line.

The nominal common-mode DC level of each output pin is 1.5 V, which swings ±1.27 V for a 0 dBFS digital input signal. A single op amp, third-order external low-pass filter is recommended to remove high frequency noise on the output pins. Using low slew rate or low bandwidth op amps can cause high frequency noise and tones to fold down into the audio band; therefore, care should be taken when selecting these components.

The voltage at the common-mode reference pin, CM, can be used to bias an external op amp that buffers the output signal (see the Power Supply and Voltage Reference section).

clock signal

The on-chip phase-locked loop (PLL) can be selected to reference the input sample rate from the LRCLK pin or 256, 384, 512 or 768 times the sample rate for 48 kHz mode from the MCLKI/XI pins. The default value at power-up is 256×f (from the MCLKI/XI pins). In 96 kHz mode, the master clock frequency remains at the same absolute frequency; therefore, the actual multiplier is divided by 2. In 192 kHz mode, the actual magnification is divided by 4. For example, if a device in the AD193x family is programmed for 256 × f mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD193x is subsequently switched to 96 kHz operation (by writing to the SPI port), the frequency of the master clock should remain at 12.288 MHz, or 128 × f. In 192 kHz mode this becomes 64×f.

For all clock modes, the ADC's internal clock is 256 × fS. The DAC's internal clock varies by mode: 512×fS (48 kHz mode), 256×fS (96 kHz mode), or 128×fS (192 kHz mode). By default, the on-board PLL generates this internal master clock from an external clock. Direct 512×f (reference 48 kHz mode) master clock can be used for adc or dac if selected in PLL and clock control 1 register. Note that it is not possible to use a direct clock for ADCs set to 192 kHz mode. It is required to use the on-chip phase-locked loop in this mode.

The PLL can be turned off in the PLL and Clock Control 0 registers. To ensure reliable lock when changing PLL modes, or if the reference clock is unstable at power-up, power down the PLL and power-cycle it when the reference clock is stable.

The internal master clock can be disabled in the PLL and clock control 0 registers to reduce power consumption when the AD1938 is idle. The clock should be stable before enabling.

Unless standalone mode is selected (see the Serial Control Port section), the clock is disabled by reset and must be written to the SPI port for proper operation.

To maintain maximum performance, limit the clock jitter of the internal master clock signal to less than 300 ps rms Time Interval Error (TIE). Even at these levels, if the jitter spectrum contains large spectral peaks, additional noise or tone may appear in the DAC output. If the internal PLL is not used, it is better to use a separate crystal oscillator to generate the main clock. In addition, it is especially important that the clock signal does not pass through an FPGA, CPLD, or other large digital chips (such as a DSP) before being applied to the AD1938. In most cases, this causes clock jitter due to sharing power and ground connections with other unrelated digital output signals. When using a PLL, the jitter in the reference clock is attenuated above a certain frequency according to the loop filter.

reset and power down

The function of the RST pin sets all control registers to their default settings. To avoid pops, reset does not turn off the analog output. After RST is deasserted and the PLL acquires the lock condition, an initialization routine runs in the AD1938. This initialization lasts approximately 256 master clock cycles.

The power-down levels in the PLL and Clock Control 0, DAC Control 1, and ADC Control 1 record the power-down of the corresponding portion. All other register settings are preserved. To ensure proper startup, the RST pin should be pulled low through an external resistor.

Serial control port

The AD1938 has an SPI control port that allows the internal control registers of the ADC, DAC, and clock system to be programmed and read. There is also a standalone mode to run Table 11 without serial control configured. Standalone mode selection is reset using the serial control pin. All registers are set to their default values, but the internal master clock enable is set to 1, and the ADC BCLK and LRCLK master/slave are set by the COUT pin. See Table 11 for details. Standalone mode only supports stereo mode with IS data format and 256f master clock rate. It is recommended to use weak pull-up resistors in applications that have microcontroller bumps. This pull-up resistor ensures that the AD1938 recognizes the presence of the microcontroller.

The SPI control port of the AD1938 is a 4-wire serial control port. This format is similar to the Motorola SPI format except that the input data word is 24 bits wide. The serial bit clock and latches can be fully asynchronous to the sampling rate of the ADCs and DACs. Figure 11 shows the format of the SPI signal.

The first byte is the global address with read/write bits. For the AD1938, the address is 0x04, due to the R/W bit being shifted one bit to the left. The second byte is the AD1938 register address and the third byte is the data.

Power and Voltage References

The AD1938 is designed for use with a 3.3V supply. Separate power pins are provided for the analog and digital sections. These pins should be bypassed with 100 nanofarad ceramic chip capacitors as close as possible to the pins to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22µF should also be provided on the same PCB as the codec. For critical applications, performance can be improved by providing separate power supplies for the analog and digital sections. If this is not possible, it is recommended to isolate the analog and digital supplies by ferrite beads in series with each supply. The analog power supply must be as clean as possible.

All digital inputs are compatible with TTL and CMOS levels. All outputs are driven by a 3.3V DVD supply and are compatible with TTL and 3.3V CMOS levels.

The ADC and DAC internal voltage reference (VREF) is output on the filter and should be bypassed as close to the chip as possible with a parallel combination of 10µF and 100nF. Any external current should be limited to less than 50µA.

The internal reference can be disabled in the PLL and Clock Control 1 registers, and the filter can be driven from an external source. This configuration can be used to scale the DAC output to the power amplifier's clipping level based on the power amplifier's supply voltage. The ADC input gain varies inversely. The overall gain from the ADC input to the DAC output remains the same.

The CM pin is the internal common mode reference. It should be bypassed as close to the chip as possible, with a parallel combination of 47µF and 100 nF. This voltage can be used to bias the external op amp to the common-mode voltage of the input and output signal pins. The output current should be limited to less than 0.5mA source and 2mA sink.

Serial Data Port - Data Format

The eight DAC channels use a common serial bit clock (DBCLK) and a common left and right frame clock (DLRCLK) in the serial data port. The four ADC channels use a common serial bit clock (ABCLK) and left and right frame clocks (ALRCLK) in the serial data port. The clock signals are all synchronized to the sample rate. The normal stereo serial mode is shown in Figure 23.

ADC and DAC serial data mode defaults to . Ports can also be programmed for left-justified, right-justified, and TDM modes. The word width defaults to 24 bits and can be programmed to 16 bits or 20 bits. The DAC serial format is programmable according to the DAC Control 0 register. The polarity of DBCLK and DLRCLK is programmable according to the DAC Control 1 register. The ADC serial format and serial clock polarity are programmable according to the ADC Control 1 register. Both the DAC and ADC serial ports can be programmed as bus masters according to the DAC Control 1 and ADC Control 2 registers. By default, both the ADC and DAC serial ports are in slave mode.

Time Division Multiplexing (TDM) Mode

The AD1938 serial port also has several different TDM serial data modes. The first and most common configuration is shown in Figure 12 and Figure 13. In Figure 12, the ADC serial port outputs a data stream consisting of four on-chip ADCs and four unused slots. In Figure 13, eight on-chip DAC data slots are packed into one TDM stream. In this mode, both DBCLK and ABCLK are 256f.

The I/O pins of the serial port are defined according to the selected serial mode. See Table 12 for a detailed description of the function of each pin in TDM and Auxiliary modes.

The AD1938 allows systems with more than eight DAC channels to be easily configured through the use of an auxiliary serial data port. The DAC TDM-AUX mode is shown in Figure 14. In this mode, the auxiliary channel is the last four time slots of the TDM data stream. These slots are extracted and output to the AUX serial port. It should be noted that due to the high DBCLK frequency, this mode is only available at 48 kHz/44.1 kHz/32 kHz sample rates.

The AD1938 also allows system configurations with more than four ADC channels, as shown in Figure 15 and Figure 16, using 8 ADCs and 16 ADCs, respectively. Also, due to the high ABCLK frequency, this mode is only available at 48 kHz/44.1 kHz/32 kHz sample rates.

Combining the AUX ADC and DAC modes results in a system configuration of 8 ADCs and 12 DACs. The system then consists of two external stereo ADCs, two external stereo DACs, and an AD1938. This mode is shown in Figure 17 (AUX ADC and DAC combined mode).

Daisy Chain Mode

The AD1938 allows a daisy-chain configuration to expand the system to 8 ADCs and 16 DACs (see Figure 18). In this mode, the DBCLK frequency is 512f. The first 8 time slots of the DAC TDM data stream belong to the first AD1938 in the chain, and the last 8 time slots belong to the second AD1938. The second AD1938 is the device connected to the DSP TDM port.

To accommodate 16 channels at a 96 kHz sample rate, the AD1938 can be configured in two-wire TDM mode, as shown in Figure 19. This mode allows for a slower DBCLK than is normally required for single-wire TDM mode.

Likewise, the first four channels of each TDM input belong to the first AD1938 in the chain, and the last four channels belong to the second AD1938.

Two-wire TDM mode can also be used to send data to the AD1938 at a 192 kHz sample rate, as shown in Figure 20.

There are two configurations that allow the ADC ports to operate in daisy-chain mode. The first is the ABCLK of the 256F shown in Figure 21. The second configuration is shown in Figure 22. Note that in 512f ABCLK mode, the ADC channels occupy the first 8 slots; the last 8 slots are empty. The TDM unit of the first AD1938 must be grounded in all modes of operation.

The I/O pins of the serial port are defined according to the selected serial mode. See Table 13 for a detailed description of each pin function. See Figure 26 for a typical AD1938 configuration with two external stereo DACs and two external stereo ADCs.

Figure 23 to Figure 25 show the serial mode format. For maximum flexibility, the polarities of LRCK and BLK are programmable. In these figures, all clocks are shown with normal polarity. The default mode is .

control register

definition

The global address of the AD1938 is 0x04, due to the left shift of the R/W bit by one. All registers are reset to 0 except for the DAC volume registers that are set to full volume.

Note that the first setting in each control register parameter is the default setting.

Additional mode

The AD1938 provides several additional modes for board-level design enhancement. To reduce EMI in board-level designs, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM data transfer mode that does not require high-speed DBCLK. This configuration applies when the AD1938 master clock is generated by a PLL with DLRCLK as the PLL reference frequency.

To relax the AD1938's setup time requirements for high-speed TDM data transfers, the AD1938 can utilize the falling edge of DBCLK to lock the data. This effectively dedicates the entire BCLK cycle to the setup time. This mode is useful when the source has a large delay time in the serial data driver. Figure 28 shows the pipeline pattern for this data transfer.

On the ADC serial data port, both no-blind and pipelined modes are available.

Application circuit

Typical application circuits are shown in Figure 29 to Figure 32. Figure 29 shows a typical ADC input filter circuit. The recommended loop filters for the LR clock and the master clock as a PLL reference are shown in Figure 30. The output filter for the DAC output is shown in Figure 31 and Figure 32.

Dimensions

automotive products

The AD1938WBSTZ and AD1938WBSTZ-RL models offer controlled fabrication to support the quality and reliability requirements of automotive applications. Note that specifications for these models may differ from commercial models; therefore, designers should carefully review the Specifications section of this data sheet. Only the automotive grade products shown are available for automotive applications. Please contact your local Analog Devices account representative for specific product ordering information and to obtain specific vehicle reliability reports for these models.