General

The FM93C46 is a 1024 -bit CMOS non-volatile EEPROM as a 64 x 16-bit array. The device has a microwire interface which is a 4-wire serial bus with chip select (CS), clock (SK), date in (DI) and date out (DO) signals. The interface is compatible with many standard microcontrollers and microprocessors. There are 7 instructions read, write, erase and write enable/disable operations on the FM93C46. this. Devices are fabricated using Fairchild's floating gate CMOS process for high reliability, high endurance and low power consumption. The LZ and L versions of the FM93C46 offer very low standby current making them suitable for low power applications. This device is available in SO and TSSOP packages for small space considerations. functional map

feature

Wide VCC 2.7V-5.5V 200A typical active current 10th typical current backup 1A typical current backup (L) 0.1 current typical backup (LZ) Erase command is required before write command Automatic timing write cycle Device status during programming cycle 40 Years Retention Day Persistence: 1,000,000 Data Changes Supplied Packaging: 8-pin SO, 8-pin DIP, 8-pin TSSOP

Pin Description Chip Select (CS) This is an active high input pin for the FM93C46 EEPROM (device) generated by the host controlling the device. A climax level on this pin selects a device, a low level deselects the device. All serial communication with the device is only enabled when this pin is held high. However, this pin cannot be tied high permanently, as a rising edge of this signal requires a reset of the internal state machine that accepts a new cycle and a falling edge to initiate internal programming after a write cycle. All activity on the SK, DI, and DO pins is ignored when CS is low. Serial Clock (SK) This is the input pin of the device and is controlled by the device. This is a clock signal used to synchronize communications between the host and the device. All input information (DI) of the device is latched on the rising edge of this clock input, which is the clock input when the output data (DO) of the device is driven by the rising edge. This pin is gated by the CS signal. Serial Input (DI) This is the input pin of the device, generated by the host that controls the device. The host plugs this pin into the device by serially transferring input information (start bits, opcode bits, array address, and data). This input information is latched on the rising edge of SCK. This pin is gated by the CS signal. Serial Out (DO) This is the output pin of the device used to transmit output data to the control host through this pin. Output data is shifted serially from the rising edge of SCK onto this pin. This pin is only active when a device is selected. Microwire Interface Typical communication on the Microwire bus is through CS, SK, DI and DO signals.

To facilitate the memory array, a set of 7 instructions is implemented on the FM93C46. The format of each instruction is shown in Table 1. Indicates that each of the 7 instructions is described under a separate instruction. Start Bit This is a 1-bit field and is the first bit entered into the device when the microfilament cycle begins. This bit must be '1' for a valid cycle to start. Any digit preceding a "0" can be recorded to be set before a timing "1". Opcode This is a 2-bit field and should be followed by the start bit. These two bits (and the 2 MSBs of the address field) select the special instruction to execute. Address Field This is a 6-bit field and should be followed by the opcode bits. In the FM93C46, all 6 bits are used for read, write and erase instructions. In all other instructions, the MSB 2 bits are used to decode the instruction (as well as the opcode bits). Data Field This is a 16-bit field and should be followed by the address bits. This field is only required for WRITE and WRALL instructions. D15 (MSB) is clocked first and D0 (LSB) is clocked last (both during write and read).

Function description

A typical microfilament cycle first selects the device (turns the CS signal high). Once the device is selected, a valid start bit ("1") shall be emitted to correctly identify the loop. Then, the 2-bit opcode for the appropriate instruction should be issued. After the opcode bits, the 6-bit address information should be posted. For some instructions, some of these 6 bits are don't care values (can be "0" or "1"), but values should still be emitted. According to the instruction follow the address information (WRITE and WRALL), send out 16-bit data. Otherwise, according to the instruction (read), the device starts driving the data on the output DO line. Other instructions perform certain control functions and do not process data bits. The microfilament cycle ends when the CS signal goes low. But after confirming the command, the falling edge of the CS signal starts the inner loop (programming), and the device is completing the inner loop. Each of these 7 instructions is described in detail in the following sections. 1) The read (read) read instruction allows to read data from the selected location in the memory array. Input information (start bit, opcode, and (address) for this specification should be issued in accordance with the following requirements in Table 1. When valid input information is received, the opcode and address are decoded, and then 16 bits are entered from the selected memory location Serial output shift register. This 16-bit data is then shifted out on the DO pin. The D15 bit (MSB) is shifted out first and the D0 bit (LSB) is shifted out last.

A dummy bit (logical 0) precedes this 16-bit data output string. The output data starts changing on the rising edge of the SK clock. When reading 16 bits of data later, the CS signal can be pulled down to the end of the read cycle. See Reading Cycle Diagrams. 2) Write Enable (WEN) When VCC is applied to the part, it is in the Write Disable (WDS) state. Therefore, all programming operations must be preceded by a Write Enable (WEN) instruction. A write executes the Enable command and programming remains enabled until a Write Disable (WDS) command is executed or VCC is completely removed from the part. The input information (start bit, opcode and address) is listed in Table 1. The device ends this cycle when the CS signal goes low. Execution of reading instruction is independent of text instruction. See Writing Enabled Cycle Graphs.

3) Write (Write) The write instruction allows to perform a write operation to the specified location in the memory with the specified data. This description is only valid if the device has write enabled (see WEN instruction). The input information (start bit, opcode, address, and data) for this purpose should be issued with a write command as listed in Table 1. After inputting the last bit of data (D0 bit), the CS signal must be lowered before the next rising edge of the SK clock. This falling edge of CS initiates an automatic timed programming loop. An internal programming cycle that takes two weeks (refer to the appropriate DC and AC electrical characteristics tables) to complete. During this time the device is still busy and not ready for other commands. The state of the internal programming cycle can bring the CS signal high again after any tCS interval. when? The CS signal is high and the DO pin indicates the ready/busy state of the chip. DO=logic 0 means programming is still in progress. DO=Logical 1 indicates that programming is complete and the device is ready to accept another command. No SK clock needs to be provided during this status poll. When the device is busy, it is recommended not to use the new command release. See Write Cycle Diagram. It is also recommended to follow this instruction (after the device is ready) to use the Write Disable (WDS) instruction to prevent data corruption due to spurious noise, accidental writes, etc. 4) Write all (WRALL) The Write all (WRALL) instruction is similar to the Write instruction except that the WRALL instruction will simultaneously write to all memory locations with the data pattern specified in the instruction. This command is only valid when the device is enabled for write operations (see instructions). For this input information (start bit, opcode, address and data) WRALL instruction should be issued as listed in Table 1. After inputting the last bit of data (D0 bit), the CS signal must be lowered before the next rising edge of the SK clock.

This falling edge of CS initiates an automatic timed programming loop. An internal programming cycle that takes two weeks (refer to the appropriate DC and AC electrical characteristics tables) to complete. During this time the device is still busy and not ready for other commands. The status of the internal programming can be polled as described under the write instruction description. It is recommended not to issue new commands when the device is busy. Refer to the full write cycle diagram. 5) Write Disable (WDS) The Write Disable (WDS) instruction disables and should follow all programming operations. Instructions following this valid write instruction will protect against accidental data disturbances due to spurious noise, glitches, inadvertent, etc. Input information (start bits, opcodes, and addresses) for this write should be issued as listed in Table 1 for the WDS instruction. This is when the CS signal goes low. The execution of the read instruction is independent of the WDS instruction. See write disable cycle diagram. 6) Erase (erase) Erase instruction will specify the position of logic "1" state. Input information (start bits, opcodes and addresses) for this WDS instruction shall be issued as listed under Table 1. After the last bit of data (A0 bit) is input, the CS signal must go low before the next rising edge of the SK clock. This falling edge of CS initiates a self-timed programming loop. It requires tWP time (refer to the corresponding DC and AC Electrical Characteristics table) for the completion of the internal programming cycle. During this time, the device is still busy and cannot prepare another instruction. Internally programmed status can be polled as described under "Write Command Description". When the device is busy, it is recommended not to use the new command release. See Clear Cycle Diagram.

The Erase all command programs all positions as a logic "1" country. For this input information (start bit, opcode and address) should be issued as listed in Table 1 with the WDS instruction. After inputting the last bit of data (A0 bit), the CS signal must be lowered before the next rising edge of the SK clock. This falling edge of CS initiates an automatic timed programming loop. An internal programming cycle that takes two weeks (refer to the appropriate DC and AC electrical characteristics tables) to complete. During this time the device is still busy and not ready for other commands. The status of the internal programming can be polled as described under the write instruction description. It is recommended not to issue new commands when the device is busy. Refer to the erase full cycle diagram. Note: Fairchild CMOS EEPROMs do not require an "erase" or "erase all" command preceding a "write" or "write all" command. This one includes "erase" and "erase all" instructions to keep with earlier technology EEPROMs. Clearing Ready/Busy Status During programming, the data output pins will show the programming status as busy (low) or ready (high) when CS is high (when CS is low). To reiterate, during the programming process, it is possible to bring the CS pin high and low any number of times to check the programming status without affecting the programming operation. Once programming is complete (output is in ready state), output is "cleared" (back to normal tri-state state) by clocking on the start bit. After the start bit is clocked, the output will return to the tri state condition. When punching, this start bit can be a command string, or CS can be turned down again to reset the internal circuitry all. See Clear Ready state diagram. Related Documents Application Note: AN758 - Using Fairchild's MICROWIRE™ EEPROM.