Virtex II Feature Overview, Industry First Platform FPGA Solutions, IP Immersion Architecture - Densities from 40K to 8M System Gates - 420 MHz Internal Clock Speed (Advanced Data) - 840 +Mb/s I/O (Advanced Data) SelectRAM ™ Memory Hierarchy - 3 Mb True Dual Port™ RAM in 18 KB Blocks SelectRAM Resources - Up to 1.5 Mb Distributed SelectRAM Resources - High Performance Interface to External Memory DDR-SLDM Interface FCRAM Interface QDR∑-SRAM Interface Sigma RAM Interface Function Dedicated 18-bit X 18-bit Multiplier Block Fast Look-Ahead Carry Logic Chain Multiplexer and extensive input function support - Horizontal cascade chain and product support - High performance clock management circuit with internal tri-state - Up to 12 DCM (Digital Clock Manager) modules * Accurate clock skew * Flexible frequency synthesis . High Resolution Phase Shift - 16 Global Clock Multiplexer Buffers, Active Interconnect Technology - 4th Generation Segment Routing Architecture - Predictable, Fast Routing Delay, Independent of Fan-Out, SelectI/O-Ultra Technology - Up to 1,108 user I/Os - 19 single-ended and 6 differential standards - programmable receiver current per I/O (2mA to 24mA)
- Digital Controlled Impedance (DCI) I/O: On-chip termination resistors for single-ended I/O standards - PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz, and CardBus compatible - Differential signaling 840 Mb/s low Voltage Differential Signaling Input/Output (LVDS) with Current Mode Driver Bus LVDS I/O Lightning Data Transfer (LDT) I/O Current Driver Buffer Low Voltage Positive Emitter Coupled Logic (LVPECL) I/O Built-in DDR Input and Output Registers - Proprietary High Performance SelectLink Technology High Bandwidth Data Path Double Data Rate (DDR) Link Web-based HDL Generation Methodology Supported by Xilinx Foundation and Alliance™ Family Development Systems - Integrated VHDL and Verilog Design Flow - Assembly 10M System Gate Design - Internet Team Design (ITD) Tool, SRAM Based on System Configuration - Fast SelectMAP™ Configuration - Triple Data Encryption Standard (DES) Security Option (Bitstream Encryption) - IEEE1532 Support - Partial Reconfiguration - None Limit Programmability - Read and Write Capability: 0.15µm 8-layer metal process with 0.12µm high-speed transistors: 1.5 V (VCCNT) core power supply, dedicated 3.3 V VCUAX auxiliary and VCCO I/O power supplies: IEEE 1149.1 compliant Boundary Scan logic support : 100% factory tested on three standard fine pitches (0.80mm, 1.00mm and 1.27mm) for flip-chip and wire-bonded Ball Grid Array (BGA) packages

Overview The Virtex II family is a high-performance platform FPGA based on IP cores and custom modules, ranging from low-density to high-density designs. This family provides complete solutions for telecom, wireless, networking, video and digital signal processor applications, including PCI, LVDS and DDR interfaces. The leading 0.15μm/0.12μm CMOS 8-layer metal process and Virtex II structure are optimized for high speed and low power consumption. Combining a variety of flexible features and a wide range of densities up to 10 million system gates, the ViTEX II family enhances programmable logic design capabilities and is a powerful replacement for mask-programmed gate arrays. As shown in Table 1, the Virtex II family consists of 12 members ranging from 40K to 10M. Packaged products include 0.80mm, 1.00mm and 1.27mm pitch ball grid array (BGA) packages. In addition to traditional wire bond interconnects, flip chip interconnects are also used in some BGA products. The use of flip-chip interconnects provides more I/O than similarly packaged wire-bond versions. Flip-chip structure provides a combination of high pin count and high thermal capacity

Architecture Virtex II Array Overview Virtex II devices are user-programmable gate arrays with various configurable elements. The Virtex II architecture is optimized for high-density and high-performance logic designs. Programmable devices consist of Input/Output Blocks (IOBs) and Internal Configurable Logic Blocks (CLBs).
Programmable I/O blocks provide the interface between package pins and internal configurable logic. The most popular and cutting-edge I/O standards are supported by programmable IOBs. The internal configurable logic consists of four main elements, which are organized in an array of rules. Configurable logic blocks (CLBs) provide functional elements for combinational and synchronous logic, including basic storage elements. BUFTs (3-state buffers) associated with each CLB element drive dedicated segmentable horizontally routable resources. The block select RAM memory module provides a large 18 Kbit storage unit of true dual port RAM. The multiplier blocks are 18-bit x 18-bit dedicated multipliers. The DCM (Digital Clock Manager) module provides self-calibrating, all-digital solutions for clock distribution delay compensation, clock multiplication and division, coarse-grained and fine-grained clock phase shifting. A new generation of programmable routing resources called active interconnect technology interconnects all these elements. A Generic Routing Matrix (GRM) is a group of routing switches. Each programmable element is bound to a switch matrix, allowing multiple connections to a common routing matrix. The entire programmable interconnect is layered and designed to support high-speed designs.

All programmable elements, including routing resources, are controlled by values stored in static memory cells. These values are loaded into memory cells during configuration and can be reloaded to change the function of programmable elements. Virtex II Features This section briefly describes the Virtex II features. Input/Output Blocks (IOBs) IOBs are programmable and fall into the following categories: Input blocks with selectable single data rate or double data rate (DDR) registers Outputs with selectable single data rate or DDR registers block, and optional 3-state buffer, to drive bidirectional blocks (any combination of input and output configurations) directly or through a single or DDR register that is either edge-triggered D-type flip-flops or level-sensitive latches device. The IOB supports the following single-ended I/O standards: LVTTL, LVCMOS (3.3 V, 2.5 V, 1.8 V and 1.5 V) PCI-X at 133 MHz, PCI (3.3 V at 33 MHz and 66 MHz) GTL and GTLP, HSTL (levels I, II, III and IV)

The SSTL (3.3 V and 2.5 V, Class I and Class II) AGP-2X Digitally Controlled Impedance (DCI) I/O feature automatically provides chip termination for each I/O element. IOB components also support the following differential signal input/output standards: LVDS • BLVDS (Bus LVDS) ULVDS, LDT, LVPECL Each differential pair uses two adjacent pads. Two or four IOB blocks are connected to a switch fabric to access routing resources. Configurable Logic Block (CLB) CLB resources include four slices and two 3-state buffers. Each part is equivalent and contains: two function generators (F&G) two storage elements, arithmetic logic gates, large multiplexers, extensive functional capabilities, fast carry lookahead chains, horizontal cascade chains ( OR gate) function generator F&G can be configured as a 4-input look-up table (LUT), as a 16-bit shift register, or as a 16-bit distributed SelectRAM memory. Furthermore, the two storage elements are either edge-triggered D-type flip-flops or level-sensitive latches. Each CLB has internal fast interconnects and connects to a switch fabric to access general routing resources. Block SelectRAM Memory Block SelectRAM memory resources are 18kb of true dual-port RAM, programmable ranging from 16kx1-bit to 512x 36-bit, with different depth and width configurations. Each port is fully synchronized and independent, offering three "read and write" modes. Block selection memory is cascadable, enabling large embedded memory blocks. The supported memory configurations for dual-port and single-port modes are shown in Table 3.
A multiplier block is associated with each SelectRAM memory block. The multiplier block is a dedicated 18 x 18-bit multiplier and is optimized for operation based on the block SelectRAM contents on one port. The 18x 18 multiplier can be used independently of the block SelectRAM resource. Read/multiply/accumulate operations and DSP filter structures are very efficient. Both SelectRAM memory and multiplier resources are connected to the four switch matrices to access conventional routing resources. The global clock DCM and global clock multiplexer buffer provide a complete solution for designing high-speed clocking schemes. Up to 12 DCM blocks are available. To generate a de-skewed internal or external clock, each DCM can be used to eliminate clock distribution delays. The DCM also offers 90 degree, 180 degree and 270 degree phase shifted versions of the output clock. Fine-grained phase shifting provides high-resolution phase adjustment in increments of 1/256 of the clock period. Very flexible frequency synthesis provides a clock output frequency equal to any M/D ratio of the input clock frequency, where M and D are two integers. See Virtex-II Electrical Characteristics for precise timing parameters. Virtex II devices have 16 global clock MUX buffers with up to 8 clock networks per quadrant. Each global clock MUX buffer can select one of two clock inputs and fail-safe switch from one clock to the other. Each DCM block can drive up to 4 of the 16 global clock MUX buffers. Routing resources IOB, CLB, block SelectRAM, multiplier and DCM elements all use the same interconnect scheme and the same access to the global routing matrix. Shared timing models greatly improve the predictability of high-speed design performance. There are 16 global clock lines in total, 8 in each quadrant. In addition, 24 long vertical and horizontal lines per row or column and numerous auxiliary and local routing resources provide fast interconnection. Virtex II buffered interconnects are relatively immune to net fanout, and the interconnect layout is designed to minimize crosstalk. Horizontal and vertical routing resources per row or column include: 24 long lines, 120 hex lines, 40 double lines, 16 direct connect lines (total of four directions)

Boundary Scan The boundary scan instructions and associated data registers support a standard method of accessing and configuring Virtex II devices compliant with IEEE Std 1149.1-1993 and 1532. Implemented system mode and test mode. In system mode, Virtex II devices perform their intended tasks even when executing non-test boundary scan instructions. In test mode, the boundary scan test command controls the I/O pins for testing. The Virtex II Test Access Port (TAP) supports BYPASS, PRELOAD, SAMPLE, IDCODE and USERCODE non-test commands. EXTEST, INTEST and HIGHZ test commands are also supported. Configuration Virtex II devices are configured by loading data into the internal configuration memory, using the following five modes: Slave Serial Mode, Master Serial Mode, Slave Select Mapped Mode, Master Select Mapped Mode, Boundary Scan Mode (IEEE1532) There is a Data Encryption Standard (DES) decryptor on the chip to protect the bitstream. Configuration information can be selectively encrypted using one or two triple DES key sets.
Readback and Integrated Logic Analyzer configuration data is stored in Virtex II configuration memory and can be read back for verification. In addition to configuration data, the contents of all flip-flop/latch, distributed SelectRAM, and block SelectRAM memory resources can be read. This feature is useful for real-time debugging. The Integrated Logic Analyzer (ILA) core and software provide a complete solution for accessing and verifying Virtex II devices. VIETEX II device/package combinations and largest I/O wire bond and flip chip packages are available. Tables 4 and 5 show the maximum possible number of user I/OSs in wire-bonded and flip-chip packages, respectively. Table 6 shows the number of available user I/Os for all device/package combinations. CS stands for wire bond chip scale ball grid array (BGA) (0.80 mm pitch). FG stands for wire bond fine pitch BGA (1.00 mm pitch). FF stands for Flip Chip Fine Pitch BGA (1.00 mm pitch). BG stands for Standard BGA (1.27 mm pitch). BF stands for Flip Chip BGA (1.27 mm pitch). The I/O count per package includes all user I/O but 15 control pins (CCLK, DONE, M0, M1, M2, PROG B, PWRDWN B, TCK, TDI, TDO, TMS, HSWAP EN, DXN , DXP and RSVD) and VBATT.