Features 7.5 ns to pin logic delay on all pins. F CNT to 125 MHz 72 macrocells with 1600 usable gates. Up to 72 user I/O pins. 5V in System Programmable (ISP). Endurance of 10,000 program/erase cycles. Program/erase over the full commercial voltage and temperature range: Enhanced PIN lock structure. Flexible 36V18 function blocks - 90 product terms drive any or all of the 18 macrocells within the function block - global and product terms clock, output enable, set and reset signals, extensive IEEE Std 1149.1 boundary scan (JTAG) support

Programmable power reduction mode in each macrocell, spin rate control for individual outputs, user programmable ground pin function, extended mode safety feature for design protection, high drive 24mA output, 3.3V or 5V input /Output function, advanced CMOS 5V flash memory technology, support parallel programming of multiple XC9500s at the same time, provide 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP package instructions
The XC9572 is a high-performance CPLD that provides advanced system programming and testing capabilities for general-purpose logic integration. It consists of four 36V18 function blocks, providing 1600 usable gates with a propagation delay of 7.5ns.
Power Management The power consumption of the XC9572 can be reduced by configuring the macrocell into standard or low-power operating modes. Turn off unused macrocells to minimize power consumption.
The operating current for each design can be approximated for specific operating conditions with the following equation: ICC(MA) = MCHP(1.7) + MCLP(0.9) + MC (0.006 mA/MHz) f:
MCHP=Macrocell in high performance mode MCLP=Macrocell in low power mode MC=Total number of macrocells used
f = clock frequency (MHz)
Typical calculations for the XC9572 device are shown.

XC9572 Architecture Note: The function block output (indicated by the black line) directly drives the I/O block