feature

iso; regulated 3.3 V or 5.0 V output; output power up to 500 MW; four dc-to-25 Mbps (NRZ) signal isolation channels; 16-lead SOIC package, 7.6 mm creepage; high temperature operation: 105 °C max; High Common Mode Transient Immunity: >25kv/μs; Safety and Regulatory Approvals; UL Recognized; 2500 V rms, 1 minute per UL 1577; CSA Parts Acceptance Notice #5A; VDE Certificate of Conformity (pending); IEC 60747-5 -2 (VDE 0884, part 2) VIORM = 560 V peak.

application

RS-232 /RS-422/RS-485 Transceivers; Industrial Fieldbus Isolation; Power Start Bias and Gate Drives; Isolated Sensor Interfaces; Industrial Programmable Logic Controllers.

General Instructions

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are quad-channel digital isolators with isoPower® integrated isolated DC-DC converters. Based on Analog Devices, Inc., iCoupler® technology, the dc-dc converter operates at 5.0 V or 3.3 V from a 5.0 V input supply, or at 3.3 V from a 3.3 V supply at the power levels shown in Table 1 , providing up to 500 mW of regulated, isolated power. In low power, isolated designs, these devices eliminate the need for a separate, isolated dc-dc converter. In dc-dc converters, iCoupler chip-scale transformer technology is used to isolate logic signals from power and feedback paths. The result is a small form factor, total isolation solution.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 isolators provide four independent channels of isolation in various channel configurations and data rates (see the ordering guide for more information).

ISO Power uses high-frequency switching elements to transmit power through a transformer. Special care must be taken during printed circuit board (PCB) layout to meet emission standards. Refer to the AN-0971 application note for board layout recommendations.

Typical performance characteristics

the term

IDD1 (Q)

I is the minimum operating current at the V pin when there is no external load on V and the I/O pin is operating below 2 Mbps without additional dynamic supply current. I reflect the current minimum running state.

IDD1 (D)

I is the maximum dynamic load condition represented by the typical input supply current with a full capacitive load at a maximum data rate of 25 Mbps with all channels driven simultaneously. Resistive loads on the output should be handled separately from dynamic loads.

IDD1 (max)

I is the input current under full dynamic and V load conditions.

ISO (load)

ISO(LOAD) is the current available to the load.

tPHL propagation delay

The tPHL propagation delay is from the falling edge of the VIx signal to the 50% falling horizontal edge of the VOx signal.

tPLH propagation delay

The tPLH propagation delay is from the rising edge of the VIx signal to the 50% level of the rising edge in the VOx signal.

Propagation delay skew

tPSK is tPHL and/or recommended operating conditions at the same operating temperature, supply voltage and output load.

Channel-to-Channel Matching (tPSKCD/tPSKOD)

Channel-to-channel matching is when operating under the same load.

Minimum pulse width

The minimum pulse width is the shortest pulse width that guarantees the specified pulse width distortion.

maximum data rate

The maximum data rate is the fastest data rate that guarantees the specified pulse width distortion.

application information

The dc-to-dc converter portion of the ADuM5401/ADuM5402/ADuM5403/ADuM5404 operates on the same principle as most switching power supplies. It has a secondary side controller structure with isolated pulse width modulation (PWM) feedback. The V power supply is provided to the oscillator circuit, which converts the current into a chip-scale air-core transformer. The power delivered to the secondary side is rectified and regulated to 3.3 V or 5 V. The secondary (V) side controller regulates the output by creating a PWM control signal that is sent to the primary (V) side by a dedicated I-coupler data channel. PWM modulates the oscillator circuit to control the power sent to the secondary side. Feedback can significantly improve power and efficiency.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 implement undervoltage lockout (UVLO) with hysteresis on the V supply input. This feature ensures that the converter does not go into oscillation due to input power noise or slow power input ramp rates.

printed circuit board layout

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 digital isolators feature a 0.5W equal power integrated DC-DC converter, eliminating the need for external interface circuitry for the logic interface. Power supply bypassing is required at the input and output power pins (see Figure 25). Note that low ESR bypass capacitors are required between pins 1 and 2 and between pins 15 and 16, as close to the chip pads as possible.

The power section of the ADuM5401/ADuM5402/ADuM5403/ADuM5404 uses a 180mhz oscillator frequency to efficiently transfer power through its chip-scale transformer. Additionally, the normal operation of the iCoupler data section can introduce switching transients on the power supply pins. Several operating frequencies require bypass capacitors. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation requires a large value capacitor. They are most conveniently connected between pins 1 and 2 of V and between pins 15 and 16 of V.

To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor value is 0.1µF and 10µF for V and V. Smaller capacitors must have lower ESR; for example, ceramic capacitors are recommended.

The total lead length between the ends of the low ESR capacitor and the input power pins must not exceed 2 mm. Installing bypass capacitors with line lengths longer than 2 mm may cause data corruption. Consider bypassing the connections between pin 1 and pin 8 and between pin 9 and pin 16, unless both common ground pins are connected together near the package.

Ensure that plate coupling on the isolation barrier is minimized in applications involving high common mode transients. Also, design the board layout so that any coupling, when it occurs, affects all pins on a given component side equally. Failure to ensure this may result in voltage differences between pins exceeding the absolute maximum ratings of the device as specified in Table 19, resulting in latch-up and/or permanent damage.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are devices that consume approximately 1 watt of power when the power supply is operating at full load and maximum speed. Because it is not possible to apply heat sinks to isolated devices, these devices mainly rely on dissipating heat to the PCB through the GND pin. If the device is used at high ambient temperatures, provide a thermal path from the ground pins to the PCB ground plane. The board layout in Figure 25 shows the enlarged pads for pins 8 and 9. A large diameter through hole should be used from the pad to the ground, and a power strip should be used to reduce inductance. Multiple vias should be implemented from the pad to the ground plane to significantly reduce the temperature inside the chip. The size of the expansion pad is determined by the designer and depends on the available board space.

Thermal Analysis

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 parts are connected to the split leadframe by four internal dies and two die attach blades. For thermal analysis, the die was treated as a thermal unit and the maximum junction temperature was reflected in θ in Table 14. Values for θ are based on measurements of parts installed on JEDEC standards, Youth Achievement Organization Youth Achievement Organization

Four layers of wooden planks with thin and wide traces and still air. Under normal operating conditions, the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices operate at full load over the entire temperature range without reducing output current. However, following the recommendations in the PCB layout section will reduce thermal resistance to the PCB, allowing increased thermal margin at high ambient temperatures.

Propagation delay related parameters

Propagation delay is a parameter that describes the time it takes for a logic signal to propagate through a component (see Figure 26). The propagation delay to a logic low output may differ from the propagation delay to a logic high output.

Pulse width distortion is the largest difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is maintained.

Channel-to-channel matching refers to the maximum amount by which propagation delays differ within a single channel.

ADuM5401/ADuM5402/ADuM5403/ADuM5404 components.

Propagation delay skew is the maximum amount of propagation delay between multiple ADUM5401 /ADUM5402/ADUM5403/ADUM5404 components operating under the same conditions.

Initiate behavior

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 do not contain a soft-start circuit. Therefore, the starting current and voltage characteristics must be considered when designing the device.

When the voltage is V, when the UVLO minimum voltage is reached, the input switch circuit starts to work and draw current. The switching circuit drives the maximum available power to the output until the regulated voltage at which PWM control begins is reached. The amount and time of current required to reach the regulated voltage depends on the load and V slew rate.

With a fast V slew rate (200 μs or less), the peak current draws to 100 mA/V of V. The input voltage is much faster than the output can turn on, so the peak current is proportional to the maximum input voltage.

When V transitions are slow (in the millisecond range), the input voltage does not change rapidly when V reaches the UVLO minimum voltage. The current fluctuation is about 300mA because V is almost constant at the 2.7 V UVLO voltage. The behavior during startup is similar to that when the device load is short-circuited; these values are consistent with the short-circuit current shown in Figure 14.

When booting the device for V=5 V operation, do not limit the current available at the V supply pin to less than 300 mA.

If the current limiter clamps the V voltage during startup, the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices may not be able to drive the output to the regulation point.

As a result, the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices can draw large amounts of current at low voltages for extended periods of time.

The output voltage of the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices exhibits V overshoot during startup. If this overshoot could damage components connected to V, a voltage limiting device such as a Zener diode can be used to clamp the voltage. Typical behavior is shown in Figure 19 and Figure 20.

Electromagnetic Interference Considerations

The dc-dc converter portion of the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices must operate at 180mhz for efficient power transfer through a small transformer. This creates high frequency currents that can propagate in the board ground and power planes, creating fringe and dipole radiation between the primary and secondary ground planes. For applications using these devices, a grounded cabinet is recommended. If grounding the case is not possible, follow good RF design practices in PCB layout. See AN-0971 application note for board layout recommendations

DC Correctness and Magnetic Field Immunity

Positive and negative logic transitions at the input of the isolator cause narrow pulses (~1ns) to be sent through the transformer to the decoder. The decoder is bistable, so it can be set or reset with a pulse, indicating input logic transitions. In the absence of more than 1 μs logic transitions at the input, a periodic set of refresh pulses indicating the correct input state is sent to ensure dc correctness at the output. If the decoder does not receive internal pulses longer than about 5µs, the inputs are assumed to be unpowered or nonfunctional, and the isolated outputs are forced to their default low state by a watchdog timer circuit. This should occur in the ADuM5401/ADuM5402/ADuM5403/ADuM5404 during power-up and power-down operations.

Magnetic Field Immunity Limits

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are set by the condition that the induced voltage in the receiving coil of the transformer is large enough to incorrectly set or reset the decoder. The following analysis defines the conditions under which this may occur. Check the 3.3V operating condition for the ADuM5401/ADuM5402/ADuM5403/ADuM5404 as it represents the most susceptible operating mode.

The pulses at the transformer output have an amplitude greater than 1 V. The decoder has a sense threshold of approximately 0.5 V, creating a 0.5 V margin to tolerate the induced voltage. The voltage induced by the receiver coil is given by:

in:

β is the magnetic flux density (Gaussian).

rn is the radius (cm) of the nth turn of the receive coil.

N is the total number of turns of the receiving coil.

Given the geometry of the receive coils in the ADuM5401/ADuM5402/ADuM5403/ADuM5404 and the required induced voltage to be at most 50% of the decoder's 0.5 VA margin, calculate the maximum allowable magnetic field as shown in Figure 27.

For example, at a magnetic field frequency of 1 MHz, a maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 volts on the receiving coil. This voltage is approximately 50% of the sense threshold and does not cause faulty output transitions. Similarly, if such an event occurs during the transmit pulse (and has the worst polarity), reduce the receive pulse from >1.0v to 0.75v, still well above the decoder's 0.5v sensing threshold.

The flux density values above correspond to specific amounts of current at a given distance from the ADuM5401/ADuM5402/ADuM5403/ADuM5404 transformers. Figure 28 presents these allowable current amplitudes as a function of frequency for selected distances. As shown in Figure 28, the ADuM5401/ADuM5402/ADuM5403/ADuM5404 are extremely immune and can only be affected by very large currents operating at high frequencies very close to the components. For the 1 MHz example, a 0.5 kA current needs to be placed 5 mm from the ADuM5401/ADuM5402/ADuM5403/ADuM5404 to affect the operation of the device.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 Second Reassure Note that under a combination of strong magnetic fields and high frequencies, any loops formed by the PCB traces will generate enough error voltages to trigger the thresholds of subsequent circuits. Be careful when laying out these traces to avoid this possibility.

Power consumption

The V power input provides power for the I-coupler data channel as well as the power converter. Therefore, the quiescent current generated by the data converter and the primary and secondary input/output channels cannot be individually determined. As shown in Figure 29, all of these static power requirements have been incorporated into the I current. The total I supply current is the sum of the quiescent operating current, the dynamic current I required by the I/O channel, and any external I loads.

Dynamic input and output currents are only consumed when the channel speed is higher than the refresh rate f. Each channel has a dynamic current determined by its data rate. Figure 21 shows the current in the forward channel, which means the input is on the primary side of the part. Figure 22 shows the current in the reverse channel, which means the input is on the secondary side of the part. Both numbers assume a typical 15 pF load. The following relationship allows calculation of the total current:

in:

IDD1 is the total power input current.

ICHn is the current produced by a single channel, as shown in Figure 21 or Figure 22, depending on the channel orientation.

IISO is the current of the external load on the secondary side.

E is the power supply efficiency at 100 mA load in Figure 11 at the interest conditions of VISO and VDD1.

The maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load.

in:

IISO (load) is a current side load that provides external secondary power.

IISO(MAX) is the maximum external secondary side load current for VISO.

IISO(D)n is the dynamic load current or output channel obtained from VISO through the input, as shown in Figure 23 and Figure 24.

The previous analysis assumed a 15 pF data output per capacitive load. If the capacitive load is greater than 15 pF, the current must be included in the analysis of IDD1 and IISO (load).

Power Factor

The inputs on the primary side of the ADuM5401/ADuM5402/ADuM5403/ADuM5404 power supply, the data input channel, and the data channel on the secondary side are protected from premature operation by undervoltage lockout (UVLO) circuitry. Below the minimum operating voltage, the power converter keeps its oscillator inactive and all input channel drivers and refresh circuits are idle. The outputs are held in a high impedance state to prevent undefined states from being transmitted during power-up and power-down operations.

During powering to V, the primary circuit remains idle until the UVLO preset voltage is reached. At this point, the data channels are initialized to the default low output state until they receive a data pulse from the secondary side.

When the primary side is above the UVLO threshold, the data input channel samples its input and starts sending encoded pulses to the inactive secondary output channel. Since there is no data from the secondary side input until the secondary side power is established, the output on the primary side remains in the default low state. The primary side oscillator also starts to work, transferring power to the secondary power supply circuit.

At this point, the secondary V voltage is below its UVLO limit; the regulation control signal on the secondary side is not generated. The primary side power oscillator is allowed to run freely under these conditions, delivering maximum power to the secondary side.

When the secondary voltage rises to its regulation set point, a large inrush current transient occurs at V. When the regulation point is reached, the regulation control circuit generates a regulation control signal which regulates the oscillator on the primary side. The V current then decreases and is proportional to the load current. The inrush current is less than the short circuit current shown in Figure 14. The duration of the inrush current depends on the V load conditions and the current and voltage available on the V pin.

When the secondary side converter begins to receive power from the primary side, the V voltage begins to rise. When the secondary side UVLO is reached, the secondary side output is initialized to its default low state until received from the corresponding primary side input. until the data. After the secondary side is initialized, it may take 1 μs for the state of the output to correlate with the primary side input.

The secondary side input samples its state and transmits it to the primary side. The output is active about 1 μs after the secondary side is activated.

Since the charge rate of the secondary-side supply depends on the load conditions, the input voltage, and the selected output voltage level, care should be taken that the design allows sufficient time for the converter to stabilize before valid data is required.

When the power supply is disconnected from V, the primary side converter and coupler are turned off when the UVLO level is reached. The secondary side stops receiving electricity and begins to discharge.

The output on the secondary side holds the last state received from the primary side. Either the UVLO level is reached and the output is placed in its high impedance state, or the output detects a lack of activity from the primary side input and sets the output to its default low value before the secondary supply reaches UVLO.

Increase available power

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 are designed to operate with other compatible isopower devices. The RC pin allows the ADuM5401/ADuM5402/ADuM5403/ADuM5404 to provide outgoing another device as a master to condition its own and slave PWM signals. The power output is combined in parallel, and the output power is evenly distributed.

The ADuM5401/ADuM5402/ADuM5403/ADuM5404 can only be a master/standalone device, and the ADuM5200 can only be a slave/standalone device. The ADuM5000 can operate as a master or a slave. This means that the ADuM5000, ADuM520x, and ADuM540x can only be used in the master/slave combinations listed in Table 26.

The allowed combinations of master and slave configuration components listed in Table 26 are sufficient to count any combination of power and channel.

Table 27 illustrates how isopower devices can provide various combinations of data channel counts and single-unit power multiples.

Insulation life

Over a sufficiently long period of time, all insulating structures will eventually collapse when subjected to voltage stress. The rate of insulation degradation depends on the characteristics of the voltage waveform applied to the insulation. In addition to testing conducted by regulatory agencies, the simulated device undergoes an extensive series of evaluations to determine the longevity of the insulating structures within the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices.

Simulated equipment is subjected to accelerated life testing using voltage levels above the rated continuous operating voltage. The acceleration coefficients under several operating conditions are determined. These factors allow to calculate the time to failure at the actual operating voltage. The values shown in Table 20 summarize the peak voltage and maximum CSA/VDE approved working voltage for a 50-year lifetime under bipolar AC operating conditions. In many cases, the approved working voltage is higher than the 50-year service life voltage. Working at these high operating voltages can lead to reduced insulation life in some cases.

The insulation lifetime of the ADuM5401/ADuM5402/ADuM5403/ADuM5404 devices depends on the type of voltage waveform applied across the isolation barrier. The insulating structure of an I-coupler degrades at different rates depending on whether the waveform is bipolar AC, unipolar AC, or DC. Figure 30, Figure 31, and Figure 32 illustrate these different isolation voltage waveforms.

Bipolar AC voltage is the most demanding environment. The goal of a 50-year operating life under bipolar AC conditions determines the maximum recommended operating voltage for analog equipment.

In the case of unipolar AC or DC voltages, the stress on the insulation is significantly reduced. This allows operation at higher operating voltages while still achieving a 50-year lifespan. The operating voltages listed in Table 20 may be applied while maintaining a minimum life of 50 years, as long as the voltage conforms to the unipolar AC or DC voltage conditions.

Any cross-insulation voltage waveform not conforming to Figure 31 or Figure 32 shall be treated as a bipolar AC waveform with a peak voltage limited to the 50-year lifetime voltage values listed in Table 20. The voltages shown in Figure 32 are sinusoidal and are for illustration purposes only. It is used to represent any voltage waveform that varies between 0V and some limit. The limit value can be positive or negative, but the voltage cannot exceed 0 V.