Features
100 -µA typical starting supply current
500 -µA Typical Operating Supply Current Operating Frequency 1 MHz Internal Soft-Start Internal Fault Soft-Start Current Sense Signal Internal Leading Edge Blanking
Typical response of 1-A totem pole output current sensed to gate drive output is 70 ns
1.5% Tolerance Reference Voltage Same Pinout as UCC3802 Device, UC3842 Device and UC3842A Device Family Description
The high-speed, low-power integrated circuits of the UCC3813-x device family contain all the control and drive components required for off-line and DC-to-DC fixed-frequency current-mode switching power supplies with a minimum number of parts.
These devices have the same pinout configuration as the UC384x device family, but also provide the additional functionality of an internal full-cycle soft-start and an internal leading edge blanking current sense input.
The higher UV radiation hysteresis of the UCC3813-2 device and UCC3813-4 device makes these devices 2 applications for off-line power supplies.
Switching Power Supplies (SMPS)
The UCC1313-X device family offers a variety of package options, a choice of temperature ranges, a choice of maximum duty cycle, and a choice of threshold voltage levels. Devices with lower reference voltages such as the UCC3813-3 and UCC3813-5 are best suited for battery powered systems, while higher reference voltages and
DC-DC Converter Power Module Industrial PSU
The battery-operated PSU UCC2813-x device family is specified for operation over the -40°C to 85°C temperature range, and the UCC3813-x device family is specified for operation over the 0°C to 70°C temperature range.

Overview
The UCCx813-x family of high-speed, low-power integrated circuits contains all the control and drive functions required for off-line and DC-DC fixed-frequency current-mode switch-mode power supplies with minimal external part count. The UCCx813-x family is a reduced cost version of the UCCx80x family with some parameter restrictions relaxed. See Differences between EUCC3813 and 3800pwmfamilies for details.
These devices have the same pinout configuration as the UCx84x and UCx84xA families, but also offer the additional functionality of an internal full-cycle soft-start and an internal leading edge blanking current sense input. UCCx813-x devices are pin-compatible with the UCx84x and UCx84xA series, but they are not plug-in compatible. Generally, the UCCx813-x requires fewer external components and consumes less operating current.
Functional block diagram

Feature description
The UCCx813-x family offers many advantages that enable power supply design engineers to meet their challenging requirements.
Features include:
Dual CMOS process Low startup supply current: typically 100µA Low operating supply current: typically 500µA Pin compatible with UC3842 and UC3842A series
5-V operation (UCCx813-[3,5])
Current-sense signal leading edge blanking On-chip soft-start for startup and fault recovery Internal full-cycle restart delay
1.5% Reference Voltage Up to 1 MHz Oscillator Low Self-Biased Output Current During UV Exposure 70 ns Response from Sensing to Output Few External Components Required Surface Mount and PDIP Package Detailed Pin Description Compensation
COMP is the output of the error amplifier and the input of the PWM comparator. Unlike earlier devices, the error amplifiers in the UCCx813-x device family are true low output impedance 2-MHz op amps. Therefore, the COMP terminal has both source and sink currents. However, the error amplifier has limited internal current, so the zero duty cycle can be controlled by externally forcing COMP to ground.
The UCCx813-x device family features built-in full-cycle soft-start after power-up and fault recovery, eliminating the need for external components. Soft-start acts as a rising clamp on the COMP voltage, increasing from 0 volts to 5 volts in 4 ms.
carbon steel
CS is the input to the current sense comparator. The UCCx813-x current sensors differ significantly from their predecessors. The UCCx813-x device family has two different current sense comparators: PWM comparators and overcurrent comparators. The overcurrent comparator is used for fault detection only, exceeding the overcurrent threshold will cause a soft-start cycle. Earlier UC3842 series current sense inputs were only connected to PWM comparators.
The UCCx813-x device family includes a digital current-sense filter that disconnects the CS terminal from the current-sense comparator for 100 ns intervals immediately following the rising edge of the output pin. This digital filtering, also known as leading edge blanking, prevents false triggering due to leading edge noise, which means that in most applications analog filtering (external RC filter) is not required for the CS. The leading edge blanking technique provides a smaller effective CS-to-OUT delay compared to external RC filter techniques. However, the minimum non-zero turn-on time of the output signal is determined by the leading edge blanking time and the CS-toOUT propagation delay. In the UCCx813-x family, the gain of the current sense amplifier is typically 1.65 V/V, while in the UC3842 family the gain is typically 3 V/V. Connect CS directly to the MOSFET source current sense resistor.
function block
FB is the inverting input of the error amplifier. For best stability, keep the FB lead length as short as possible and keep the FB stray capacitance as small as possible. At 2MHz, the gain bandwidth of the error amplifier is twice that of earlier UC3842 series devices, and the feedback design techniques are the same.
ground
GND is the signal reference ground and power ground for all functions in this part. TI recommends separating the signal return path and the high current gate driver path so that the signal is not affected by switching currents.
Output The output is the output of a high current power driver capable of driving the gates of power MOSFETs with peak currents in excess of ±750mA (up to ±1A). OUT is low when VCC is below the UVLO threshold. This feature eliminates the need for gate-to-source bleed resistors associated with MOSFET gate drive.
The high-current power driver consists of a CMOS FET output device, which can be switched all the way to GND and all the way to VCC. The output provides very smooth rising and falling waveforms with very low impedance for overshoot and overshoot, which means that in many cases an external Schottky clamp diode may not be required for the output. Finally, the UCCx813-x does not require an external gate voltage clamp because the on-chip Zener diode automatically clamps the output to VCC.
RC
RC is the oscillator timing pin. For fixed frequency operation, set the timing capacitor charge current by connecting a resistor from REF to RC. The frequency is set by connecting a timing capacitor from RC to GND. For best performance, keep the timing capacitor leads as short and direct as possible to ground. If possible, use separate ground traces for timing capacitors and all other functions.

Reference Voltage The traditional 5-V bandgap reference voltage of the UC3842 family can also be found on UCCx813-[0,1,2,4] devices. However, the reference voltage for the UCCx813-[3,5] device is 4v. This change is necessary to facilitate operation with input supply voltages below 5v. Many reference voltage specifications are similar to the UC3842 device, although the test conditions have been changed to indicate low current PWM applications. Similar to bipolar devices, BiCMOS devices internally pull the reference voltage low during UVLO, which can be used as a logic state indication.
The 4-V reference on the UCCx813-[3,5] comes from the supply voltage (VVCC) and requires about 0.5 V of headroom to maintain regulation. The reference also falls outside its normal operating range whenever VVCC falls below about 4.5 V. During this trip, the relationship between VVCC and VREF, the non-vertical input to the error amplifier is associated with half the controller reference voltage (VREF). This input is 2 V on UCCx813-[3,5] and 2.5 V on the higher reference voltage section: UCCx813-[0,1,2,4].
Required Reference Bypass Minimum Capacitor Oscillator
The UCCx813-x oscillator generates a sawtooth wave on RC. The rise time is set by the time constants of RT and CT. The fall time is set by CT and the internal transistor on-resistance is about 130Ω. During the fall time, the output is turned off and the maximum duty cycle is reduced below 50% or 100%, depending on the part number. The larger the timing capacitor value, the longer the discharge time and the smaller the maximum duty cycle and frequency, as shown in Figure 5 and Figure 6.
Oscillator Equivalent Circuit
The oscillator portion of the UCCx813-x BiCMOS family bears little resemblance to the UC3842 type, except for single-pin programming. It still uses a resistor to reference voltage and capacitor to ground to program oscillator frequencies up to 1 MHz. Since the charge current required for low power operation is much lower, the timing component value must be changed. Some features of the oscillator have been optimized for high-speed, noise-immune operation. In the UC3842 series, the oscillator peak-to-peak amplitude has been increased to 2.45 V (typ) instead of 1.7 V. The lower oscillator threshold has dropped to about 0.2 V, while the upper threshold is still fairly close to the original 2.8 V at about 2.65 V.
The discharge current of the timing capacitor increases from about 8 mA to a peak value of nearly 20 mA. This can be represented by approximately 130Ω in series with the discharge switch to ground. Higher currents are necessary to achieve short dead times and high frequency duty cycles. Practical applications can reach switching frequencies of 1 MHz using these devices.
Computed Tomography Synchronization Synchronization of these PWM controllers is best accomplished by the general technique shown in FIG. 19 . The device oscillator was programmed to free-run at a frequency approximately 20% lower than the sync frequency. Apply a brief positive pulse across the 50Ω resistor to force sync. Typically, a 100ns wide pulse of 1v amplitude is sufficient for most applications.
The controller can also be synchronized to a pulse train applied directly to the oscillator RC pin. Once the oscillator upper threshold is exceeded, the device pulls low internally at that node. This 130Ω impedance to ground remains active until the voltage on RC drops below 0.2V. External synchronization circuits must accommodate these conditions.
Synchronous oscillator PWM generators have a higher maximum duty cycle than their UC38 4 [2, 3, 4, 5] predecessors. This is primarily due to the high ratio of timing capacitor discharge to charge current, which can exceed 100:1 in typical BiCMOS applications. Attempts to program the oscillator maximum duty cycle well below the specified range by adjusting the values of the timing components of RT and CT must be avoided. There are two reasons to avoid this design practice. First, the high discharge current of the device will require a higher charge current than required for programming, defeating the purpose of low power operation. Second, the low value timing resistor prevents the capacitor from discharging to the lower threshold and initiating the next switching cycle.
Minimum off time adjustment (dead time control)
Dead time is a term used to describe the guaranteed off time of the PWM output during each oscillator cycle. It is used to ensure that even at maximum duty cycle, there is enough time to reset the magnetic circuit components and prevent saturation. The dead time of the UCCx813-x PWM series is determined by the internal 130Ω discharge impedance and timing capacitor value. Larger capacitor values prolong dead time, while smaller values result in a higher maximum duty cycle for the same operating frequency. A plot of dead time versus timing capacitor value is shown in Figure 20. Dead time can be further increased by adding a low value resistor between the RC pin and the timing element, as shown in Figure 21. As can be seen from the curve in Figure 22, as the discharge resistance value increases, the dead time increases to around 470Ω. Higher resistors must be avoided as they reduce dead time and lower oscillation peak-to-peak amplitude. Reducing the excessive current (1 mA) by lowering RT will prevent discharge to the lower comparator threshold voltage of 0.2 volts, freezing the oscillator. Adding this discharge control resistor has several effects on oscillator programming. First, it introduces a DC offset to the capacitor during the discharge interval, rather than the charge interval of the timing cycle, reducing the available peak-to-peak timing capacitor amplitude. Due to the reduced peak-to-peak amplitude, the exact value of CT may need to be adjusted to obtain the correct oscillator frequency. Another approach is to keep the same timing capacitor value and adjust the timing resistor and discharge resistor values as they are easily available in finer digital increments.

Leading edge blanking In the current sense input circuit of the UCCx813-x device, a leading edge blanking interval of 100 ns is applied. This internal feature eliminates the need for an external resistor-capacitor filter network to suppress switching spikes associated with power MOSFET turn-on. This 100 ns period should be sufficient for most switch-mode designs, but can be extended by adding an external R/C filter. In addition to the PWM function with cycle-by-cycle current limit, the overcurrent fault comparator also uses 100ns leading edge blanking.
The PWM comparator has two inputs: one from the current sense input and the other from the attenuated error amplifier output (COMP), which has a diode and two series resistors to ground. The diodes in this network are used to ensure that zero duty cycle is achieved. When the E/A output is below the diode forward voltage drop, no current flows in the resistive divider and the PWM input goes to zero, resulting in zero pulse width.
Under certain conditions, the leading edge blanking circuit can result in an output pulse of minimum width equal to the blanking interval. This happens when COMP is slightly above the diode forward voltage drop of about 0.5v, so that the decaying COMP input to the PWM comparator allows the output pulse to start. If the decaying COMP level commands a peak current whose pulse width will fall within the leading edge blanking interval, the output will remain on until the blanking interval is complete, and the peak current will be higher than the peak current required by the COMP level. The usual result is that the converter output voltage increases, the error increases, and the drive voltage of COMP is lower than the diode drop, resulting in zero pulse width. When the output voltage rises or falls at this minimum pulse width condition, it can cause cycle skipping.
A 1-V (typ) cycle-by-cycle current limit threshold is included in the UCCx813-x family. The current limiting circuit uses a leading edge blanking interval of 100ns. Blanking overrides the current limit comparator output to prevent leading edge switching noise from triggering the current limit function. The propagation delay from the current limit comparator to the output is typically 70ns. This high-speed path minimizes power semiconductor losses during overload by shortening the time.
To improve the efficiency of the current sense circuit, resistors RA and RB shift the actual current sense resistor voltage upwards, allowing the use of smaller current sense amplitudes. This circuit provides current-limit protection for low-power current sensing.
The example shown uses a 200 mV full-scale signal at the current sense resistor. Resistor RB is biased by approximately 700mV to match the 0.9V minimum specification of the IC's current-limiting comparator. Due to the difference in reference voltage, the value of resistor RA varies with the specific IC used. Resistor values should be chosen for minimum power loss. For example, for the UCCx813-[0,1,2,4] device, the 50µa bias current sets RB=13 kΩ, RA=75 kΩ, and for the UCCx813-[3,5] device RA=56 kΩ.
Overcurrent Protection and Full Cycle Restart
A separate overcurrent comparator within the UCCx813-x device handles operation of shorted or severely overloaded power supply outputs. This overcurrent comparator has a threshold of 1.5 volts and is gated by a leading edge blanking signal to prevent false triggering. Once triggered, the overcurrent comparator uses an internal soft-start capacitor to create a delay before attempting to retry. This delay time, commonly referred to as hiccup, is used to significantly reduce the input and dissipated power of the main converter and switching elements. Full-cycle soft-start ensures a predictable delay greater than 3 ms between successive attempted operations under fault conditions. The circuit shown in Figure 28 and the timing diagram shown in Figure 29 show the response of the integrated circuit to a severe fault such as a saturated inductance. When a peak current fault is first detected, the internal soft-start capacitor discharges immediately and remains discharged until the fault clears. At the same time, the PWM output is turned off and remains off. When the fault clears, the capacitor charges slowly and allows the error amplifier output (COMP) to rise. When COMP reaches enough to enable the output, another fault occurs, locking the PWM output, but the soft-start capacitor still continues to rise to 4v before discharging and allowing a new cycle to begin. This means that, for a severe fault, the consecutive retry interval is the time it takes to fully charge the soft-start capacitor. TI recommends a low leakage transformer design in high frequency applications to activate overcurrent protection. Otherwise, the switch current may not be enough to rise for the leading edge blanking duration to trigger the overcurrent comparator. This condition causes continuous cycling of the circulating current limit comparator instead of the overcurrent comparator. This will cause the main converter to have a short duration of high power dissipation at the switching frequency. The purpose of the overcurrent comparator is to reduce the effective retry rate under these conditions to a few milliseconds, thereby significantly reducing the short-circuit power dissipation of the converter.
Soft-Start Internal soft-start PWM output is achieved by gradually increasing the error amplifier (E/A) output voltage at COMP. When used for current-mode control, this implementation continuously and slowly increases the peak switch current each PWM cycle, forcing a controlled start-up. In voltage mode (duty cycle) control, this function continuously expands the pulse width.
Soft-start is performed within the UCCx813-x device by limiting the E/A amplifier output (COMP) to the voltage on the internal soft-start capacitor (CSS), which is charged by a current source. The CSS is discharged after an undervoltage lockout transition, or if the reference voltage falls below the minimum value for normal operation. Additionally, CSS discharge occurs when the overcurrent protection comparator is triggered by a fault. Once the CSS is charged above the normal PWM operating voltage required by the error amplifier, the soft-start clamp will be overridden.
Slope Compensation Slope compensation can be added to all current mode control applications to eliminate peak-to-average current errors. Slope compensation is necessary in applications with duty cycles greater than 50%, but can also improve performance below 50%. The primary current is sensed through resistor RCS in series with the converter switch. The timing resistor can be split into two series resistors to bias the NPN voltage follower, as shown in Figure 32. This requires sufficient compliance for slope compensation at the beginning of the switching cycle, especially for continuous current converters. The voltage follower drives the slope compensation programming resistor (RSC) to supply the slope compensation current to CF.
Added slope compensation device function mode
The UCCx813-x family of high-speed, low-power current-mode PWM controllers has the following functional modes.
Normal Operation In this mode of operation, the IC controls the power converter into either voltage mode or current mode control, regulating the output voltage or current through the converter duty cycle. Regulation can be achieved with an integrated error amplifier or external feedback circuitry.
Device Functional Modes (continued)
UVLO mode During system startup, the V VCC voltage rises from 0v. The IC operates in UVLO mode until the VCC voltage reaches the corresponding turn-on threshold. In this mode, the reference pin voltage is not generated. When VVCC is above 1V and below the turn-on threshold, the reference pin is actively pulled low through a 5-kΩ resistor. In this way, VREF can be used as a logic signal to indicate UVLO mode.
Soft-Start Mode Once the VCC voltage rises above the UVLO level, or the device exits fault mode, it will enter soft-start mode. During soft-start, the internal soft-start capacitor CSS clamps the error amplifier output voltage, forcing it to rise slowly. This in turn controls the peak current of the power converter to rise slowly, reducing the voltage and current stress on the system. The UCCx813-x family has a fixed built-in soft-start time (4ms).
failure mode
A separate overcurrent comparator within the UCCx813-x device handles operation of shorted or severely overloaded power supply outputs. This overcurrent comparator has a threshold of 1.5 volts and is gated by a leading edge blanking signal to prevent false triggering. When a fault is first detected, the internal soft-start capacitor discharges immediately and remains discharged until the fault clears. At the same time, the PWM output is turned off and remains off. This is often called a hiccup. This delay time is used to significantly reduce the input and dissipated power of the main converter and switching elements. A full-cycle soft-start ensures a predictable delay greater than 3 milliseconds between successive attempted operations during a fault. When the fault clears, the capacitor charges slowly and allows the error amplifier output (COMP) to rise. When COMP gets high enough to enable the output, another fault occurs, locking the PWM output, but the soft-start capacitor still continues to rise to 4v before discharging and allowing a new cycle to begin. This means that, for a severe fault, the consecutive retry interval is the time it takes to fully charge the soft-start capacitor.

Application Information
The UCCx813-x controllers are peak current mode (PCM) pulse width modulators (PWM). These controllers have an on-board amplifier and can be used in isolated and non-isolated power supply designs. There is a totem pole gate driver on board capable of delivering up to ±1 A peak current. These controllers are capable of operating at switching frequencies up to 1 MHz.
Typical Application Typical circuit diagram of an AC-DC converter using the UCC2813-0 in a peak current mode controlled flyback application.

Power Supply Recommendations Internal VCC shunt regulators are incorporated into each member of the UCX813-X family to limit the supply voltage to approximately 13.5 V. A series resistor from VCC to the input supply requires an input exceeding 12 V to limit the shunt regulator current. The maximum 10mA can be shunted to the ground by the internal regulator. The internal regulator combined with the low start-up and operating current of the device can greatly simplify powering the device and can eliminate the need for a regulated bootstrap auxiliary power supply and windings in many applications. The supply voltage is compatible with the MOSFET gate level, eliminating the need for external Zener diodes or regulator protection with current-limited input supplies. The UVLO startup threshold is 1v below the shunt regulator level on the UCCx813-[2,4] device to ensure startup. It is important to bypass the device's power supply (VCC) and reference voltage (REF) pins, each with a 0.1-1-1-µF ceramic capacitor to ground. Capacitors must be placed as close as possible to the actual pin connections for optimal noise filtering. In offline applications, a second, larger filter capacitor may also be required to keep the supply voltage (VVCC) above the UVLO turn-off threshold during startup.
Layout Guidelines for Different Methods of Powering Up Your Device In addition to the following general power management IC layout guidelines (star grounding, minimum current loops, reasonable impedance levels, etc.), the layout of the UCCx813-x family must consider the following:
When possible, ground planes should be used to minimize the noise introduced in a single trace by voltage drops on grounded circuits and parasitic inductances.
A decoupling capacitor is required for each of the VCC and REF pins, and both must return as close to the IC's GND as possible.
For best performance, keep the timing capacitor leads as short as possible and directly to ground. If possible, use separate ground traces for timing capacitors and all other functions.
The CS pin filter capacitor must be as close as possible to the IC and directly grounded at the IC ground pin. This ensures optimal filtering and minimizes the possibility of current sense pin failure.
The gate drive loop area must be minimized to reduce EMI noise due to high di/dt of current in the loop.
layout example