feature

Fast 12-bit ADC with 1.47s conversion time; 600 kSPS throughput ( AD7892-3 ); 500 kSPS throughput (AD7892-1, AD7892-2); single-supply operation; on-chip track/hold amplifier; selection of input ranges: AD7892-1 is 10 V or 5 V; AD7892-2 is 0 V to +2.5 V; AD7892-3 is 2.5 V; high speed serial and parallel interface; low power, 60 mW (typ); analog input overvoltage protection (AD7892-1 and AD7892-3).

General Instructions

The AD7892 is a high-speed, low-power, 12-bit A/D converter that is powered by a +5V supply. This section contains a 1.47µs successive approximation ADC, an on-chip track/hold amplifier, an internal +2.5V reference and an on-chip multifunction interface structure that allows serial and parallel connection to a microprocessor. The part accepts analog input ranges of ±10 V or ±5 V (AD7892-1), 0 V to +2.5 V (AD7892-2), and +2.5 V (AD7892-3). Analog Input Overvoltage Protection For the AD7892-1 and AD7892-3, input voltages of ±17 V or ±7 V, respectively, are allowed to pass through without damaging the ports.

The AD7892 offers a choice of two data output formats: single, parallel, 12-bit word, or serial data. Fast bus access times and standard control inputs ensure easy parallel interface to microprocessors and digital signal processors. A high-speed serial interface allows direct connection to microcontrollers and digital signal processors. In addition to traditional DC accuracy specifications, dynamic performance parameters such as linearity, full-scale and offset error including harmonic distortion and signal-to-noise ratio.

The AD7892 is fabricated using Analog Devices' Linear Compatible CMOS (LC2) MOS process, a hybrid technology process that combines precision bipolar circuits and low-power CMOS logic. Available in 24 lead, 0.3" wide, plastic or hermetic immersion or immersion in 24 lead SOIC.

Product Highlights

1. The AD7892-3 has a conversion time of 1.47 microseconds and a track/hold acquisition time of 200 ns. This allows the part to have a throughput of up to 600 kSPS. The AD7892-1 and AD7892-2 operate at a throughput of 500 kSPS.

2. The AD7892 is powered by a +5V power supply and consumes 60mW, making it ideal for low-power and portable applications.

3. This part provides a high-speed and flexible interface configuration. Features parallel and serial interfaces for easy connection to microprocessors, microcontrollers and digital signal processors.

term signal-to-noise ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (fS/2), except DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio (noise + distortion) of an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB, so for a 12-bit converter this is 74 dB.

total harmonic distortion

Total Harmonic Distortion (THD) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7892, the definitions are as follows:

where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fS/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. Typically, the value of this specification is determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7892 is tested with two input frequencies away from the bottom end of the input bandwidth. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dBs.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line through the endpoints of the ADC transfer function.

Differential nonlinearity

This is the difference between the measured value and the ideal 1 LSB change between any two adjacent codes in the ADC.

Positive Full-Scale Error (AD7892-1)

This is the deviation of the last code transition (01). . . 110-01. . . 111) After adjusting for bipolar zero error, from ideal 4 × REF IN – 3/2 LSB (±10 V range) or 2 × REF IN – 3/2 LSB (±5 V range).

Positive Full-Scale Error (AD7892-2)

This is the deviation of the last code transition (11). . . 110 to 11. . . 111) After adjusting for the unipolar offset error, start with the ideal value (REF IN – 3/2 LSB).

Positive Full-Scale Error (AD7892-3)

This is the deviation of the last code transition (01). . . 110 to 01. . . 111) After adjusting the bipolar zero error, start from the ideal value (REF IN – 3/2 LSB).

Bipolar Zero Error (AD7892-1, AD7892-3)

This is the deviation of the mesoscale transformation (all 1s to all 0s) from the ideal (AGND – 1/2 LSB).

Unipolar Offset Error (AD7892-2)

This is the deviation of the first code transition (00). . . 000 to 00. . . 001) from ideal (AGND+1/2 LSB).

Negative Full-Scale Error (AD7892-1)

This is the deviation of the first code transition (10). . . 000 to 10. . . 001) After adjusting for bipolar zero error, from ideal –4×REF IN+1/2 LSB (±10 V range) or –2×REF IN+1/2 LSB (±5 V range).

Negative Full-Scale Error (AD7892-3)

This is the deviation of the first code transition (10). . . 000 to 10. . . 001) After adjusting for bipolar zero error, from ideal – reference input +1/2 LSB.

Track/Hold Acquisition Time

Track/hold capture time is the time it takes for the output of the track/hold amplifier to reach its final value (within ±1/2 LSB) after the conversion ends (the point at which the track/hold returns to track mode). It also applies when there is a step input change in the input voltage on the VIN input of the AD7892. This means that the user must wait the duration of the track/hold acquisition time after the conversion ends or after the step input is changed to VIN before starting another conversion to ensure the part is operating to specification.

Circuit Description

The AD7892 is a fast 12-bit single-supply A/D converter. It provides users with signal scaling, track/hold, reference, A/D converters and versatile microcontroller interface logic functions. The signal scaling on the AD7892-1 allows the part to handle ±5 V or ±10 V input signals when operating from a single +5 V supply. The AD7892-2 handles an analog input range of 0 V to +2.5 V, while the signal scaling on the AD7892-3 allows it to handle ±2.5 V input signals when operating from a single supply. The part requires a reference voltage of +2.5 V, which can be supplied from the part's own internal voltage reference or from an external voltage reference source.

A conversion is initiated on the AD7892 by pulsing the CONVST input. On the rising edge of CONVST, track/hold goes from track mode to hold mode and starts the conversion sequence. At the end of the conversion (EOC falling edge), track/hold returns to track mode and the acquisition time begins. The part has a conversion time of 1.47 microseconds (AD7892-3) and a track/hold acquisition time of 200 nanoseconds (AD7892-3). This enables the AD7892-3 to operate at throughputs up to 600 kSPS. The AD7892-1 and AD7892-2 have a conversion of 1.6 microseconds and a capture time of 400 nanoseconds, allowing a throughput of 500 kSPS.

track/hold segment

The track/hold amplifier on the AD7892 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. Even when the ADC is operating at a maximum throughput rate of 600 kHz (that is, the track/hold can handle input frequencies in excess of 300 kHz), the input bandwidth of the track/hold is greater than the ADC's Nyquist rate.

The track/hold amplifier obtains an input signal with 12-bit precision in less than 200 ns. The operation of tracking/holding is basically transparent to the user. The track/hold amplifier goes from its track mode to its hold mode on the rising edge of CONVST. The track/hold aperture time (ie the delay time between the external CONVST signal and the actual track/hold entering the hold) is typically 15ns. At the end of the conversion, the part returns to its tracking mode. The acquisition time of the track/hold amplifier starts at this point.

Reference chapter

The AD7892 includes a single reference pin, labeled REF OUT/REF IN, which provides access to the part's own +2.5 V reference voltage, and can also be connected to an external +2.5 V reference to provide a reference voltage source for the part. This part is specified as a +2.5 V reference. Errors in the reference source will cause gain errors in the AD7892 transfer function and will add to the full-scale errors specified on the part. On the AD7892-1 and AD7892-3, it will also cause offset errors to be injected into the attenuator stage.

The AD7892 includes an on-chip +2.5V reference. To use this reference as a reference source for the AD7892, simply connect a 0.1µF disc ceramic capacitor from the REF OUT/REF IN pins to AGND. The voltage appearing on this pin is buffered internally before being applied to the ADC. If the reference needs to be used external to the AD7892, it should be buffered because the part has a FET switch in series with the reference output, resulting in a nominal 5.5 kΩ source impedance for this output. At 25°C, the internal reference tolerance is ±10 mV, the typical temperature coefficient is 25 ppm/°C, and the maximum error is ±25 mV.

If the application requires a reference with tighter tolerances or if the AD7892 needs to be used with a system reference, the user has the option to connect an external reference to this REFOUT/REFIN pin. The external reference will effectively drive the internal reference, providing a reference source for the ADC. The reference input is buffered before being applied to the ADC, with a maximum input current of ±100µA. Suitable reference sources for the AD7892 include the AD680, AD780, and the ReF43 precision +2.5 V reference.

interface

This part offers two interface options, a 12-bit parallel interface and a three-wire serial interface. The desired interface mode is selected via the mode pin. These two interface modes will be discussed in the following sections.

Parallel interface mode

The parallel interface mode is selected by tying the mode input to a logic high level. Figure 2 shows a timing diagram illustrating the sequence of operation of the AD7892. The on-chip track/hold enters hold mode, and conversions are initiated on the rising edge of the CONVST signal. When the conversion is complete, the end of the conversion line (EOC) is pulsed low to indicate that new data is available in the AD7892's output register. This EOC line can be used to drive edge-triggered interrupts to the microprocessor. The falling edge of the RD signal should occur 200 ns before the next rising edge of CONVST. CS and RD go low to access the 12-bit conversion result. In systems where this part interfaces with a gate array or ASIC, this EOC pulse can be applied to the CS and RD inputs to latch data from the AD7892 into the gate array or ASIC. This eliminates the logic required in the gate array or ASIC to recognize the end of conversion and generate the read signal for the AD7892. To get the best performance from the AD7892, it is not recommended to permanently lower CS and RD as this will keep the tri-state active during conversions.

serial interface mode

The AD7892 configures the serial mode interface by setting the mode input low. It provides a three-wire serial link between the AD7892 and industry standard microprocessors, microcontrollers, and digital signal processors. SCLK and RFS of the AD7892 are inputs, the serial interface of the AD7892 is designed to interface directly to systems that provide a serial clock input that is synchronized with the serial data output, including microcontrollers such as the 80C51, 87C51, 68HC11, and 68HC05 and most digital signal processors.

Figure 3 shows the timing diagram for reading data from the AD7892 in serial interface mode. RFS is low enough to access data from the AD7892. The serial clock input does not have to be continuous. Serial data can be accessed in bytes. However, during data transfer operations, RFS must be kept low. Transfer 16-bit data, 4 leading zeros followed by 12-bit conversion result starting from MSB. Serial data is clocked from the device on the rising edge of SCLK. Old data is guaranteed to be valid within 5 ns after this edge. This is useful for high-speed serial clocks, where the access time of the part does not allow sufficient data setup time to be accepted on the falling edge of the clock. In this case, care must be taken that RFS does not precede the rising edge of SCLK. For slower serial clocks, data is valid on the falling edge of SCLK. At the end of a read operation, the SDATA line is represented as three by a rising edge on the SCLK or RFS input, whichever occurs first. Serial data cannot be read during the conversion process to avoid feedthrough issues from the serial clock to the conversion process. For optimum performance of the AD7892-3, serial reads within 200 ns of the rising edge of CONVST should also be avoided to avoid track/hold during acquisition. Therefore, the serial read should occur between the end of the conversion (falling edge of EOC) and 200 ns before the next rising edge of CONVST. For the AD7892-1 and AD7892-2, serial reads within 400 ns of the rising edge of CONVST should also be avoided. This limits the maximum achievable throughput rate in serial mode (assuming a 20 MHz serial clock) to 400 kSPS for the AD7892-3 and 357 kSPS for the AD7892-3 and AD7892-2.

Analog input section

The AD7892 is divided into three parts, allowing four different analog input voltage ranges. The AD7892-1 can handle a ±5 V or ±10 V input voltage range. The AD7892-2 handles an input voltage range of 0 V to +2.5 V, while the AD7892-3 handles an input range of ±2.5 V.

AD7892-1

Figure 4 shows the analog input section of the AD7892-1. At the VIN1 input, the analog input range is ±5 V or ±10 V (using VIN2). When VIN2 is connected to AGND, the input range on VIN1 is ±10 V and the input resistance on VIN1 is 15 kΩ (nominal). When VIN2 is connected to VIN1, the input range on VIN1 is ±5 V, and the input resistance on VIN1 is 8 kΩ nominal. Therefore, the VIN1 and VIN2 inputs should be driven by low impedance sources. The resistive attenuator stage is followed by the high input impedance stage of the track/hold amplifier.

This resistor attenuator stage allows input voltages to reach ±17 V without damaging the AD7892-1.

The designed transcoding occurs in the middle between consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB). The output encoding is 2's complement binary, 1 LSB=FSR/4096=20v/4096=4.88mv (within ±10v range), 1 LSB=FSR/4096=10v/4096=2.44mv (within ±5v range) . The ideal input/output transfer function of the AD7892-1 is shown in Table 1.

AD7892-2

The analog input section of the AD7892-2 does not contain bias resistors. The analog input goes directly to the track/hold input stage. The analog input range on the VIN1 input is 0 V to +2.5 V. The VIN2 input can be left unconnected, but if it is connected to a potential, that potential must be AGND. The VIN1 input is connected directly to the AD7892-2 track/hold input sampling capacitor. The value of this input sampling capacitor is nominally 10 pF.

Again, the designed transcoding occurs in the middle between consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB). The output code is straight (natural) binary, 1 LSB=FSR/4096=2.5 V/4096=0.61 mV. The ideal input/output transfer function of the AD7892-2 is shown in Table II.

AD7892-3

Figure 5 shows the analog input section of the AD7892-3. On the VIN1 input, the analog input range is ±2.5 V. The VIN2 input can be left unconnected, but if it is connected to a potential, that potential must be AGND. The input resistance on VIN1 is 1.8 kΩ nominal. Therefore, the VIN1 input should be driven by a low impedance source. The resistive attenuator stage is followed by the high input impedance stage of the track/hold amplifier. This resistor attenuator stage allows input voltages to reach ±7 V without damaging the AD7892-3.

The designed transcoding occurs in the middle between consecutive integer LSB values (ie 1/2 LSB, 3/2 LSB, 5/2 LSB). The output encoding is 2's complement binary, 1 LSB=FSR/4096=5v/4096=1.22mv, REF IN=+2.5v. The ideal input/output transfer function of the AD7892-3 is shown in Table 3.

Microprocessor interface

High-speed parallel and serial interfaces allow considerable flexibility in the interface of microprocessor systems. For best performance from the part, data should not be read during conversions, which limits the achievable throughput of the AD7892-3 in serial mode to 400 kSPS.

Figures 6, 7, and 9 show some typical interface circuits between the AD7892 and popular DSP processors. Figure 8 shows the interface between this part and the gate array or ASIC, where the data is clocked into the ASIC by the AD7892 itself at the end of the conversion. In all cases, the CONVST signal is generated by an external timer to ensure equidistant sampling.

AD7892 to ADSP-2101 interface

Figure 6 shows the parallel interface between the AD7892 and the ADSP-2101 DSP processor. CONVST starts the conversion, and when the conversion ends, the falling edge of the EOC output provides an interrupt request to the ADSP-2101.

AD7892 to TMS320C25 interface

Figure 7 shows the parallel interface between the AD7892 and the TMS320C25 DSP processor. CONVST starts the conversion, and when the conversion ends, the falling edge of the EOC output provides an interrupt request to the TMS320C25.

EOC pulse provides CS and RD

Figure 8 shows the parallel interface between the AD7892 and a gate array or ASIC. CONVST starts a conversion, and at the end of the conversion, the falling edge of the EOC output provides CS and RD pulses to latch data from the AD7892 into the gate array/ASIC. This scheme allows the fastest possible throughput because the interrupt service routine does not lose time and the data is transferred out as soon as it is available from the part.

AD7892 to DSP56000 interface

Figure 9 shows the serial interface between the AD7892 and the DSP56000 DSP processor. CONVST starts to convert, when the conversion ends, the falling edge of EOC output provides interrupt request to DSP56000.

Grounding and Arrangement

The AD7892 has a single supply voltage pin, VDD, which provides part of the analog and digital circuitry. For optimum performance of the part, it is recommended to remove the +5 V from the +5 V analog supply in the system. The analog and digital grounds of the AD7892 are independent and secured separately to minimize coupling between the analog and digital portions of the device. The part has good immunity to noise on the power supply, but care must still be taken with grounding and layout, especially when using switching power supplies.

The design of the printed circuit board containing the AD7892 should keep the analog and digital sections separate and confined to certain areas of the board. This facilitates the use of easily separated ground planes. The minimum etch technique is usually best for the ground plane because it provides the best shielding. Digital and analog ground can only be connected in one place. If the AD7892 is the only device that requires an AGND to DGND connection, the ground plane should be connected at the AGND and DGND pins of the AD7892. If the AD7892 is in a system where multiple devices require an AGND to DGND connection, it should still only be connected at one point, which should be as close to the AD7892 as possible to establish a star ground point.

Avoid running digital lines under the device as this will couple noise onto the die. The analog ground plane should allow operation under the AD7892 to avoid noise coupling. The power supply lines to the AD7892 should use as large traces as possible to provide a low impedance path and reduce the effect of faults on the power supply lines. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to the rest of the board, and clock signals must not run near the analog inputs. Avoid crossover of digital and analog signals. The traces on opposite sides of the board should be at right angles to each other. This will reduce feedthrough effects through the board. Microstrip technology is by far the best, but not always possible on double-sided panels. In this technique, the component side of the board is dedicated to the ground plane, while the signals are placed on the solder side.

Good decoupling is very important when using high resolution ADCs. All analog supplies should be separated from 10µF tantalum and in parallel with 0.1µF capacitors to AGND. To get the best results from these decoupling components, they must be placed as close to the device as possible, ideally facing the device. All logic chips should be separated to DGND with 0.1µF disc ceramic capacitors. It is recommended to use the system's AVDD power supply to provide VDD to the AD7892. This power supply should have the recommended analog supply decoupling capacitor between the AD7892 and the VDD pin of AGND and the recommended digital supply decoupling capacitor between the AD7892 and the VDD pin of DGND.

Evaluating AD7892 Performance

The recommended layout for the AD7892 is outlined in the evaluation board for the AD7892. The evaluation board package includes a fully assembled and tested evaluation board, documentation and software for controlling the evaluation board from a PC

Use an evaporation control board. The evaluation control board can be used with the AD7892 evaluation board and many other analog device evaluation boards ending with the CB designator. Using the evaluation control board with the AD7892 evaluation board, the user can evaluate the ac and dc performance of the AD7892 on a PC.

The software provided with the evaluation board allows the user to perform ac (fast Fourier transform) and dc (code histogram) tests on the AD7892. The evaluation board can also be used standalone without the need for an evaluation control board, but in this case the user must write their own software to evaluate the part. There are two versions of the evaluation board, one for the AD7892-2 and one for the AD7892-3. To order the AD7892-2 evaluation board, order number EVAL-AD7892-2CB; to order the AD7892-3 evaluation board, order number EVAL-AD7892-3CB.