feature

Fast 14-bit ADCms conversion time with 5; 8-lead SOIC package; single 5 V supply operation; high-speed, easy-to-use, serial interface; on-chip track/hold amplifier; choice of input range; 3 is 62.5 volts; 0 V to +2.5 V for AD7894-2; high input impedance; low power: 20 mW (typ); Pin compatible upgrade for 12-bit AD7895.

General Instructions

The AD7894 is a fast 14-bit ADC powered from a +5V supply and packaged in a small 8-lead SOIC. This part contains a 5-bit successive approximation A/D converter, a track/hold amplifier, an on-chip clock and a high-speed serial interface.

The output data of the AD7894 is provided through the high-speed serial interface port. This two-wire serial interface has a serial clock input and a serial data output, and the external serial clock accesses the serial data of the part.

In addition to traditional DC accuracy specifications such as linearity, full scale, and offset error, the AD7894 specifies dynamic performance parameters including harmonic distortion and signal-to-noise ratio.

The part accepts analog input ranges of ±10 V (AD7894-10), ±2.5 V (AD7894-3), 0 V to +2.5 V (AD7894-2), and consumes only 20 mW typical from a single +5 V Power is running.

The AD7894 features a high sample rate mode and, for low power applications, a proprietary auto-power-down mode, where after a conversion is complete, the part automatically enters a power-down state and "wakes up" before the next conversion cycle.

A small outline integrated circuit (SOIC) is available for this part.

Product Highlights

1. Fast 14-bit ADC in 8-wire package

The AD7894 contains a 5␣μs ADC, a track/hold amplifier, control logic, and a high-speed serial interface, all in an 8-wire package. This saves a lot of space over other solutions.

2. Low power, single power supply operation

The AD7894 is powered by a +5 V supply and consumes only 20 megawatts. An automatic power-down mode, where the part goes into a power-down state after a conversion is complete and "wakes up" before the next conversion cycle, makes the AD7894 ideal for battery-powered or portable applications.

3. High-speed serial interface

This section provides high-speed serial data and serial clock lines, allowing a simple two-wire serial interface arrangement.

the term

signal to noise ratio

This is the signal-to-noise ratio (noise + distortion) measured at the output of the A/D converter. The signal is the rms amplitude of the fundamental wave. Noise is the rms sum of all non-fundamental signals up to half the sampling frequency (fS/2), except DC. The ratio depends on the number of quantization levels in the digitization process; the more levels, the less quantization noise. The theoretical signal-to-noise ratio (noise + distortion) of an ideal N-bit converter with a sine wave input is: Signal to (Noise + Distortion) = (6.02␣ N + 1.76) dB, so for a 14-bit converter this is 86.04 dB .

total harmonic distortion

Total Harmonic Distortion (THD) is the ratio of the root mean square sum of harmonics to the fundamental. For the AD7894, the definitions are as follows:

where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second to sixth harmonics.

Peak harmonics or spurious noise

Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component (up to fS/2, excluding dc) in the ADC output spectrum to the rms value of the fundamental. The value of this specification is usually determined by the largest harmonic in the spectrum, but for the part of the harmonic buried in the noise floor, it will be the noise peak.

Intermodulation Distortion

When the input consists of two sine waves of frequencies fa and fb, any active device with nonlinearity will produce distortion products at the sum and difference frequencies of mfa±nfb, where m, n = 0, 1, 2, 3 Wait. An intermodulation term is a term for which neither m nor n is equal to zero. For example, second-order terms include (fa+fb) and (fa-fb), and third-order terms include (2fa+fb), (2fa-fb), (fa+2fb), and (fa-2fb).

The AD7894 is tested with two input frequencies. In this case, the meanings of the second- and third-order terms are different. The second-order term is usually farther away in frequency from the original sine wave, while the third-order term is usually at a frequency close to the input frequency. Therefore, the second-order and third-order terms are specified separately. Intermodulation distortion is calculated according to the THD specification, where it is the ratio of the rms sum of a single distortion product to the rms amplitude of the fundamental in dBs.

Relative accuracy

Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line through the endpoints of the ADC transfer function.

Differential nonlinearity

This is the difference between the measurement between any two adjacent codes in the ADC and the ideal 1␣LSB change.

Positive Gain Error (AD7894-10)

This is the deviation of the last code transition (01). . . 110 to 01. . . 111) After the bipolar zero error is adjusted, start from the ideal value (4 × VREF – 1 LSB).

Positive Gain Error (AD7894-3)

This is the deviation of the last code transition (01). . . 110 to 01. . . 111) After adjusting the bipolar zero error, start from the ideal value (VREF – 1 LSB).

Positive Gain Error (AD7894-2)

This is the deviation of the last code transition (11). . . 110 to 11. . . 111) After adjusting for the unipolar offset error, start with the ideal value (VREF – 1 LSB).

Bipolar Zero Error (AD7894-10, AD7894-3)

This is the deviation of the midscale transition (from 0 to 1) from the ideal 0 V (GND).

Unipolar Offset Error (AD7894-2)

This is the deviation of the first code transition (00). . . 000 to 00. . . 001) from the ideal 1 LSB.

Negative Gain Error (AD7894-10)

This is the deviation of the first code transition (10). . . 000 to 10. . . 001) After adjusting the bipolar zero error, start from the ideal value (–4×VREF+1 LSB).

Negative Gain Error (AD7894-3)

This is the deviation of the first code transition (10). . . 000 to 10. . . 001) After adjusting the bipolar zero error, start from the ideal value (–VREF+1 LSB).

Track/Hold Acquisition Time

The track/hold acquisition time is the time it takes for the track/hold amplifier output to reach its final value, ±1/2␣LSB after the end of the conversion (the point at which the track/hold returns to track mode). It also applies when there is a step input change in the input voltage on the VIN input of the AD7894. This means that the user must wait for the duration of the track/hold acquisition time after the conversion ends or after the step input is changed to VIN before starting another conversion to ensure the part is operating to specification.

Converter Details

The AD7894 is a fast 14-bit single-supply A/D converter. It provides users with signal scaling, track/hold, A/D converter and serial interface logic functions on a microcontroller. The A/D converter part of the AD7894 consists of a traditional successive approximation converter based on an R2R ladder structure. The signal scaling on the AD7894-10 and AD7894-3 allows the part to handle ±10 V and ±2.5 V input signals, respectively, when operating from a single +5␣V supply. The AD7894-2 accepts an analog input range of 0 V to +2.5 V. This part requires an external +2.5 V reference. The reference input to the part is buffered on-chip. The AD7894 has two operating modes, a high sampling mode and an "auto-sleep" mode, where the part automatically goes to sleep after a conversion is complete. These modes are discussed in detail in the Timing and Control section.

A major advantage of the AD7894 is that it provides all of the above features in an 8-lead SOIC package. This offers the user a considerable space saving advantage compared to other solutions. The AD7894 typically consumes only 20␣MW, making it ideal for battery-powered applications.

A conversion is initiated on the AD7894 by pulsing the CONVST input. On the falling edge of CONVST, the on-chip track/hold switches from track to hold mode, starting the conversion sequence. The conversion clock for this part is generated internally using a laser trimmed clock oscillator circuit. In high sampling mode, the AD7894 has a conversion time of 5␣µs (10µs in auto-sleep mode) and a track/hold acquisition time of 0.35␣µs. For best performance from the part, read operations should not be performed during a conversion or during the 250 ns before the next conversion. This allows the part to operate at throughputs up to 160 kHz and meet data sheet specifications.

Circuit Description

Analog input section

The AD7894 is divided into three types: AD7894-10 (handling a ±10 V input voltage range), AD7894-3 (handling a ±2.5 V input voltage range), and AD7894-2 (handling a 0␣V to +2.5␣V input voltage range) .

Figure 2 shows the analog input section of the AD7894-10 and AD7894-3. The analog input range of the AD7894-10 is ±10 V, and the analog input range of the AD7894-3 is ±2.5 V. This input is benign with no dynamic charging current as a resistive stage followed by the high input impedance stage of the track/hold amplifier. For the AD7894-10, R1=8 kΩ, R2=2 kΩ, and R3=2 kΩ. For the AD7894-3, R1=R2=2 kΩ and R3 is open. The current in the analog input is directly related to the analog input voltage. The maximum input current flows when the analog input is at negative full scale.

For the AD7894-10 and AD7894-3, the designed code transitions occur on consecutive integer LSB values (ie, 1 LSB, 2 LSB, 3 LSB). . .). The output encoding is two complementary binary, LSB=FS/16384. The ideal input/output transfer functions for the AD7894-10 and AD7894-3 are shown in Table 1.

notes

1. FSR full-scale range = 20 V (AD7894-10) and = 5 V (AD7894-3), and the reference voltage is +2.5 V.

2. LSB=FSR/16384=1.22 mV (AD7894-10) and 0.3 mV (AD7894-3), and the reference voltage is +2.5 V.

The analog input section of the AD7894-2 contains no bias resistors, and the VIN pin drives the input directly to the track/hold amplifier. The analog input range is 0 V to +2.5 V, and the input current is less than a high impedance level of 500␣nA. This input is benign and has no dynamic charging current. Again, the designed transcoding occurs on consecutive integer LSB values. The output encoding is straight (natural) binary, 1lsb=FS/16384=2.5v/16384=0.15mv. Table II shows the ideal input/output transfer function for the AD7894-2.

notes

1. FSR is the full-scale range, 2.5 V for the AD7894-2 with VREF=+2.5 V.

2. LSB=FSR/16384, AD7894-2 is 0.15 mV, VREF=+2.5 V.

track/hold segment

The track/hold amplifier on the analog input of the AD7894 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 14-bit accuracy. The input bandwidth of track/hold is greater than the Nyquist rate of the ADC, even when the ADC operates at its maximum throughput rate of 160 kHz (ie, track/hold can handle input frequencies in excess of 100 kHz).

The track/hold amplifier obtains an input signal with 14-bit precision in less than 0.35␣ microseconds. The operation of tracking/holding is basically transparent to the user. In high-sampling mode of operation, the track/hold amplifier transitions from track mode to hold mode at the start of a conversion (ie, the falling edge of CONVST). The aperture time for track/hold (i.e. the delay time between the external CONVST signal and the actual track/hold entering the hold) is typically 15␣ns. At the end of the conversion (on the falling edge of busy), the part returns to its tracking mode. The acquisition time of the track/hold amplifier starts at this point. For auto-shutdown mode, the rising edge of CONVST wakes up the part, and after the rising edge of CONVST, the track-and-hold amplifier transitions from its track mode to its hold mode for 5 microseconds (provided that CONVST is high for less than 5 microseconds). Again, when the busy signal goes low, the part returns to its tracking mode at the end of the transition.

reference input

The reference input to the AD7894 is buffered on-chip with a maximum reference input current of 1µA. This section is specified with a +2.5 V reference input voltage. Errors in the reference source will cause gain errors in the AD7894 transfer function and will add to the full-scale errors specified on the part. Suitable reference sources for the AD7894 include the AD780 and AD680 precision +2.5V references.

Timing and Control Section

Figure 3 shows the timing and control sequence required to obtain optimum performance from the AD7894. In the sequence shown, a conversion is initiated on the falling edge of CONVST, and new data from that conversion is then available in the AD7894's output register for 5␣μs. Once a read operation has taken place, a further 250␣ns should be allowed before the next falling edge of CONVST to optimize the track/hold amplifier settings before the next conversion begins. When the serial clock frequency is up to 16 MHz, the achievable throughput for this part is 5 μs (conversion time) plus 1 μs (read time) plus 250 μns (quiet time). This results in a minimum throughput time of 6.25␣ microseconds (equivalent to a throughput rate of 160 kHz). Serial clocks smaller than 16MHz can be used, but this will in turn mean that the throughput time will increase.

The read operation consists of 16 serial clock pulses to the output shift register of the AD7894. After 16 serial clock pulses, the shift register is reset and the SDATA line is asserted three times. If there are more serial clock pulses after the 16th clock, the shift register will move after its reset state. However, the shift register will reset again on the falling edge of the CONVST signal to ensure that the part returns to a known state on each conversion cycle. Therefore, a read operation of the output register should not cross the falling edge of CONVST, because the output shift register will be reset in the middle of the read operation, and the data read back to the microprocessor will appear invalid.

Operating mode

Mode 1 Operation (High Sampling Performance) The timing diagram in Figure 3 is for optimum performance in operating Mode 1, when the falling edge of CONVST initiates the conversion and places the track/hold amplifier in its hold mode. This falling edge of CONVST also causes the busy signal to go high to indicate that a conversion is in progress. When a conversion is complete, the busy signal goes low for a maximum of 5 microseconds after the falling edge of CONVST, and new data from the conversion is available in the AD7894's output registers. Read operations access this data. This read operation consists of 16 clock cycles, the length of this read operation will depend on the serial clock frequency. For the fastest throughput rate (serial clock of 16 MHz), a read operation will take 1.0 microseconds. The read operation must complete at least 250 ns before the next falling edge of CONVST, which gives a total time of 6.25 microseconds for the entire throughput time (equivalent to 160 kHz). This mode of operation should be used for high sampling applications.

Mode 2 operation (automatic sleep after transition)

The timing diagram in Figure 4 is for optimal performance in operating mode 2, where after busy goes low, the part automatically enters sleep mode and "wakes up" before the next conversion occurs. This is accomplished by holding CONVST low at the end of the conversion and high at the end of the conversion for Mode 1 operation. The rising edge of Const "wakes up" the AD7894. This wake-up time is typically 5 microseconds and is controlled internally by the monostable circuit. When the AD7894 wakes up, there is some digital activity inside the part. If a falling edge of CONVST occurs during this digital activity (putting the track/hold amplifier in hold mode), it will inject noise into the track/hold amplifier, resulting in poor conversion. For best results, the width of the CONVST pulse should be between 40 ns and 2 μs or greater than 6 μs. Narrower pulses will allow the system to instruct the AD7894 to start waking up and perform conversions when ready, while pulses greater than 6 microseconds will provide control when the sampling instant occurs. Note that the 10-µs wake-up time shown in Figure 4 applies to CONVST pulses less than 2 µs. If a CONVST pulse greater than 6 microseconds is used, the conversion will not complete within 5 microseconds after the falling edge of CONVST. Even if the part is in sleep mode, data can still be read from it. As with Mode 1 operation, a read operation consists of 16 clock cycles. For the fastest serial clock of 16 MHz, a read operation will take 1.0 microseconds and must complete at least 250 ns before the next CONVST falling edge to allow sufficient time for the track/hold amplifier to stabilize. This mode is useful when the part is transitioning at low speed, as the power consumption will be significantly reduced from that of Mode 1 operation.

serial interface

The serial interface of the AD7894 consists of only three wires, a serial clock input (SCLK) and a serial data output (SDATA), and a conversion status output (busy). This enables an easy-to-use interface to most microcontrollers, DSPs and shift registers.

Figure 5 shows the timing diagram for the AD7894 read operation. The serial clock input (SCLK) provides the clock source for the serial interface. Serial data is clocked from the SDATA line on the falling edge of this clock and is valid on both the rising and falling edges of SCLK. The advantage of having data validity on the rising and falling edges of SCLK is that it gives the user more flexibility in connecting to the component, thus accommodating a wider range of microprocessor and microcontroller interfaces. This also explains the two timing numbers t4 and t5 referenced in the figure. Time t4 specifies how long after the falling edge of SCLK the next data bit becomes valid, while time t5 specifies how long after the falling edge of SCLK the current data bit is valid. The first leading zero is clocked on the first rising edge of SCLK. Note that the first zero is still valid on the first falling edge of SCLK, even though the data access time for the other bits is specified as 60 ns. The reason is that the first bit is clocked out faster than the other bits due to the internal structure of the part. 16 clock pulses must be given to the part to get the full conversion result. The AD7894 provides two leading zeros followed by a 14-bit conversion result starting with the MSB (DB13). The last data bit to be clocked on the penultimate falling clock edge is the LSB (DB0). On the 16th falling edge of SCLK, the LSB (DB0) will be asserted for the specified time to allow a bit to be read on the falling edge of SCLK and then disable the SDATA line (three states). After the last bit has been clocked, the SCLK input should return low and remain low until the next serial data read operation. If there is an additional clock pulse after the 16th clock, the AD7894 will restart and output data from its output registers and the data bus is no longer 3 states even if the clocks are stopped. If the serial clock stops before the next falling edge of CONVST, the AD7894 will continue to operate normally

The output shift register is reset on the falling edge of CONVST. However, when CONVST goes low, the SCLK line must be low in order to properly reset the output shift register.

The serial clock input does not have to be continuous during serial read operations. 16-bit data (two leading zeros and a 14-bit conversion result) can be read in bytes from the AD7894.

The AD7894 counts the serial clock edges to know which bit in the output register should be placed on the SDATA output. To ensure the part does not lose synchronization, the serial clock counter will reset on the falling edge of the CONVST input as long as the SCLK line is low. The user should ensure that the SCLK line is held low until the end of the conversion. When the conversion is complete, BUSY goes low, the output register will be loaded with the new conversion result and can be read in 16 SCLK clock cycles.

Microprocessor/Microcontroller Interface

The AD7894 provides a two-wire serial interface that can be used to connect to the serial ports of DSP processors and microcontrollers. Figures 6 through 9 show the AD7894 interfacing with many different microcontrollers and digital signal processors. The AD7894 accepts an external serial clock, so in all the interfaces shown here, the processor/controller is configured as the master, providing the serial clock, and the AD7894 is the slave in the system. If the read can be timed to 5 microseconds after the conversion starts (assuming Mode 1 operation), the busy signal is not required for the two-wire interface.

AD7894 to 8X51/L51 interface

Figure 6 shows the AD7894 and 8X51/L51 microcontrollers. The 8X51/L51 is configured in its Mode 0 serial interface mode. The diagram shows the simplest form of the interface, where the AD7894 is the only part connected to the 8X51/L51 serial port, so serial read operations do not need to be decoded.

To select the AD7894 in a system where multiple devices are connected to the 8X51/L51 serial port, a port bit configured as an output on one of the 8X51/L51 parallel ports can be used to turn the AD7894's serial clock on or off. A simple sum function on this port bit and the serial clock from the 8X51/L51 will provide this functionality. The port bit should be high to select the AD7894, and low if not selected.

The end of the conversion can be monitored using the BUSY signal, as shown in the interface diagram of Figure 6. The busy line P1.2 connected to the port from the AD7894 is in the 8X51/L51 and can be polled for busy by the 8X51/L51. If an interrupt-driven system is preferred, the busy line can be connected to the INT1 line of the 8X51/L51. Both options are shown in the figure.

Also note that during a read operation, the AD7894 outputs the MSB first, while the 8X51/L51 outputs the LSB first. Therefore, the data read into the serial buffer needs to be rearranged before the correct data format for the AD7894 appears in the accumulator.

The serial clock frequency from the 8X51/L51 is limited to significantly lower than the allowable input serial clock frequency at which the AD7894 can operate. Therefore, the time to read data from the component is actually longer than the transition time of the component. This means that the AD7894 cannot operate at its maximum throughput when used with the 8x51/L51.

AD7894 to 68HC11/L11 interface

The interface circuit between the AD7894 and the 68HC11/L11 microcontroller is shown in Figure 7. For the interface shown, the 68L11 SPI port is used and the 68L11 is configured in its microcontroller mode. The 68L11 is configured in master mode with its CPOL bit set to logic zero and its CPHA bit set to logic one. As with the previous interface, this diagram shows the simplest form of the interface, where the AD7894 is the only part connected to the serial port of the 68L11, so serial read operations do not need to be decoded.

Again, to select the AD7894 in a system where multiple devices are connected to the 68HC11's serial port, the port bit configured as the output of one of the 68HC11's parallel ports can be used to switch the AD7894's serial clock on or off. A simple sum function on this port bit and the 68L11's serial clock will provide this functionality. The port bit should be high to select the AD7894, and low if not selected.

The BUSY signal is used for monitoring at the end of the conversion, as shown in the interface diagram of Figure 7. When the busy line of the AD7894 is connected to the PC2 port of the 68HC11/L11, the 68HC11/L11 can poll the busy line.

If an interrupt-driven system is preferred, the busy line can be connected to the IRQ line of the 68HC11/L11. These two options are shown in the figure.

The serial clock rate of the 68HC11/L11 is limited to significantly less than the allowable input serial clock frequency at which the AD7894 can operate. Therefore, the time to read data from the part will be longer than the conversion time of the part. This means that the child process cannot run at the maximum throughput rate when running with the usage time.

AD7894 to ADSP-2101/5 interface

The interface circuit digital signal processor of AD7894 and ADSP-2101/5 is shown as in Fig. 8. In the interface shown, the RFS1 output of the ADSP-2101/5s SPORT1 serial port is used to gate the serial clock (SCLK1) of the ADSP-2101/5 before it is applied to the SCLK input of the AD7894. The RFS1 output is configured to run high. The busy line from the AD7894 is connected to the IRQ2 line of the ADSP-2101/5 to generate an interrupt at the end of the conversion, telling the ADSP-2101/5 to initiate a read operation. The interface ensures that the clock of the AD7894 serial clock input is discontinuous, only 16 serial clock pulses are provided, and the serial clock line of the AD7894 remains low between data transfers. The SDATA line from the AD7894 is connected to the DR1 line of the ADSP-2101/5 serial port.

The timing relationship between the SCLK1 and RFS1 outputs of the ADSP-2101/5 results in a delay of up to 30␣ns between the rising edge of SCLK1 and the rising edge of active high RFS1. It is also required to set 10␣ns of data before the falling edge of SCLK1 for the ADSP-2101/5 to read correctly. The data access time of the AD7894 is 60␣ns (A, B version) from the rising edge of its SCLK input. Assuming a propagation delay of 10␣ns through the external and gate, the high time of the SCLK1 output of the ADSP-2105 must be ≥(30+60+10+10)␣ns, which is ≥110 ns. This means that the serial clock frequency at which the interface of Figure 8 can work is limited to 4.5␣MHz.

Another alternative is to configure the ADSP-2101/5 to accept an external discontinuous serial clock. In this case, an external discontinuous serial clock is provided to drive the serial clock input of the ADSP-2101/5 and AD7894. In this scheme, the serial clock frequency is limited to the cycle rate of the processor, up to 13.8 MHz.

AD7894 to DSP56002/L002 interface

Figure 9 shows the interface circuit between the AD7894 and the DSP56002/L002 DSP processor. The DSP56002/L002 is configured for normal mode asynchronous operation with gated clocks. It is also set to a 16-bit word with SCK output as a gated clock. In this mode, the DSP56002/L002 provides 16 serial clock pulses to the AD7894 in a serial read operation. The DSP56002/L002 assumes that there is valid data on the first falling edge of SCK, so the interface is only three wires, as shown in Figure 9.

The busy line from the AD7894 is connected to the MODA/IRQA input of the DSP56002/L002 to generate an interrupt at the end of the conversion. This will ensure that the read operation is performed after the conversion is complete.

AD7894 performance

Linearity

The linearity of the AD7894 is determined by the on-chip 14-bit D/A converter. This is a segmented DAC that is laser trimmed to 14-bit integral linear and differential linear. The typical relative accuracy of the part is ±1/2␣LSB, while the typical DNL error is ±1/3␣LSB.

noise

In A/D converters, noise appears as code uncertainty in DC applications and as a noise floor in AC applications (eg in FFTs). In a sampling A/D converter like the AD7894, all information about the analog input is present in baseband from dc to 1/2 the sampling frequency. The input bandwidth of track/hold exceeds the Nyquist bandwidth, so in applications where such a signal is present, an antialiasing filter should be used to remove unwanted signals above FS/2 in the input signal.

Figure 10 shows a histogram of 8192 dc input conversions using the AD7894. The analog input is set at the center of the transcoding. It can be seen that almost all codes appear in one output bin, which indicates that the ADC has very good noise performance.

Dynamic performance (mode 1 only)

The AD7894 has a conversion time of 5 microseconds, making it ideal for wideband signal processing applications. These applications require information about the effect of the ADC on the spectral content of the input signal. Signal-to-noise ratio (noise + distortion), total harmonic distortion, peak harmonic or spurious noise, and intermodulation distortion are specified. Figure 11 shows a typical FFT plot after digitizing a 10 kHz, ±10␣V input with the AD7894-10 operating at a 160 kHz sample rate. The signal-to-noise ratio is 80.24db, and the total harmonic distortion is -96.35db.

The formula for signal-to-noise ratio (noise + distortion) (see the Terminology section) is related to the resolution or number of bits of the converter. Rewrite the formula below to give a performance measure in significant digits (N):

where SNR is the signal-to-noise ratio.

The effective number of bits of a device can be calculated from the ratio of its measured signal to (noise + distortion). Figure 12 shows a typical plot of effective bits versus frequency for the AD7894 from dc to F samples/2. The sampling frequency is 160khz. The figure shows that the AD7894 converts a 10␣kHz input sine wave to 13.00 effective bits, which is equivalent to converting the signal to a (noise + distortion) level of 80.02db.

Power Factor

In auto power-down mode, the part can operate at sample rates well below 160 kHz. In this case the power consumption will be reduced and depends on the sampling rate. Figure 13 shows a graph of power consumption versus sampling rate from 1 Hz to 100 kHz in auto power-down mode. Conditions are 5 V supply +25°C. The SCLK pin is held low and no data is being read from the part.