Features

● High linear approximation of limit

● Quick recovery of overspeed: 1NS

● Restricted voltage accuracy: ± 10mv

● —3db Bandwidth (g u003d+6): 260MHz

● Bad bandwidth multiplication: 1000MHz

● G ≥+4V/V stable

● Conversion rate: 1400V/μs [123 [123 ]

● ± 5V and+5V power operation

● Low -gain version: OPA698

Application

] ● Quickly limit ADC input drive

● Low -proportional delay comparator

● Non -linear analog signal processing

● Differential amplifier

● Intermediate frequency limit amplifier amplifier

● OPA689 Upgrade

Instructions

OPA699 is a broadband band voltage feedback op amp, providing bipolar output voltage limit, gain ≥+4 stability. When the two buffer restrictions are controlled by controlling output, it tries to exceed these restrictions. This new output limit structure keeps the displacement error of the limiter at ± 10mv. The linear work of the computing amplifier is within 20 millivolves.

The combination of narrow non -linear range and low limit offset allows the restricted voltage to be set within 100mV of the desired linear output range. Quickly recovering 1NS from limitations can ensure that the driving signal is transparent to the signal channel. To implement the limit function at the output terminal, which is the opposite of the input terminal, it can provide a specified limit accuracy for any gain, and allow OPA699 to be used for all standard computing amplifiers applications.

The non -linear analog signal processing circuit will benefit from the sharp transformation from OPA699 from linear operation to output restrictions. Fast recovery time supports high -speed applications.

OPA699 has an industrial standard Pinout in a SO-8 package. For low -gain applications that need to restore the output limit, please consider OPA698.

Typical features: vs u003d ± 5V

TA u003d+25 ° C, g u003d+6, RF u003d 750 , RL u003d 500 #8486;, vh u003d --vl u003d 2V, unless there is another instructions.

Typical features: vs u003d +5V TA u003d+25 ° C, G u003d+6, RF u003d 750 , RL u003d 500 to VCM u003d+2.5V, VL u003d VCM – 1.2V, VH u003d VCM+1.2V, unless otherwise explained.

Typical application

Broadband pressure operation High -voltage feedback amplifier combined 69V// A's high voltage feedback characteristics. Its output can swing up to 1V from each orbit, and the output current can reach 120mA. These functions make it an ideal interface to drive ADC, while increasing speed protection for ADC input. FIG. 1 shows DC coupling as ± 5V electrical characteristics and typical characteristics foundation, and the dual -power circuit configuration of+6V/V. For the purpose of testing, the input impedance setting is 50 and the resistance is connected to the resistance, and the output is set to 500 The voltage fluctuation reported in the specification is directly measured at the input and output pin. For the circuit in Figure 1, the total output load is 500 | | 900 u003d 321 . Through the sterilizer network between+V and VH grounding, the limited pins are set to VS and ground with ± 2V -VL. These limited voltages are fully bypassed through 0.1 μF ceramic capacitors. The limiter voltage (VH and VL) and their respective bias current (IVH and IVL) have the polarity shown. Figure 1 contains an additional component. The additional resistor (100 ) is connected in series with non -swap input. Coupled with 25 DC source resistance returns the signal generator, which generates an input bias current offset the resistance, which is matched with 125 #8486 at the inverter input (see DC accuracy and offset control control part). Power bypass power consists of two capacitors: one is a 2.2μF electrolytic capacitor and the other is 0.1 μF ceramic capacitors. Power cross -road container clearly shows in Figure 1 and 2, but it will be assumed in other figures. Between the two power pins can also include an additional 0.01 μF power supply capacitor (not displayed here). In the actual PC plate layout, this optional and added capacitors usually increase the two -time decibels to 6 decibels.

Single power supply, no conversion amplifier

FIG. 2 shows a AC coupling, non -conversion gain amplifier for single+5V power operation. The circuit is used for the communication characteristics of OPA699, the power supply is 50 (matching), and the load is 500 The reference of the non -switch to the input is set up by two 1.5K the resistor settings. This generates an input bias current offset the resistance, which is matched with the 750 Move the control part). The power supply by the power supply consists of two capacitors: one is a 2.2μF electrolytic capacitor and the other is a 0.1 μF ceramic capacitor. Power barrier container clearly shows in Figure 1 and Figure 2, but it will be assumed in other figures. The limiter voltage (VH and VL) and their respective bias current (IVH and IVL) have the polarity shown. These limited voltages are fully bypassed through 0.1 μF ceramic capacitors. Note that the single power circuit can use three resistors to set VH and VL, while the dual -power circuit usually uses four resistors to refer to the extreme voltage of ground. When the circuit is displayed+5V, the same circuit can be used for single -power supply for high+12V.

Broadband inverter operation

There are several benefits to run OPA699 as a inverter amplifier, when you need to match 50 Input impedance is especially useful. Figure 3 shows the inverter gain of -4V/V circuits as a typical characteristic foundation of the inverter mode.

In the case of inverter, only the feedback resistance as part of the total output load connects with the actual load. For the 500 load used in typical features, the total load in this reverse configuration is 329 The gain resistance is set to obtain the required gain (in this example, the gain is 187 ), and if necessary, you can use an additional input resistance (RM) to set the total input impedance to the source. In this case, RM u003d 68.1 with 187 gain setting the resistor in parallel to get the matching input impedance of 50 Only when the input needs to be matched with the source impedance, this match is needed, such as the characteristic test using the circuit in Figure 3.

For the matching of the bias current, the input of no switching requires 169 The calculation of this resistor includes DC coupling 50 source impedance and RG and RM. Although the resistor will eliminate bias currents, it must be well decoupled (0.1 μF in Figure 3) to filter the noise contribution and input current noise of the resistance.

When the required RG resistor is close to 50 the bandwidth of the circuit in Figure 3 will far exceed the bandwidth at the same gain in Figure 1. When the analysis includes 50 source impedance, the noise gain in Figure 3 circuit is lower. For example, when the signal gain is -15 (RG u003d 50 , RM u003d Open, RF u003d 750 ), 50 source, the noise gain of the circuit 3 circuit will be added to the noise gain equation. It is 1+750 /(50 +50 ) u003d 8.5. The bandwidth ratio provided by this method is irreversible gain +15 It is much higher. Applying 1GHz gain bandwidth to OPA699, from 50 Source to 50 RG to -15 will provide 140MHz bandwidth, instead of the inverted gain to +8 will generate 55MHz bandwidth, as shown in Figure 4 of Figure 4, as shown in Figure 4 of Figure 4 The measurement results show.

The low -gain compensation of the improved SFDR

In the case of a low -gain and acceptable reversal operation, new external compensation technology can be used Maintain the full conversion rate and noise benefits of OPA699, and at the same time provide an increased loop gain and related distortion improvement provided by the non -unit gain and stable computing amplifier. This technology -shaped loop gain to obtain good stability, and at the same time provides a second -order low -line frequency response that is easy to control. To set up compensation capacitors (CS and CF), consider the semi -circuit in Figure 5, where the power supply is used at 50

Considering the noise gain of the circuit in Figure 5, the low -frequency noise gain (NG1) is set by a resistance ratio, and the high -frequency noise gain (NG2) is set by a capacitor ratio. The capacitor value sets the transition frequency and high -frequency noise gain. If the high -frequency noise gain determined by the NG2 u003d 1+CS/CF is set to the minimum stable gain recommended by the computing amplifier, and the noise gain polar point (set by 1/RFCF) is properly placed, it will produce a very good one Controlled second -order low -line frequency response.

You need to select the values u200bu200bof CS and CF at the same time, just need to solve two parameters and three equations. The first parameter is the target high -frequency noise gain (NG2), which should be greater than the minimum stable gain of OPA699. Here, using NG2 u003d 26 target. The second parameter is the expected low -frequency signal gain, and it also sets a low -frequency noise gain (NG1). In order to simplify the discussion, we respond to the target's maximum flat second -order low -pass Bartworth frequency (Q u003d 0.707). The signal gain shown in FIG. 5 Set low -frequency noise gain to NG1 u003d 1+RF/RG (u003d 2). Then, only the width of the gain bandwidth of these two gains and OPA699 (1000MHz), the key frequency in the compensation is set by the equal form 1.

In physical, this ZO (22.3MHz, for the value shown above) is set to 1/(2πrf (CF+CS)), and it is noise increasingly The frequency of intersecting the increase in the unit gain (if the projection returns to the 0db gain). The actual zero point of noise gain appears at Ng1 #8226; ZO, and the pole point in the noise gain appears at NG2 #8226; ZO. The actual setting is 1/(RFCF). Because GBP is represented by Hertz, it can be used by ZO by 2π to get CF by seeking to solve equations 2.

Finally, because CS and CF set up high -frequency noise gains, the use equation 3 determines CS (using ng2 u003d 6 to solve CS):

CS u003d 15pf.

In Figure 5, these two calculation values u200bu200bare slightly reduced to illustrate the parasite. The closedLoop bandwidth is equal to equal equalization 4.

For the value shown in FIG. 5, F -3DB is about 149MHz. This is smaller than the simplicity to remove the gain bandwidth (GBP). The compensation network controls the bandwidth to a lower value, and at the same time provides a full conversion rate at the output end, and increases the loop gain at the frequency below NG1 #8226; ZO, which improves distortion performance.

Low distortion, limited output, ADC input drive

FIG. 6 shows a simple ADC driver that works on a single power supply and provides excellent distortion performance. The input range of the extreme voltage tracking converter is completely prevented from entering the driver. Note that the restriction voltage has been set to 100 millivolves higher than/lower than the converter's corresponding reference voltage. The circuit also uses external compensation to achieve an improved distortion, making the reverse gain to 2.

Limited output, Differential ADC input drive

FIG. 7 shows a differential ADC driver using OPA699 limiter to protect ADC input. Use two OPA699. The first is a reversal configuration of -2 gain. The second is in an irreversible configuration of +2. Refer to the ""Extract SFDR Low -gain Compensation"" section, understand the discussion of OPA699 when working at the time of gain less than 4. Each amplifier swing 2VPP, providing 4VPP differential signals to drive the input of ADC. The limiter is set at a place where the maximum semaphore of each amplifier is 100mV, so as to maintain the input protection of the ADC while maintaining the acceptable distortion level.

Precision Half -wave rectifier

FIG. 8 shows a semi -wave rectifier with excellent accuracy and speed. VH (pin 8) is usually default to 3.5 when it is opened, and the negative limit is set to ground.

The gain of the circuit in FIG. 8 is set to +6. Figure 9 shows the input and output of ± 0.5V 100MHz input.

Ultra high -speed Schmidt trigger

FIG. 10 shows a very high -speed Schmidt trigger. The output level is precisely defined and the switching time is abnormal. The output voltage fluctuates between VH and VL.

The circuit works as follows. When the input voltage is less than VHL,The output is limited to VH. When the input is greater than VHH, the output is limited to VL, VHL and VHH as follows:

Due to the reversal function of the Schmidt trigger, VHL corresponds to VOUT u003d VH , VHH corresponds to VOUT u003d VL. FIG. 11 shows that Schmidt trigger works under VREF u003d+5V. This gives us VHH u003d 2.4V and VHL u003d 1.6V. In Schmidt trigger configuration, the transmission delay of OPA699 is 4NS from high to low, and 4NS from low to high.

Design tool

Demonstration fixture

Print circuit board (PCB) can help the use of OPA699 preliminary assessment of circuit performance. The fixture is provided for free as an uns filled PCB and delivered with the user guide. The summary information of the fixture is shown in Table 1.

Demonstration fixture can be requested on the Texas instrument website and via the OPA699 product folder.

Operation suggestion

Operation theory

OPA699 is a stable operation amplifier with a voltage feedback with a gain of+4V/V. The output voltage is limited within the range of the voltage settings on the limiter pin (5 and 8). When the input tries to pass the drive output, the limiter controls the output buffer. This movement of the limiter avoids any part of the signal pathway, and it can achieve fast speeding and good restrictions accuracy under any signal gain. There is a very sharp transition from a linear working area to output limit. This conversion allows the voltage of the limit to be set at the expected signal range of ( lt; 100mv). Near the limiter voltage, the distortion performance is also very good.

Output limiter

When the output voltage is between the limit voltage VH (pin 8) and VL (pin 5), the output voltage is related to the input linear. When the output is trying to exceed VH or VL, the corresponding limiter buffer controls the output voltage and keep it on VH or VL. Because the limiter acts on the output, their accuracy will not change with gain. The transition from a linear working area to the output limit is very obvious. The expected output signal can safely reach the 30MV range of VH or VL without non -linearity. The limiter voltage can be set within the 0.7V range of the power supply (VL ≥-VS+0.7V, VH ≤+VS-0.7V). The distance between them must be at least 400 millivolves (VH -VL ≥ 0.4 volts). When the pin 5 and 8 are kept open, VH and VL enter the default voltage limit; the minimum value is given in the electrical specifications. It can be seen from Figure 12 that the expected range (vs -default limit voltage) u003d net empty in Figure 12.

When the limiter voltage of the power supply is greater than 2.1V (VL ≥-VS+2.1V or VH ≤+VS – 2.1V), you can use a simple resistor division to set up settings VH and VL (see Figure 1). Ensure that the limit is input (Figure 8) in the calculation (Figure 8) (that is, IVL u003d 50 μA in the pin 5, IVH u003d+50 μA in the pin 8). In order to obtain a good limiter voltage accuracy, run a minimum 1MA static bias current through these resistors. When the limiter's voltage needs to be within the 2.1V range of the power supply (VL≤-VS+2.1V or VH ≥+VS – 2.1V), consider using a low impedance buffer to set VH and VL to minimize the partial pressure current Errors caused by uncertainty. This situation is usually suitable for single power operations (vs u003d+5V). Figure 2 Run 2.5mA by setting VH and VL resistors. This limits the error caused by the target limit voltage of IVH and IVL lt; ± 1%. The DC accuracy of the limit device depends on the attention of details. The two main error sources can be improved as follows:

#8226; when the power supply is used to drive the resistance division of VH and VL, it may produce a large error (eg ± 5%). Use more accurate power to bypass the pins 5 and 8 with a good capacitor to increase the PSRR of the amplifier.

#8226; The sterilizer in the resistor can also control the resistance of the resistor. Use 1%resistance.

Other error sources also have an impact, but the impact on the DC accuracy of the limiter is very small:

#8226; reduce the offset caused by the limited input bias current. As mentioned above, select the resistor in the resistor division.

#8226; The DC error of the signal path is considered as a factor that causes uncertainties in the available output swing.

#8226; Limitor compensation voltage only minimizes the accuracy of the limiter. FIG. 13 shows how the limiter affects distortion performance. There is almost no observing output voltage swinging to the limiter voltage. In this figure, when the limiter voltage is reduced symmetrically, it drives a fixed ± 1V output width. Before the limiter was reduced to ± 1.1V, there was almost no observation of distortion.

Output driver

OPA699 has been optimized and can drive 500 load, such as ADC. It still performs well during driving 100 the technical specifications of 500 showing 500 This makes OPA699 an ideal choice for various high -frequency applications.

Many high -speed applications, such as driving ADC, requires low -output impedance operations amplifiers. As the typical performance curve of the output impedance and frequency, OPA699Keep a very low closed -loop output impedance in the frequency. The closed -loop output impedance increases with frequency, because the frequency of the circuit gain is reduced.

Thermal factors

OPA699 does not require heat dissipation under most operating conditions. The maximum temperature required will set the maximum allowable internal power consumption as described below. In any case, the highest knot temperature must not exceed 150 ° C.

Total internal power consumption (PD) is the sum of the additional power consumed by static power (PDQ) and output (PDL) when transmitting load power. PDQ is the specified air -load power supply current multiplied by the total power voltage of the entire component. PDL depends on the required output signals and loads. For the ground resistance load and equal dual -pole power, when the output voltage is 1/2 of the power supply voltage, the value is the maximum value. In this case, PDL u003d vs2/(4RL), where RL includes feedback network load. Note that the power consumption of the internal power is the output level, not the load.

The working knot temperature is: TJ u003d TA+PD xθja, where the TA is the ambient temperature. For example, at the maximum TA u003d+85 ° C, G u003d+6, RF u003d 750 , RL u003d 500 and the maximum TJ calculation of OPA699id of ± vs u003d ± 5V is as follows:

This will be the largest TJ of VO u003d ± 2.5VDC. Most applications will be at low output -level power and lower TJ.

Capaciture load

Capacity load, such as ADC input, will reduce the phase of the amplifier, which may lead to high -frequency peak or oscillation. The capacitance load ≥2PF should be isolated by a small resistance to the output, as shown in Figure 14. Increasing gain from +2 will increase capacitor driving capabilities because of the increase in phase margin.

Generally speaking, the capacitance load should be minimized to obtain the best high -frequency performance. The capacitance of the coaxial cable (RG-58 is 29pf/FT) will not be loaded to the amplifier when the characteristic impedance of the coaxial cable or transmission line is terminated.

Frequency response compensation

OPA699 internal compensation is stable in unit gain, and it has a nominal phase habits of 60 ° when the gain is +6. Phase margin and peaks improved at higher gain. Recall that the reversal gain is -5 is equivalent to a bandwidth gain to +6 (that is, noise gain u003d 6). Standard external compensation technology work with this device. For example, in the reverse configuration, you can limit the bandwidth without modifying the reversal gain by putting the ground on the reverse node in the reverse node. This increases high -frequency noise gain, thereby limiting bandwidth.

If the unit gain stable amplifier is required, it is recommended to use OPA698.

It should be required to feedback resistanceIn the use, for example, an optoelectronic diode cross -blocking the bulk, and the parasitic capacitance entered from the inverter to the ground will cause peak or oscillation. To compensate for this impact, connect a small capacitor to connect with feedback resistors. Bandwidth will be limited by the pole of feedback resistance and capacitors. In other high -gain applications, a three -resistance three -link network is used to reduce the RC time constant set by parasitic capacitors.

Pulse stable time

OPA699 can make a very fast response time to the pulse input. In order to obtain the best stable time, the frequency response is required to be flat and phase linear. For capacitance loads, such as ADC, use the RS -capacitance load recommended in the typical performance curve. The extremely fine scale (0.01%) needs to pay close attention to the grounding background in the power supply counter -coupled capacitor.

When recovery from the speeding gear, the pulse stability characteristics are very good, as shown in the typical characteristics.

Twisted

OPA699 distortion performance is specified by 500 load (such as ADC). As shown in Figure 15, the driver load with less resistance will increase deformation. Remember to include the feedback network in the load resistance calculation.

Noise performance

High conversion rate, voltage feedback operations amplifier usually achieve conversion rate at a high input noise voltage.

However, the 4.1NV/√Hz input voltage noise of OPA699 is far lower than similar amplifiers. The input terminal voltage noise is combined with the two input -end reference current noise items, which can provide lower output noise under various working conditions. FIG. 16 shows the noise analysis model containing all noise items. In this model, all noise items are considered noise voltage or current density items, and the unit is NV/√Hz or PA/√Hz.

The total output spots noise voltage can be calculated as a square root of all square output noise voltage contributors. Formula 5 shows the general form of the output noise voltage, as shown in Figure 16.

This expression will be removed by noise gain (ng u003d (1+rf/rg)). As shown in equivalent 6.

Evaluate these two equations of the OPA699 circuit and component value (see Figure 1) to get 27.4nv/√Hz total output point noise voltage and 4.6nv/√Hz Total equivalent input point noise voltage. This total investment refers to the 4.1NV/√Hz specification of the voltage noise of the computing amplifier voltage noise. As long as the impedance restrictions on the input end of each operation amplifier are limited to the maximum value of 300 this case will occur. Keep (RF || RG) and non -ease input source impedance is less than 300 it will meet the consideration of noise and frequency response at the same time. Because the noise caused by the resistance can be ignored, the bias current of the reverse operation amplifier configuration in Figure 3 eliminates the additional capacitors on the resistor (RT) on the resistance of the resistor (RT), but it is still desirable.

DC accuracy and offset control

The balance input stage of broadband voltage feedback amplifier allows good DC output accuracy in various applications. Compared with similar products, the power current of OPA699 provides stricter control. Although the high -speed input level really requires a relatively high input bias current (usually 3 μA at each input terminal), the tight match between them can be used to reduce the output DC error caused by the current. By matching the DC source resistance that appears at two inputs, the total output offset voltage can be greatly reduced. This reduces the output DC error caused by feedback resistance due to the input bias current. In the most worst case,+25 ° C input offset voltage and current specification evaluation of Figure 1 configuration, give the output offset voltage in the worst case, NG u003d non -conversion signal gain, equal to:

[ 123]

Generally, you need to fine -tune the output offset or DC work point adjustment. There are many technologies to introduce DC offset control in the computing amplifier circuit. Most of these technologies are ultimately increased DC current through feedback resistors. When selecting the method of mitigation and fine -tuning, a key consideration is the effect on the frequency response of the expectation signal path. If the signal path is non -reversible, it is best to use offset control as inversion and signal applications to avoid interaction with the signal source. If the signal path is reversed, you can consider the offset control of the input application of non -turbulent input. However, the DC offset voltage on the harmony will return the DC current to the power supply, which must be considered. For reverse computing amplifiers input application bias adjustment can change noise gain and frequency response flatness. For DC coupling inverters, Figure 17 shows an example of the minimum offset adjustment technology that has minimized signal frequency response. In this case, the DC offset current through the resistance value that is much larger than the signal channel is introduced into the inverter input node. This will ensure that the regulatory circuit has the minimum effect on the width gain and frequency response.

Circuit plate layout guide

The best performance of the best performance needs to be carefully paid attention to the design and component selection of the best performance. The recommended PCB layout technology and component selection standards are as follows:

A), minimize parasitic capacitors that communicate with any communication to all signal I/O pins. Open the window of the ground and power plane around the signal I/O pins, and make the ground and power plane of other places intact.

B) Provide high -quality power supply. Use a linear regulator, ground plane and power plane to provide power.Place the high -frequency 0.1 μF decoupled power container in a place where the feet of each power supply lt; 0.2 "". Use wide and short lines to connect these capacitors to the ground and power plane. ) High -frequency decoupled power container to bypass the low frequency. They may be slightly far away from the device and shared between multiple adjacent devices.

The problem of inductance, grounding circuit, transmission line effect and transmission delay. Pay special attention to feedback (RF), input and output resistance.

D), use high -frequency components to minimize parasitic elements. The resistor should be very low electric resistance resistance. Type. Surface stickers are the best work and allow more compact layouts. Metal membrane or carbon compound axial leading resistance can also provide good performance when the lead is as short as possible. Resistance. Remember, most potentiocators have large parasitic capacitors and inductors. Multi -layer ceramic -type capacitors are the best working and small space. Single -piece ceramic capacitors also work well. Use low ESR and ESL RF RF. Capacitor. The high -power tube feet bypass power container (2.2 μF to 6.8 μF) should be 钽 to obtain better high -frequency and pulse performance.

E), select low resistance values u200bu200bto make resistors and parasitic parasites The time constant of the connection capacitance setting is the smallest. Good metal membrane or surface -installed resistor has a parasitic parallel c