Features
8-pin solution reduces external components Wide range of universal AC input voltage Fixed 65 kHz operating frequency with 98% maximum duty cycle (typ).
Output Over/Under Voltage Protection Input Brown Output Protection Cycle-by-Cycle Peak Current Limit Open Loop Detection Low Power User Controlled Standby Mode Applications
CCM boost power factor corrected power converters from 100W to >2kW
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The UCC28019A 8-pin active power factor correction (PFC) controller uses a boost topology operating in continuous conduction mode (CCM). The controller is suitable for systems in the 100W to >2kW range and accepts a wide range of universal AC line input. Startup current during undervoltage lockout is less than 200 μA. The user can control the low power standby mode by pulling the VSENSE pin below 0.77 V.
Low-distortion waveform shaping of the input current is achieved using average current mode control, eliminating the need for input line sensing and reducing the number of external components. Simple external networks allow flexible compensation of current and voltage control loops. The switching frequency is fixed internally and adjusted to better than ±5% accuracy at 25°C. Fast 1.5 A peak gate current drives external switches.
Many system level protection features include peak current limit, soft overcurrent, open loop detection, input brown output and output over/under voltage. Soft-start limits the boost current during startup. A trimmed internal reference provides accurate protection thresholds and regulation set points. An internal clip limits the gate drive voltage to 12.5V.

Overview
The UCC28019A is a switch mode controller for boost converters for power factor correction operating at fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate as an active power factor correction preregulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz, ensuring that both fundamental and second harmonic components of the conducted EMI noise spectrum are below the EN55022 conducted band measurement limit of 150 kHz.
Its tightly trimmed internal 5-V reference voltage provides precise output voltage regulation over typical world-wide 85-265V AC mains input ranges from zero to full output load.
The adjustment is done in two loops. Under continuous inductor current conditions, the inner current loop forms the average input current to match the sinusoidal input voltage. Under light load conditions, depending on the boost inductor value, the inductor current may be discontinuous, but despite the higher harmonics, it still meets EN61000-3-2 Class D requirements. The outer voltage loop regulates the PFC output voltage by producing a voltage on VCOMP (depending on line and load conditions) that determines the internal gain parameter that maintains a low-distortion steady-state input current waveform.
Functional block diagram

CHARACTERISTICS SOFT START Soft start controls the rate of rise of VCOMP to obtain linear control of the duty cycle over time. The output VCOMP of the voltage loop transconductance amplifier is pulled low during UVLO, IBOP and OLP (open loop protection)/standby. Once the fault condition is removed, an initial precharge source rapidly charges VCOMP to approximately 1.9V. After this point, a constant 30µA current is fed into the compensation component, causing the voltage on this pin to rise linearly until the output voltage reaches 85% of its final value. At this point, the source current decreases until the output voltage reaches 99% of its final rated voltage. The soft-start time is controlled by the value of the voltage error amplifier compensation capacitor selected and programmed by the user based on the desired loop crossover frequency. When the output voltage exceeds 99% of the rated voltage, the pre-charge power supply is interrupted and the EDR is no longer suppressed.

System Protection System-level protection features help keep the converter within a safe operating range.
VCC undervoltage lockout (UVLO)
During startup, an undervoltage lockout (UVLO) keeps the device off until VCC rises above the 10.5-V enable threshold, VCCON. Due to the typical 1V hysteresis at UV low voltages for improved noise immunity, the device shuts down when VCC drops to the V disable threshold VCCOFF.

Ultraviolet Radiation If, during a brief AC line disconnect, the VCC voltage drops below the level required to bias the internal fault circuit, the UVLO condition enables a special fast discharge circuit to continue to discharge the VCOMP capacitor through a low impedance despite the complete lack of VCC. This helps avoid excessive current surges when the AC line returns while there is still a lot of voltage on the VCOMP capacitor. Typically, these capacitors can discharge to less than 1.2 V within 150 ms of losing VCC.
Input Brown Output Protection (IBOP)
The sensed line voltage input, VINS, provides the designer with a way to set the desired mains RMS voltage level at which the PFC preregulator should start, vacuum on, and at the desired mains RMS voltage level , it should close and the vacuum is off. This prevents unnecessary continuous operation of the system at or below the brown-out voltage, where excessive line currents can overheat components. Additionally, since the VCC bias is not derived directly from the line voltage, IBOP protects the circuit from low line conditions that might not trigger the VCC UVLO shutdown.
Input Loss of Field Protection The input line voltage is sensed directly from the rectified AC supply voltage through a resistor divider filter network, providing a scaled and filtered value at the VINS input. When VINS falls below (from high to low) 0.8 V, IBOP will put the device into standby mode, VINSBROWNOUT_th. When VIN rises (from low to high) by more than 1.5 V, the device will come out of standby. The bias current from VINS, IVINS V, is less than 0.1 μA. When the bias current is this low, there is little concern about any set point error caused by this current flowing through the sensing network. The highest practical resistor value for this network should be chosen to minimize power dissipation, especially in applications requiring low standby power. Note that higher resistor values are more susceptible to noise, but low-noise PCB layout techniques can help mitigate this. Also, depending on the type of resistor used and its voltage rating, RVINS1 should employ multiple series resistors to reduce voltage stress.

Output Over Voltage Protection (OVP)
VOUT(OVP) means that the output voltage exceeds 5% of the rated value, causing VSENSE to exceed the 5.25-V threshold (5-V reference voltage +5%), VOVP. The normal control loop is bypassed and the gate output is disabled until VSENSE falls below 5.25 V. For example, in a system with a rated output of 400 V, VOUT(OVP) is 420 V.
Open Loop Protection/Backup (OLP/Backup)
If the output voltage feedback element fails and disconnects (open loop) the input signal, the voltage error amplifier may increase the gate output to the maximum duty cycle. To prevent this, an internal pull-down force VSENSE is low. If the output voltage falls below 16% of rated voltage, causing VSENSE to drop below 0.8V, the device is in standby, i.e. the PWM switching is stopped, and the device remains on, but draws standby current to 2.9mA the following. This shutdown feature also provides the designer with the option to use an external switch to pull VSENSE low.
ISENSE Open Needle Protection (ISOP)
If the current feedback part fails and disconnects (ISO) the input signal (open loop), then the PWM stage is likely to increase the gate output to the maximum duty cycle. To prevent this, an internal pull-up supply drives ISENSE above 0.1V, such that a detector forces a state in which PWM switching stops while the device remains on, but pulls the standby current low to below 2.9mA. This shutdown function avoids continuous operation and severely distorted input current in OVP.
Output Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
During normal operation, small disturbances in the PFC output voltage rarely exceed a 5% deviation, and the gain-driven output of the normal voltage control loop returns to normal. For large changes in line or load, if the output voltage drop exceeds -5%, output undervoltage (UVD) is detected and the dynamic response (EDR) is enhanced to speed up the slow response of the low bandwidth voltage loop. During EDR, the transconductance of the voltage error amplifier increases by a factor of about 16 to charge the voltage loop compensation capacitor to the level required for regulation. EDR will be removed when VSENSE>4.75 V. The EDR function will not activate until the soft start is complete.

Overcurrent Protection The inductor current is sensed by a low value resistor RISENSE in the input rectifier loop. The other side of the resistor is connected to system ground. Voltage is induced on the rectifier side of the sense resistor, and the voltage is always negative. The voltage at ISENSE is buffered by a fixed gain of -1.0 to provide a positive internal signal to the current function. There are two overcurrent protection functions: soft overcurrent (SOC) to protect the output from overload, and peak current limit (PCL) to protect the inductor from saturation.

The gate driver gate output uses a current-optimized structure to directly drive large value MOSFET total gate capacitance at high switching speeds. An internal clamp limits the voltage on the MOSFET gate to 12.5v (typ). When the VCC voltage is below the UVLO level, the gate output remains off. An external gate drive resistor, RGATE, can be used to limit the rise and fall times of the gate drive circuit, suppress ringing caused by parasitic inductance and capacitance, and reduce EMI. The final value of the resistor depends on parasitic elements and other considerations related to the layout. Between the gate and ground, a 10-kΩ resistor close to the MOSFET gate discharges stray gate capacitance and helps prevent accidental dv/dt-triggered turn-on.
Current Loop The entire system current loop consists of a current averaging amplifier stage, a pulse width modulation stage, an external boost inductor stage and an external current sensing resistor.
The negative polarity signal of the ISENSE and ICOMP function current sense resistors is buffered and inverted at the ISENSE input. The internal positive signal is then averaged by a current amplifier (gmi) whose output is the ICOMP pin. The voltage on ICOMP is proportional to the average inductor current. Add an external capacitor to ground on the ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is determined by the internal VCOMP voltage. This gain is non-linear to accommodate the worldwide AC line voltage range.
ICOMP is internally connected to 4V when the device is in fault or standby.
Pulse Width Modulator
The PWM stage compares the ICOMP signal to a periodic ramp to generate a leading edge modulated output signal that is high when the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined by a nonlinear function of the internal VCOMP voltage.
The pulse width modulation is generated at the beginning of the cycle, and the PWM output signal triggered by the internal clock is always active low. The output remains low for a minimum off-time, tOFFômin, and then ramps up linearly to intersect the ICOMP voltage. The intersection of the ramp ICOMP determines tOFF, and therefore DOFF. Since DOFF=VIN/VOUT according to the boosttopology equation, and VIN is a sinusoidal waveform, and since ICOMP is proportional to the inductor current, the control loop forces the inductor current to follow the input voltage waveform to maintain boost regulation. Therefore, the average input current is also sinusoidal.
control logic
The output of the PWM comparator stage is passed to the gate driver stage, which is controlled by various protection functions in the device. The gate output duty cycle can be as high as 99%, but always has the shortest off-time tOFF-min. Normal duty cycle operation can be directly interrupted by OVP and PCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the gate output pulse and further inhibit the output until SS operation begins.
voltage loop
The outer control loop of the PFC controller is the voltage loop. The circuit consists of a PFC output sensitive stage, a voltage error amplifier stage and a nonlinear gain generating circuit.
The output sensing resistor divider network from the PFC output voltage to GND forms the sensing block of the voltage control loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulated reference voltage.
As with the VINS input, the very low bias current at the VSENSE input allows selection of the highest practical resistor value for the lowest power dissipation and backup current. A small capacitor from VSENSE to GND is used to filter the signal in high noise environments. The filter time constant should normally be less than 100μs.
Voltage Error Amplifier The output current produced by the transconductance error amplifier (gmv) is proportional to the difference between the voltage feedback signal at VSENSE and the internal 5-V reference voltage. This output current charges or discharges the compensation network capacitor on the VCOMP pin to establish a VCOMP voltage suitable for system operating conditions. Proper selection of compensation network components results in a stable PFC pre-regulator over the entire AC line range and 0-100% load range. The total capacitance also determines the rate of rise of the VCOMP voltage during soft-start, as previously described.
During any fault or standby state, the amplifier output VCOMP is pulled to GND to discharge the compensation capacitor to the initial zero state. Typically, large capacitors have a series resistance that delays the full discharge of their respective time constants (perhaps a few hundred milliseconds). If the VCC bias voltage is removed quickly after UVLO, the normally discharged transistor on VCOMP will lose drive and a large amount of voltage may be left on the large capacitor, negating the benefits of the subsequent soft-start. The UCC28019A includes a parallel discharge path without VCC bias to further discharge the compensation network after VCC is removed.
When the output voltage disturbance is greater than ±5%, the amplifier will exit linear operation. During overvoltage, the OVP function acts directly to turn off the gate output until VSENSE returns to within ±5% of regulation. In a brown-out condition, the UVD function calls EDR, which immediately increases the transconductance of the voltage error amplifier to about 440µS. This higher gain helps charge the compensation capacitor to the new operating level faster.
Nonlinear gain generation
The voltage at VCOMP is used to set the current amplifier gain and PWM ramp. As mentioned, this voltage is buffered internally and then modified by the SOC function.
When VCOMP is changed, the current gain and PWM slope are adjusted together to suit different system operating conditions (set by line voltage and output load level) to provide a low distortion, high power factor input current waveform that follows the input voltage waveform.
Device functional mode This device does not have a functional mode.
APPLICATIONS AND IMPLEMENTATION NOTE The information in the application section below is not part of the TI component specification and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining the suitability of parts for their purpose. Customers should verify and test their design implementation to confirm system functionality.
Application Information
The UCC28019A is a switch mode controller for boost converters for power factor correction operating at fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate as an active power factor correction preregulator. The operating switching frequency is fixed at 65 kHz.
An internal 5-V reference voltage provides accurate output voltage regulation over a typical worldwide 85VAC to 265Vac power input range (from zero to full output load). Available system loads range from 100 watts to several kilowatts.
The adjustment is done in two loops. Under continuous inductor current conditions, the inner current loop forms the average input current to match the sinusoidal input voltage. Under light load conditions, depending on the value of the boost inductor, the inductor current may be discontinuous, but still meet IEC 61000-3-2 Class A/D requirements despite higher harmonics. The outer voltage loop regulates the PFC output voltage by generating a voltage on VCOMP (depending on line and load conditions) that determines the internal gain parameter that maintains a low distortion, steady state, input current waveform.
A typical application uses the UCC28019A's continuous conduction mode power factor correction boost converter design process and component selection. The target design is a universal input 350-W power factor corrected boost converter designed for ATX power supply applications. This design process is tied directly to the UCC28019A Design Calculator (SLUC117) spreadsheet, which can be found in the Tools section of the UCC28019A product folder on the Texas Instruments website.

The device bias operates in several states. During startup, VCC undervoltage lockout (UVLO) sets the minimum operating DC input voltage for the controller. There are two UVLO thresholds. When the UVLO turn-on threshold is exceeded, the PFC controller turns on. If the VCC voltage is below the UVLO shutdown threshold, the PFC controller shuts down. During the UVLO process, the current consumed by the device is minimal. After the device starts up, soft start (SS) is initiated to increase the boost inductor current in a controllable manner to reduce stress on external components and avoid output voltage overshoot. During soft-start, after output regulation, the device draws its normal operating current. If any of several fault conditions are encountered, or if the device is put into standby by an external signal, the device will consume a reduced standby current.
Layout Guidelines As with all PWM controllers, the effectiveness of filter capacitors on signal pins depends on the integrity of the ground return. The pins of the UCC28019A are ideal for separating high di/dt induced noise on the power supply ground from the low current quiet signal ground required for adequate noise immunity. A star point ground connection can be achieved at the ground pin of the device by simply cutting across the ground plane of the printed circuit board. Capacitors on ISENSE, VINS, VCOMP and VSENSE must return directly to the quiet part of the ground plane, driven by the signal GND indicates, not the high current return path of the converter, as indicated by the power supply GND. Since the example circuit in Figure 34 uses surface mount components, ICOMP capacitor C10 has its own dedicated ground pin return.