The VNI8200XP is a monolithic 8-channel driver with very low supply current, integrated SPI interface and high efficiency 100mA micropower step-down switching regulator peak current control loop mode. Implemented in STMicroelectronics 8482 ; VIPower™ technology, this integrated circuit is designed to drive any type of load with one side grounded.
Active channel current limiting combined with thermal shutdown, independent of each channel, and automatic restart protects the device from overload.
Additional embedded features include: loss of ground protection to automatically shut down device outputs on ground disconnect, undervoltage shutdown with hysteresis, power good diagnostics for valid supply voltage range identification, output enable for immediate power output on/off, and programmable Watchdog function for safe operation of microcontroller; case overheat protection for controlling IC case temperature.
The device embeds a four-wire SPI serial peripheral with selectable 8-bit or 16-bit operation; via a select pin, the device can also operate using a parallel interface.
Both 8-bit and 16-bit SPI operation are compatible with daisy chain connections.
The SPI interface allows the output driver to be commanded by enabling or disabling each channel (16-bit format) with parity control for communication robustness. It also allows monitoring of the status of the IC, signal power is good, over-temperature status of each channel, IC temperature warning detection.
A built-in thermal shutdown protects the chip from overheating and short circuits. In an overload condition, when the IC temperature falls below a threshold determined by the temperature hysteresis, the channel automatically closes and reopens, thus controlling the junction temperature. If this condition brings the case temperature to the case temperature limit, the TCSD, the overload channel is shut down and not restarted at the same time when the case and connector temperatures drop below their own reset thresholds. In the case of a warm reset, the loaded channel will not turn on until a junction temperature reset event occurs. Non-overloaded channels continue to function normally. Case temperatures above TCSD are reported through the TWARN drain pin.
Internal circuitry provides a non-latching common fault indicator report if one of the following events occurs: channel overheating, parity failure. Power good diagnostics warns that the controller supply voltage is below a fixed threshold.
The watchdog function is used to detect the occurrence of software faults of the host controller. The watchdog circuit generates an internal reset when the internal watchdog timer expires. A watchdog timer reset can be achieved by applying a negative pulse on the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This pin also allows programming of a wide range of watchdog timings.
An internal LED matrix driver circuit (4 rows, 2 columns) allows detection of the state of individual outputs. An integrated buck regulator provides the supply voltage for the internal LED matrix driver and logic output buffer, and can be used to power an external optocoupler if the application requires isolation. The regulator is protected against short circuits or overloads due to pulse-by-pulse current limiting with a peak current control loop.

Reverse Polarity Protection Reverse polarity protection can be implemented on board using two different solutions:
1. Place a resistor (RGND) between the IC ground pin and the load ground
2. Place a diode between the IC ground pin and the load ground If option 1 is selected, the minimum resistor value must be chosen according to the following formula:
RGND ≥ VCC/IGND, where IGND is the DC reverse ground pin current, which can be found in this datasheet.
The power dissipated by RGND (when VCC<0: in the case of opposite polarity) is:
PD=(VCC)2/RGND
If option 2 is chosen, the diode must be chosen by considering VRRM>|VCC| and its power dissipation capability:

Serial Data Input (SDI)
If SEL2=H, this pin is the input of the serial control frame. SDI is read on the rising edge of CLK, therefore, the microcontroller must change the state of SDI during the falling edge of CLK.
After the falling edge of SS, SDI is equal to the most significant bit of the control frame.
Serial Data Out (SDO)
If SEL2=H, this pin is the output of the serial fault frame. SDO is updated on the falling edge of CLK, therefore, the microcontroller must read the SDO status during the rising edge of CLK.
When the SS signal is high, the SDO pin is tri-stated, which is equal to the MSB of the fault frame after the falling edge of SS.
Serial Data Clock (CLK)
If SEL2=H, the CLK line is the input clock for serial data sampling. On the rising edge of CLK, the SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller. On the falling edge of CLK, both the SDI and SDO lines are updated to the next bit of the frame, most significant to least significant. When the SS signal is high and the slave is not selected, the microcontroller should drive CLK low (the settings for the MCU SPI port are CPHA=0 and CPOL=0).
Pin Function Description If SEL2=H, the slave select (SS) signal is used to enable the VNI8200XP serial communication shift register; data is refreshed through the SDI pin and sent from
The SDO pin is only when the SS pin is low. On the falling edge of the SS pin, the shift register (containing the fault condition) is frozen, so any change in power switch state is latched until the next SS falling edge event and the SDO output is enabled. On the SS pin rising event, the 8/16 bits present on the SPI shift register are evaluated and the output is driven according to the frame. If more than 8/16 bits (depending on SPI settings) are refreshed internally, only the last 8/16 bits are evaluated; the other bits are refreshed from the SDO pin after the fault condition bit; this way, in a daisy-chain configuration as well Have proper communication.

Bit Select (SEL1)
If SEL2=H, then SEL1 is used to select two possible SPI configurations: 8-bit SPI mode (SEL1=L) and 16-bit SPI mode (SEL1=H). 8/16-bit SPI operation is described below.
output enable (output)
If SEL2=H, the OUT_EN pin provides a quick way to disable all outputs at the same time. When the OUT_EN pin is driven low for at least TRES, the output is disabled when the fault condition in the SPI register is latched. To enable the output, the output pin should be raised and the IC reprogrammed through the SPI interface. Since the fault condition is latched inside the IC and the SPI interface is also functional while the OUT_EN pin is driven low, the SPI can be used to detect if the fault condition occurs before a reset event.
After one TSU cycle, the device can operate normally. Output pins are the fastest way to disable all outputs in the event of a fault.

IC warning box temperature detection
The TWARN pin is a low open-drain output. This pin is activated if the IC case temperature exceeds TCSD. Depending on the PCB thermal design and the RthJC value, this feature allows warnings of PCB overheating conditions.
The TWARN bit is also available via SPI. This bit is unlocked: the TWARN pin is only low when the case overtemperature condition is active (TC > TCSD) and deactivated in that condition (TC Fault Indication The fault pin is an open-drain active low fault indication pin. This pin is activated by one or more of the following conditions:
Channel Over Temperature (OVT)
This pin is activated when at least one channel is at a high junction temperature.
Unlike the SPI fault detection bit, this signal is not latched: the fault pin is low only when the fault state is active, and released after the input drive signal is off or the OVT protection state is removed. If the channel temperature falls below the threshold without the case temperature exceeding TCSD or falling below TCR. This means that the fault pin is low only when the junction overtemperature activates (TJ > TTSD) and releases when the condition is removed (TJ Parity Failure When using SPI mode (SEL2=H), if the parity failure of the incoming SPI frame is detected or counted, the rising edge of CLK differs by a factor of 8 and the fault pin remains low. The fault pin is held high when the counted CLK rising edge is a multiple of 8 and parity is active.
Good power (PG)
The PG terminal is an open drain that indicates the state of the supply voltage. when?
When the VCC supply voltage reaches the Vsth1 threshold, the PG enters a high impedance state. When VCC is below the Vsth2 threshold, it enters a low impedance state.
In 16-bit SPI mode, the PG bit is also available. This bit is set high when the power-good diagnostics is active, and cleared otherwise.

Programmable Watchdog Counter Reset (WD)
If SEL2=H, the VNI8200XP embeds a watchdog counter that must be erased before the negative pulse on the WD pin expires. If the WD counter disappears, the VNI8200XP goes into an internal reset state and all outputs are disabled; to restart normal operation, a negative pulse must be applied to the WD pin.
The watchdog enable/disable pin should be connected to VREG through an external divider.

Step-Down Switching Regulator This IC embeds a high-efficiency 100mA micropower step-down switching regulator. The regulator has short circuit or overload protection. Through current loop control, pulse-by-pulse current limit regulation is obtained during normal operation.
A low-ESR output capacitor connected to the VREG pin helps limit regulation voltage ripple; a low-ESR (less than 10 mΩ) capacitor is best. The control loop pin FB allows regulation of the 3.3V voltage, connecting it directly to VREG, or connecting it to 5V through the voltage divider Rl/Rfbl. The DC-DC converter can be turned off by connecting the feedback pin to the DCVDD pin. In some applications, 5 V or 3.3 V can be supplied externally, or in the case of two or more VNI8200XPs within the same board, the DC-DC converter can be configured on only one device, or power other ICs.
If the DC-DC converter is adjusted to provide 3.3 V regulation, and the VDC_-out is used to power an external load instead of the device, a 33 kΩ resistor must be connected to the VDC_-out pin.