feature

Low power; 1.7 mA/amp supply current; fully specified for 5 V and +5 V supplies; high output current, 125 mA; high speed; 350 MHz, -3dB bandwidth (G=+1); 150 MHz, -3dB bandwidth (G=+2); 2250 V/s slew rate; 20 ns settling time to 0.1%; low distortion; –72 dBc worst harmonic @ 500 kHz, RL=100; –66 dBc worst harmonic Wave@5 MHz, RL=1k; good video specs (RL=1k, G=+2); 0.02% differential gain error; 0.06% differential phase error; gain flatness 0.1dB to 40MHz; 60ns overspeed recovery low Offset voltage, 1.5 mV; low voltage noise, 2.5 nV/Hz√; 8-lead SOIC and 8-lead MSOP available.

application

XDSL, HDSL line drivers; ADC buffers; professional cameras; CCD imaging systems; ultrasonic equipment; digital cameras.

Product Description

The AD8012 is a dual low power current feedback amplifier capable of delivering 350 MHz of bandwidth while using only 1.7 mA per amplifier. It is suitable for high frequency, wide dynamic range systems where low distortion and high speed are essential and low power is key.

The AD8012 provides only 1.7 mA of supply current, and also offers special AC specifications such as a settling time of 20 ns and a slew rate of 2250 V/µs. The video specs are 0.02% differential gain and 0.06 degree differential phase, ideal for such a low power amplifier. Additionally, the AD8012 has a low offset of 1.5 mV.

The AD8012 is ideal for any application requiring high performance with low power consumption.

The product is available in a standard 8-lead SOIC or MSOP package and operates from -40°C to +85°C.

AD8012 maximum power consumption

The maximum power that can be safely dissipated by the AD8012 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic packaged devices is determined by the glass transition temperature of the plastic, which is approximately 150°C. Temporarily exceeding this limit may result in changes in parametric performance due to changes in the stress the package imposes on the mold. Junction temperatures exceeding +175°C for extended periods of time can cause device failure.

The output stage of the AD8012 is designed for maximum load current capability. Therefore, shorting the output to common can cause the AD8012 to source or sink 500 mA. To ensure correct operation, it is necessary to observe the maximum power derating curve. Connecting the output directly to either power rail can damage the device.

test circuit

Supply voltage . . . . . . . . . . . . 12.6 V

Internal power consumption 2

SOIC package (R). . . . . . . .0.8 W

MSOP Package (RM) . . . . . . . . . 0.6 W

Input Voltage (Common Mode). . . . . . . . ±VS

Differential Input Voltage . . . . . . . . . . ±2.5 V

Output short circuit duration. . . . . . . . . Observe the power derating curve

Storage temperature range RM, R. . . . .–65°C to +125°C

Operating Temperature Range (Class A) . . . . . –40°C to +85°C

Lead temperature range (10 seconds for soldering). . . . . . 300°C

be careful

Note: 1. The pressures listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device under the conditions described in the operating section of this specification or any other conditions above is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. Specifications apply to installations in free air at +25°C.

8-lead SOIC package: JA=155°C/W

8 lead MSOP packaging: JA=200°C/W

Electrostatic discharge sensitive devices. Electrostatic charges of up to 4000 volts can easily build up on the human body and test equipment and can be discharged without detection. Although the AD8012 has proprietary ESD protection circuitry, permanent damage to devices exposed to high-energy electrostatic discharges may occur. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

theory of operation

The AD8012 is a dual high speed CF amplifier that achieves new bandwidth (BW), power, distortion and signal swing capabilities. Its broad dynamic performance (including noise) is the result of a new complementary high-speed bipolar process and a new unique architectural design. Compared to the traditional single-stage complementary mirror structure (sometimes referred to as a Nelson amplifier), the AD8012 employs a dual-gain stage complementary design approach. Although dual stages have been tried before, they typically consume high power due to the folded cascade design, similar to the AD9617. This design allows quiescent or quiescent current to be ramped up to high signal or switching current sensing stages. In the time domain, the large-signal output rise/fall times and slew rates are typically controlled by the amplifier's small-signal BW and input-signal step amplitude, respectively, rather than the DC quiescent current of the gain stage (except for the input level-shift diodes Q1/Q2) . Using two stages also allows for a higher total gain-bandwidth product (GBWP) at the same power compared to one, resulting in lower signal distortion and the ability to drive heavier external loads. In addition, the second gain stage also isolates (splits) A3's input reflective load drive and resulting nonlinearity, resulting in relatively low distortion and high open-loop gain.

Overall, when high external load drive and low AC distortion are required, a dual-gain stage integrated amplifier like the AD8012 will provide lower power than traditional single-stage complementary devices. Also, since the AD8012 is a CF amplifier, the closed loop BW change with external gain change (changed RN) will be much lower compared to a VF op amp, where BW is inversely proportional to gain. Another key feature of this amplifier is its ability to operate from a single 5V supply, due in part to its ability to have a wide common-mode input and output voltage range. For 5V supply operation, the device consumes half the quiescent power (relative to a 10V supply) with little degradation in its AC and DC performance characteristics. See data sheet comparison.

DC Gain Characteristics

The combination of gain stages A1/A1B and A2/A2B provides a negative feed-forward resistor gain, as shown in Figure 4. Stage A3 is a unity gain buffer that provides external load isolation for A2. Each stage uses a symmetrical complementary design (A3 is also complementary, although not explicitly shown). This is done to reduce second-order signal distortion and total static power, as previously described. In the quasi-DC to low frequency region, the closed-loop gain relationship can be approximated as:

These fundamental relationships are common to all conventional op amps.

Line driver for HDSL applications

High Bit Rate Digital Subscriber Line (HDSL) is becoming more and more popular as a means of providing full duplex data communication over medium distances over traditional telephone twisted pairs at rates up to 1.544mbps or 2.048mbps. Traditional T1 (E1 in Europe) requires repeaters every 3,000 feet to 6,000 feet to boost signal strength and allow transmission over a distance of 12,000 feet. To achieve repeat-free transmission over this distance, the HDSL modem requires a transmission power level of 13.5dbm (assuming a line impedance of 135Ω).

HDSL uses two binary/one quaternary line codes (2B1Q). Figure 5 shows an example of a 2B1Q waveform. The digital bit stream is divided into two groups. Four analog voltages (called quaternary symbols) are used to represent the four possible combinations of two bits. These symbols are assigned the arbitrary names +3, +1, -1, and -3. The corresponding voltage levels are generated by a DAC, which is usually part of an analog front-end circuit (AFEC). Before being applied to the line, the DAC output is low-pass filtered and obtained as a sinusoidal form as shown in Figure 5. Finally, the filtered signal is applied to the line driver. The line voltages corresponding to the quaternary symbols +3, +1, -1 and -3 are 2.64 V, 0.88 V, -0.88 V and -2.64 V, respectively. This results in a peak-to-line voltage of 5.28 V.

The HDSL line driver in Figure 6 shows many elements of a classic differential line driver. A 6 volt peak-to-peak differential signal is applied to the input. The amplifier's differential gain (1+2rf/RG) is set to +2, so the resulting differential output signal is 12vp.

As is normal in telephony applications, the transformer isolates the difference amplifier from the line by current. In this case, a 1:1 turns ratio is used. In order to properly terminate the line, the output impedance of the amplifier must be set equal to the impedance of the driven line (135Ω in this case). Because the transformer has a 1:1 turns ratio, the impedance reflected from the line is equal to the line impedance of 135Ω (RREFL=RLINE/turns Ratio2). So the two 66.5 ohm resistors properly terminated the line.

The immediate effect of reverse termination is that the signal from the amplifier is halved before being applied to the line. This doubles the power the amplifier has to deliver. However, the back-end resistance also plays an important second role.

A full-duplex data transmission system like HDSL transmits data in both directions simultaneously. So the signal on the line and through the back end resistor is a combination of transmit and receive signals. A terminating resistor is used to cut off this signal and feed it to the receiving circuit. Because the receiving circuit "knows" what was being transmitted, the transmitted data can be subtracted from the digitized composite signal to reveal the received data.

Driving lines with differential signals has many advantages over single-ended drivers. Because the two outputs are always 180 degrees out of phase with respect to each other, the differential signal output is twice the magnitude of the output of the two op amps. So a differential amplifier can have 16v peak-to-peak swing even if the supply is ±5v (each op amp can swing to ±4v).

Also, the even-order harmonics (2nd, 4th, 6th, etc.) of the two single-ended outputs tend to cancel each other out, so even if the signal amplitude is doubled, the total harmonic distortion (the quadratic sum) is also reduced. This is especially advantageous in the case of second harmonics. Because it's so close to the fundamentals, filtering becomes difficult. In this application, the THD is dominated by the third harmonic, which is 65db lower than the carrier (ie, spurious free dynamic range = –65dbc).

Differential line drive also helps maintain transmit signal integrity in the presence of electromagnetic interference (EMI). EMI tends to induce itself evenly on positive and negative signal lines. Therefore, a receiver with good common mode rejection will amplify the original signal while rejecting induced (common mode) EMI.

Choosing the Right Turns Ratio for the Transformer Increasing the peak-to-peak output signal of the amplifier in the previous example, and increasing the variation of the transformer's turns ratio, can produce further enhancements to the circuit. The output signal swing of the AD8012 can increase to approximately ±3.9V before clipping occurs. This increases the peak-to-peak output of the differential amplifier to 15.6 V. Because the signal applied to the primary winding is now larger, a transformer turns ratio of 1:1 can be replaced with a (step-down) turns ratio (from amplifier to line) of about 1.3:1. This reduces the peak-to-peak primary voltage of 7.8 V to 6 V. This is the same secondary voltage as in the previous example, so the same power is delivered to the line.

However, the received signal, which is small relative to the transmitted signal, will be amplified by a factor of 1.3. Amplifying the received signal in this way improves its signal-to-noise ratio and is useful when the received signal is small compared to the signal to be transmitted.

The reflected impedance of the 135Ω line is now 228Ω (1.32 135Ω). If the lines are properly terminated, the amplifier must now drive a total load of 456Ω (114Ω + 114Ω + 228Ω), much higher than the original 270Ω load. This will reduce the drive current of the op amp by about 40%.

More importantly, however, is the reduction in dynamic power consumption, that is, the power that the amplifier must dissipate to provide load power. Increase the output signal as close to the power rails as possible to minimize the power dissipated in the amplifier.

However, there is a price to be paid in terms of increased signal distortion. Increasing the output signal of each op amp from the initial ±3 V to ±3.9 V reduces the spurious free dynamic range (SFDR) from -65 dB to -50 dB (measured at 500 kHz), even with the total load impedance Increased from 270Ω to 456Ω.

Layout Considerations

The specified high-speed performance of the AD8012 requires careful attention to board layout and component selection. Table 1 shows the recommended component values for the AD8012, and Figure 8-13 shows the recommended layout for positive gain in 8-lead SOIC and MSOP packages. Proper RF design techniques and selection of low parasitic components are mandatory.

The printed circuit board should have a ground plane covering all unused sections on the component side of the board to provide a low impedance ground path. The ground plane should be kept away from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for power supply bypassing (see Figure 7). One end should be connected to the ground plane and the other end should be within 1/8" of each power pin. An additional (4.7µF to 10µF) tantalum electrolytic capacitor should be connected in parallel.

The feedback resistor should be placed close to the inverting input pin to keep stray capacitance at this node to a minimum. Capacitors greater than 1.5pF at the inverting input will significantly affect high-speed performance when operating at low non-inverting gains.

Long signal paths (greater than 1 inch) should use stripline design techniques. They should be designed with proper system characteristic impedance and properly terminated at each end.