Features Description Low output jitter
The UCC2897A PWM controller simplifies the main and auxiliary soft stop to implement various active clamp or reset and synchronous rectification switching power supply topologies.
110-V Input Startup Function for Active Clamping, Forward Reset, Flyback The UCC2897A is a peak current mode fixed frequency high performance pulse width modulator.
The purpose of the synchronous rectifier controller includes logic and drivers to provide the auxiliary auxiliary driver P-channel auxiliary switch performance Programmable dead time (turn-on delay) A simple critical time delay planning method Active clamping operation.
Peak Current Mode Control, 0.5 V Period - Features include Internal Programmable Ramp Cycle Current Limit Compensation Circuit, Accurate DMAX Limit, and TrueDrive 8482 ; 2-A Receiver, 2-A Source Output Internally Timing Synchronous Oscillator Trimmed Internal Band gap reference capacitor. The precise line monitoring function can also program precise line UV and line OV threshold converters with respect to bulk input voltage, VIN.
Programmable slope compensation
The UCC2897A adds high performance 1 MHz synchronization with secondary hiccup mode, current sensing threshold, bidirectional internally timed capacitor oscillator, synchronization and input overvoltage protection, precision programmable maximum duty cycle, features. UCC2897A is available in 20-pin lead-free lead enamel package

Overview
The UCC2897A is a peak current mode active clamp PWM controller. It provides an easy interface to program critical moments such as soft-start, gate turn-on delay, switching period, maximum operating duty cycle, and slope compensation. Features include high voltage JFET circuitry, UVLO protection, line under/over voltage protection, pulse skipping and synchronization. The UCC8997A also has the logic and drive capability of a P-channel auxiliary switch. The VDD supply is generated by a bootstrap circuit connected to the bias winding.
Functional block diagram

Feature Description Detailed Pin Description Order This pin is internally connected to about 2.5V DC power supply. The resistor to ground (RDEL) sets the turn-on delay for the two gate drive signals of the UCC2987A controller. The delay time is the same for switching transitions between OUT off and AUX on, and when AUX is off and OUT is on. The delay time is defined in Equation 1.
Ron this pin is internally connected to about 2.5V DC power. Resistance to Ground (RON) (Pin 6) sets the charge current for the internal timing capacitor. The RON pin, combined with the ROF pin (pin 3), sets the operating frequency and maximum operating duty cycle ROFF
This pin is internally connected to about 2.5V DC power. Resistor to Ground (ROFF) (Pin 6) sets the discharge current for the internal timing capacitor. The Ron and S pins set the switching period (maximum value) and the maximum operating duty cycle (duty cycle) according to the following formulas:
The controller's internal 5-V bias rail is connected to this pin. The internal bias regulator requires a high-quality ceramic bypass capacitor (CVREF) to ground for noise filtering and to provide compensation for the regulator circuit. The recommended CVREF value is 0.22µF, and an X7R capacitor is recommended. The capacitance value of the capacitor is 0.022µF, and the maximum value is about 22µF due to the stability of the bias regulator.
The VREF pin is internally current limited and provides approximately 5mA to external circuitry. The 5-V bias is only available when the undervoltage lockout (UVLO) circuit enables operation of the UCC2897A controller. The VREF bias distribution may not be monotonic until VDD reaches 5v.
For a detailed functional description of the undervoltage lockout (UVLO) circuit, see the section of this datasheet.
SYNC This pin is a bidirectional sync terminal. If not used, this pin should remain open.
This pin provides the input of an external clock signal that synchronizes the internal oscillator of the UCC2897A controller. The sync frequency must be higher than the free running frequency of the on-board oscillator (TSYNC (1-DMAX) × TSYNC where
DMAX is set by RON and ROFF (6)
If the pulse width of the sync signal remains within these limits, the maximum duty cycle of operation remains valid, as defined by the ratio of RON and ROFF, and DMAX is the same in free-running and sync modes of operation. If the pulse width of the sync signal will exceed the (1 - dMAX) × TSYNC limit, the maximum duty cycle of operation is defined by the sync pulse width.
In standalone mode, the sync pins are driven by an internal oscillator that provides output pulses. The pulse width of the sync output does not vary with duty cycle. This signal synchronizes other PWM controllers or circuits that require a constant frequency time base.
External capacitance should be minimized on this pinout. There are no capacitors connected between SYNC and GND or PGND. For more information on synchronization of the UCC2897A, see the section of this datasheet.
Ground This pin provides the reference voltage for all small signal control and programming circuits inside the UCC2897A. Grounding layout is critical for proper operation. Large current surges from the MOSFET driver are conducted through PVDD, OUT, AUX, and PGND. To localize these surges, PVDD must bypass PGND directly. PGND currents must be electrically, capacitively, and inductively isolated from GND, with only a short trace connecting PGND to GND in a location that minimizes noise entering GND.
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CS is the direct input to the UCC2897A controller's PWM and current limit comparators. The CS pin is never directly connected to the current sense resistor (RCS) of the power converter. A small regular RC filter is required between the current sense resistor and the CS pin for proper operation of the onboard slope compensation circuit and to protect the internal discharge transistor connected to the CS pin (RF1, CF).
Slope compensation is achieved at RF by a linearly increasing current flowing out of the CS pin. The slope compensation current is only present when the gate drive signal of the converter's main power switch (OUT) is on. The internal pull-down transistor on the CS pin is activated during the discharge of the timing capacitor. This time interval is (1 – DMAX) × TSW long and represents the specified off time of the main power switch.
A resistor (RSLOPE) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation current. During the on-time of the main gate drive output (OUT), the voltage on RSLOPE is a representation of the internally timed capacitor waveform. As the timing capacitor charges, the voltage across RSLOPE also increases, producing a linearly increasing current waveform. The current provided at the CS pin for slope compensation is proportional to the current through RSLOPE.
Due to the presence of high-speed AC voltage waveforms on the RSLOPE pins, care should be taken to minimize parasitic capacitance and inductance of external circuit components connected to the RSLOPE pins.
See the section of this data sheet for details on how to program the internal slope compensation.
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FB and SS/SD interact. Control duty cycle with lower voltage value, see SS/SD description. This pin is the input of the control voltage of the pulse width modulator of the UCC2897A. The control voltage is generated by an external error amplifier by comparing the output voltage of the converter to a voltage reference and compensating the voltage regulation loop. Typically, the error amplifier is located on the secondary side of an isolated power converter, and the output voltage crosses the isolation boundary via an optocoupler. Therefore, the FB pin is usually driven by an optocoupler. As part of the feedback circuit, an external pull-up resistor on the VREF pin (pin 4) is also required for proper operation.
The control voltage is buffered internally and connected to the PWM comparator through a voltage divider to make it compatible with the signal level of the current sense circuit. The useful voltage range of the FB pin is between approximately 2.5 V and 4.5 V. Control voltages below the 2.5-V threshold result in zero duty cycle (pulse skipping), while voltages above 4.5 V result in full duty cycle (DMAX) operation.
A stainless steel/stainless steel capacitor (CSS) connected between this pin and GND (pin 6) can program the soft-start time of the power converter. The soft-start capacitor is charged by an accurate internal DC current source programmed by a RON resistor connected to pin 2. The soft-start current is defined in Equation 7.
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2 Ron (7)
This DC current charges from 0 volts to about 5 volts. Inside the UCC897A, the soft-start capacitor voltage is buffered and accompanied by the control voltage present on the FB pin (pin 9). The lower of the two voltages operates the controller's PWM engine through the voltage divider described with respect to the FB pin. Therefore, the useful control range on the SS pin is similar to that of the FB pin and is approximately between 2.5 V and 4.5 V. In the case of line under-voltage protection, in order to realize the soft-stop function, PWM follows this pin capacitor to discharge platinum group neodymium. This pin is used as a dedicated connection for all high-current circuits inside the UCC2897A. The high-current portion of the controller consists of two high-current gate drivers and various bias connections other than VREF (pin 4). The PGND (Pin 11) and GND (Pin 6) pins have no internal connection, and a low impedance external connection is also required between the two ground pins. TI recommends forming a separate ground plane for low-current setup components (RDEL, RON, ROFF, CVREF, CF, RSLOPE, CSS, and transmitters of optocouplers in feedback circuits). This single ground plane (GND) should have a single connection to the rest of the ground of the power converter (PGND), and this connection should be between pin 6 and pin 11 of the controller.
Auxiliary
AUX is the high current gate drive output of the auxiliary switch for active clamp operation of the power stage. The auxiliary output (AUX) of the UCC997A drives a P-channel device as a clamp switch, so it requires active-low operation (switch on when output is low).
Output This high current output drives an external N-channel MOSFET. The UCC2897A controller uses an active high drive signal as the main switch of the converter.
Due to the high speed and high drive current capability of these outputs (AUX, OUT), the parasitic inductance of external circuit components connected to these pins is carefully minimized. One possible way to avoid unnecessary parasitic inductance in the gate drive circuit is to place the controller close to the MOSFET and connect the output (AUX, OUT) and gate of the MOSFET device through wide overlapping traces. TI recommends connecting a 10-kΩ resistor from this pin to the PGND pin to reduce possible layout parasitics.
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The VDD rail is the primary bias for the internal high current gate driver, internal 5v bias regulator, and undervoltage lockout circuitry. To reduce switching noise on the bias rail, a high-quality ceramic capacitor (CHF) must be placed between the VDD pin and PGND (pin 11) to provide adequate filtering. The recommended CHF value is 1-µF for most applications, but this value may be affected by the characteristics of the external MOSFET transistors used in the power stage.
In addition to low-impedance high-frequency filtering, the controller's bias rail requires a large value storage capacitor (CBIAS) in parallel with CHF. The storage capacitor must provide hold-up time to operate the UCC2897A (including gate drive power requirements) during startup. In steady state operation, the controller must be powered by a bootstrap transformer winding or auxiliary bias supply. In the case of a separate auxiliary bias supply, energy storage is provided by the output capacitor of the bias supply. The capacitance value is also determined by the capacitance value connected to VREF. Capacitors on VREF and VDD should be at least 1:10.
UV This input monitors the input supply and provides accurate undervoltage lockout with user-programmable hysteresis for supplies controlled by the UCC2897A. A unique feature of the UCC2897A is the use of only one pin to implement these functions without sacrificing performance. The input voltage of the power supply is scaled to the exact 1.27-V threshold of the undervoltage lockout comparator by an external resistor divider (RIN1, RIN2 in). Once the input threshold of the line monitor is exceeded, an internal current source is connected to the LINEUV pin. The current generator is programmed by the RDEL resistor connected to pin 1 of the controller. The actual current level is shown in Equation 8.
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Second order (8)
When this current flows through RIN2 of the input divider, the undervoltage lockout hysteresis is a function of IHYST and RIN2, allowing precise programming of the hysteresis of the line monitoring circuit. When LINEUV is detected, the PWM follows the discharge of the VSS capacitor and provides a soft-stop function. The soft-start capacitor begins to discharge when the soft-start capacitor voltage reaches 2.5 V. When the soft-start capacitor resumes soft-start under the assumption that all other soft-start conditions are met, the soft-start capacitor continues to discharge until the voltage reaches 0.5 V.
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The UCC280A controller is equipped with a high voltage N-channel JFET start-up device to start operation from the converter's input supply in applications where the input voltage does not exceed the 110-V maximum rating of the start-up transistor. In these applications, the VIN pin is connected directly to the positive terminal of the input power supply. An internal JFET enable transistor provides charging current to the storage capacitor (CBIAS) connected across the VDD (Pin 14) and PGND (Pin 11) terminals. Note that when the voltage on the VDD pin exceeds approximately 12.7 V, the boot device turns off immediately and the controller has an adjustable threshold to turn on. The JFET is also always disabled when the high current gate driver switches to prevent excessive power dissipation and current through the device. For reliable startup, the load on VDD must not exceed 4 mA.
Lenov This input monitors the input power supply and provides precise overvoltage protection with user programmable hysteresis for the power supply controlled by the controller. The circuit implementation of the overvoltage protection function is the same technique used to monitor the input power rail for undervoltage lockout. This circuit achieves precise thresholds and hysteresis using only one pin. The input voltage of the power supply is precisely adjusted to the 1.27 V threshold of the overvoltage protection comparator through an external resistor divider (RIN3, RIN4 in). Once the input threshold of the line monitor is exceeded, an internal current source is connected to the LINEOV pin. The current generator is programmed by the RDEL resistor connected to pin 1 of the controller. The actual current level is shown in Equation 9.
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Second order (9)
The overvoltage protection hysteresis is a function of IHYST and RIN4 when current flows through RIN4 of the input voltage divider, allowing precise programming of the hysteresis of the line monitoring circuit.
JFET control and UVLO
The UCC2897A controller includes a high voltage JFET enable transistor. The steady-state power dissipation of the control circuit, which also includes the gate drive power loss of the two power switches of the active clamp converter, exceeds the current and thermal capacity of the device. Therefore, the JFET should only be used for the initial start-up of the control circuit and to provide power to remain powered in standby mode when the gateway driver output is not switching. Therefore, the startup device is managed by the control algorithm implemented on the UCC2897A. The timing diagram in Figure 19 illustrates the operation of the JFET enabler.

During initial power-up, the JFET turns on and charges the CBIAS and CHF capacitors connected to the VDD pin. The controller's undervoltage lockout circuit monitors the VDD pin to ensure proper biasing before operation is enabled. When the VDD voltage reaches about 12.7 V (UVLO TurNo threshold), the UVLO circuit makes the rest of the controller work. At this point, the JFET is turned off and 5V appears on the VREF terminal. The switching waveform may not appear at the gate drive output unless all other normal operating conditions are met. These conditions are:
The voltage on the CS pin is below the current limit threshold and the control voltage is above the zero duty cycle boundary (VFB > 2.5 V).
The input voltage is within the valid operating range (VVON When the controller starts running, it draws bias power from the CBIAS capacitor until the lead winding takes over (refer to Figure 25 and Figure 26). During this time, the VDD voltage drops rapidly as the JFET turns off, but the boot voltage is still insufficient to power the control circuitry. Sufficient energy must be stored in the CBIAS to prevent the bias voltage from dropping below the UVLO circuit's turn-off threshold during the start-up interval. Otherwise, the power supply will go through multiple retry attempts before steady state operation is established.
During normal operation, the bias is determined by the bootstrap bias design. The UCC997A tolerates a wide range of bias voltages between the minimum operating voltage (UVLO turn-off threshold) and the maximum operating voltage.
In applications where the power supply goes into standby in response to an external command, the controller's bias voltage must remain active in order to respond intelligently to control signals. In standby mode, the switching action is suspended for an undefined time and boot power is not available to bias the controller. In the absence of backup power, the bias voltage collapses and the controller initiates a restart sequence. To avoid this, the onboard JFET of the UCC2897A controller remains biased to VDD as long as the gate drive output remains inactive. As shown in the timing diagram in Figure 19, when FDD = 10 V, the JFET turns on and charges the CBIAS capacitor to about 12.7 V. At this point the JFET is turned off, VDD is gradually reduced to 10 V, and the process repeats. When power is enabled again, the controller is fully biased and ready to initiate a soft-start sequence. Once the gate drive pulse occurs, the JFET is turned off and the bias is provided by the bootstrap bias generator.
During power down, the situation is different as the switching continues until the VDD bias voltage is below the controller's UVLO turn-off threshold (~8 V). At this point, when the JFET device turns on and the CBIAS capacitor starts charging again, the UCC2897A turns off and turns off the 5-V bias rail and returns to start-up. If the input voltage to the converter is re-established, the UCC2897A will attempt to restart the converter.
Line Brownout Protection When the input power supply is removed, the power supply is shut down by the line brownout protection because the bootstrap winding maintains the VDD bias as long as there is switching in the power stage. As the input voltage of the power supply gradually decreases towards the line cutoff voltage, the duty cycle of the converter must compensate for the lower input voltage. At the minimum input voltage, the duty cycle is close to the maximum value (DMAX). Under these conditions, the voltage across the clamping capacitor is near its maximum value because the transformer must reset in a relatively short time. The timing diagram emphasizes that the clamp capacitor voltage may be at its maximum level in the event that the converter stops switching. Since the only load on the clamp capacitor is the power transformer, this high voltage can stay on the clamp capacitor for a long time when the converter is turned off. Due to the narrow duty cycle of the main switch and the longer on-time of the clamp switch, the high voltage present on the clamp capacitor can cause a very dangerous soft start. This can cause the power transformer to saturate during the next soft-start cycle.

To eliminate this potential hazard, the UCC2897A controller discharges the clamping capacitors during power safe shutdown. The output and auxiliary output continue to switch while the soft-start capacitor CSS slowly discharges. Since the auxiliary pulse width gradually increases with the decrease of the clamping voltage, and no high voltage is applied to the transformer for a long time, the soft-stop function is realized.

Line Overvoltage Protection When the UCC2897A controller triggers the line overvoltage protection, the gate drive signal is immediately disabled. At the same time, the slow discharge of CSS begins. The gate drive signal remains disabled while the soft-start capacitor discharges. Once VSS=0.5v, the overvoltage disappears from the power supply input and operation is resumed by periodically soft-starting the converter. Output and auxiliary stop pulses if one of the following three conditions is met:
1. VDD reaches UVLO off
2. Vehicle speed sensor voltage is lower than 2.5V
3. FB voltage is lower than 2.5V

Pulse Skipping Most PWM controllers must be able to skip a certain number of PWM pulses during output load current transients or light load conditions. In an active clamp topology, the clamp switch is driven complementary to the main switch, and the skipping of pulses applies the clamp voltage continuously to the transformer. Since operating conditions may require skipping several switching cycles on the main transistor, the transformer is likely to saturate if the auxiliary output remains on.

The UCC2897A has a bidirectional sync pin. In stand-alone operation, the sync pin is driven by the internal oscillator, which provides a square wave output of approximately 5 V amplitude. This signal synchronizes other PWM controllers or circuits that require a constant frequency time base. When the internal timing capacitor peaks, the sync output of the UCC2897A is generated. Therefore, the synchronization waveform does not coincide with the turn-on of the main gate driver output, as it is usually implemented in a PWM controller.
The operation of the oscillator and other related waveforms in free-running and synchronized modes is shown in Figure 23.
The most critical and unique feature of the synchronous waveform oscillator of the synchronous input P channel is to limit the maximum operating duty cycle of the converter, which is achieved by precisely controlling the charging and discharging intervals of the on-board timing capacitors. The maximum time of the output pin, which is also the maximum duty cycle of the active clamp converter, is limited by the charging interval of the timing capacitor. Make sure OUT is disconnected when the capacitor resets to its initial voltage level.
When synchronization is used, the rising edge of the signal terminates the charge cycle and begins the discharge of the timing capacitor. Once the timing capacitor voltage reaches the predetermined valley voltage, a new charging cycle starts automatically. This synchronization method leaves the charge and discharge slopes of the timing waveform unaffected, thereby maintaining the converter's maximum duty cycle, independent of the mode of operation.
While the sync circuit is level sensitive, the actual sync event occurs on the rising edge of the waveform, allowing the sync pulse width to vary significantly while some limitations are observed. The minimum pulse width should be sufficient to ensure reliable triggering of the internal oscillator circuit, so it is greater than about 50 nanoseconds. Another limiting factor is keeping it shorter than Equation 10.

Gate drive connection The low-side P-channel gate drive circuit involves a level shifter using capacitors and diodes, which ensures that the gate drive amplitude of the auxiliary switch is independent of the actual duty cycle of the converter.
Detailed analysis and design examples of these and many similar gate drive solutions are given in Design and Application Note SLUP169, High Speed MOSFET Gate Drive Circuits.

Boot bias

Many converters use a bootstrap circuit to generate bias power during steady-state operation. The simplicity and high efficiency of the circuit demonstrate the generality of the scheme. Typically, bias power is obtained from the main transformer by adding an additional dedicated winding to the structure. Using a flyback converter as shown in Figure 25, the bootstrap winding provides a quasi-regulated bias voltage for the primary-side control circuit. The voltage on the VDD pin is equal to the output voltage multiplied by the turns ratio between the output and the lead wire in the transformer. Because the output is regulated, so is the bias rail.
The forward converter uses the same structure, but the bootstrap winding of the main transformer cannot provide quasi-regulation. In a forward converter, the voltage across the bootstrap winding is equal to the input voltage times the turns ratio. Therefore, the bias voltage varies with the input voltage and exceeds the maximum operating voltage of the control circuit on the high line. If the power dissipation is acceptable, the linear regulator limits and regulates the bias voltage. Another possible solution for a forward converter is to generate the bias voltage from the output inductor shown in Figure 26.

Bootstrap Bias 2, Forward Example This scheme uses an adjustable output voltage across the output inductor during free rotation to create a quasi-adjustable bias for the control circuit.
Both solutions provide reliable bias power during normal operation. Note that in both cases the bias voltage is proportional to the output voltage. This characteristic of the bootstrap bias supply causes the converter to operate in hiccup mode under significant overload or short-circuit conditions because the bootstrap winding cannot keep the bias rail above the controller's undervoltage lockout threshold.
Another active circuit based biasing solution is shown on the previous page and its components are Q10, C18, R19, D10 and D12. This circuit is used in applications that limit the allowable bias capacitor size to optimize board space utilization.

Device functional mode
The UCC2897A uses a high voltage JFET to provide start-up current to the controller until a bootstrap rail is available on the VDD pin. When the VDD pin voltage exceeds the UVLO threshold, the JFET will be turned off. The device then goes into normal working mode. If the line voltage is abnormal, the unit goes into undervoltage or overvoltage mode. During light loads or load transients, if the feedback voltage FB is less than a certain threshold, the device may enter pulse skip mode

Application Information
The UCC2897A provides a highly integrated solution for active clamp PWM converters. To make the parts easier to use, TI has prepared a number of materials to demonstrate the properties of the device.
The UCC2897A family offers a highly integrated feature set and excellent accuracy to control active clamp forward or active clamp flyback power converters.
Typical Applications To take advantage of all the benefits integrated in these controllers, the following procedure simplifies setup to avoid unnecessary iterations in the design process

Power Recommendations
The VDD pin is the power supply for the device. There should be a 1µF capacitor from VDD to PGND. The VREF pin provides the supply rail for the internal logic, and it should be as close as possible to the ground of the device through a 0.1µF capacitor. The PVDD pin is the power supply pin of the power supply device and it should be passed to PGND by using a 10µF capacitor.
Layout Guidelines Connection of two grounds: GND (analog ground) and PGND (power ground). The two grounds should be connected between the IC's GND pin and the PGND pin using a net, and there should be only this connection between the two grounds.
Bypass capacitors for the VDD and VREF pins should be placed as close as possible to the device ground.
Timing configuration pins RDEL, RTON, RTOFF, and RSLOPE are tied to device ground as much as possible.
PGND should be returned as the high current output driver output and auxiliary current. The current path should be as short as possible.
Connect PVDD and VDD using 0 ohm resistors at the IC on these two pins.