feature

Average Current Sensing, Continuous Boost, Leading Edge Low Total Harmonic Distortion and Near Unity Power Factor Correction Power Factor Built-in ZVS Switch Control for Fast Response Efficiency at High Power Levels Average Line Voltage Compensation (with No Voltage Control) Current Feedback Gain Modulation Comparator Improves Noise Immunity and Provides Universal Input Operation Over Voltage Comparator Eliminates Causes of Output “Runaway” Unload UVLO, Current Limit and Soft Start Accuracy

General Instructions

The FAN4822 is designed for high power applications. The controller contains all the functions needed to achieve an average current boost PFC converter, as well as a zero voltage switching (ZVS) controller to reduce diode recovery and MOSFET conduction losses. The average current boost PFC circuit provides high power factor (>98%) and low total harmonic distortion (THD). Built-in safety features include undervoltage lockout, overvoltage protection, peak current limit and input voltage eyebrow protection. The ZVS control section drives an external ZVS MOSFET which, in combination with a diode and inductor, soft-switches the boost regulator. This technique reduces diode reverse recovery and MOSFET switching losses to reduce EMI and maximize efficiency.

Function description

The switching losses of the wide input voltage range PFC-boost converter increase sharply by 200 watts with increasing power levels. Zero-voltage switching (ZVS) technology improves the efficiency of high-power PFCs by significantly reducing the conduction losses of boost MOSFETs. ZVS is achieved by using a second, smaller MOSFET, in conjunction with the storage element (inductor) to convert the switching loss power of the boost MOSFET. The basic function of the Fan 4822 is to provide power factor correction, using a continuously regulated DC bus voltage, and average current mode control. Like Micro Linear's family of PFC/PWM controllers, the FAN4822 employs leading edge PWM to reduce system noise and allow frequency synchronization of the trailing edge PWM stage to the maximum possible DC bus voltage bandwidth. To minimize switching losses, circuits have been incorporated to control the switches of the ZVS FETs. The theory of operation diagram shows a simplified schematic of the output and control sections of a high-power PFC circuit. The diagram shows the relationship of the various waveforms in the circuit.

Q1 acts as the main switching FET and Q2 provides ZVS action. In each cycle, Q2 turns on before Q1, diverting the current in L1 from D1 into L2. The secondary current increases linearly until t2 equals the current through L1. When these currents are equal, L1 stops discharging and the current is now charging through the secondary and secondary. At time t2, the drain pipe Q1 voltage begins to drop. The voltage waveform is sinusoidal due to the interaction of L2 and the combined parasitic capacitance of D1 and Q1 (or optional ZVS capacitor CZVS). At t3, the voltage across Q1 is low enough that the controller turns off Q2 and turns on Q1.

Then Q1 acts as a common PFC switch, in boost inductor L1. During Q1 off, the energy stored in L2 is fully discharged into the boost capacitor through D2, and the value of L2 must be selected for stop mode operation. Component Select Q1 Off Because the FAN4822 uses leading edge modulation, the PFC MOSFET (Q1) always turns off the oscillator at the end of each ramp cycle. For proper operation, the internal ZVS flip-flop must be reset every cycle during which the oscillator is discharging. This is done by automatically resetting the ZVS comparator a short time after the main Q's drain voltage has reached zero (see Figure Sensing Circuit).

This sense circuit terminates the ZVS drain voltage by sensing the main Q timing to zero. It is then reset by a resistor pulled up to VCC (R6). The advantage of this circuit is that the ZVS comparator does not reset when the main Q is turned off at the end of the clock cycle. This avoids a potential improper reset of the internal ZVS flip-flop. Another problem is that the correct operation of the ZVS comparator during discontinuous mode operation (DCM) will occur at the tip of the rectified AC waveform and at light loads. Due to the nature of the voltage at the drain during DCM operation, the ZVS comparator in the main boost Q could be fooled into being forced on for the entire period. This problem can be avoided by adding a circuit that limits the maximum value within the ZVS-Q time. The Q3 chart provides this functionality.

The Q1 turn-on turn-on event consists of the current through L2 to L1 current plus the resonance event L2 and ZVS capacitance. Total events should occur at a minimum of 350-450 ns, but may be longer to increase total harmonic distortion. Setting these times equal should minimize conducted and radiated emissions.

The application diagram shows a typical application circuit ZVS PFC power supply of 500W. Full design details are included in Application Note 33, FAN4822 Power Factor Corrected Zero Voltage Resonant Switch.