Introduction
The VSP2265 is a complete mixed-signal integrated circuit for CCD signal processing with a CCD timing generator and a/D converter. The system synchronizes the master clock, HD and VD. The VSP2265 supports all signal termination required for CCD and vertical drivers, as well as externally triggered mechanical shutter and gating functions. The R drive and H drive synchronize the clock phase of the A/D converter for ideal performance. The CCD channel extracts image information from the CCD output signal by correlated double sampling (CDS). The digitally controlled gain curve is linear in decibels, ranging from -6dB to 42dB. The black level clamp circuit ensures accurate black level reference and fast black level recovery after gain changes. Can be clamped using input signal with CDS offset adjustment.
Features
The VSP2265 supports the following features:
CCD signal processing:
– Correlated Double Sampling (CDS)
– Programmable Black Level Clamp Timed Generator with R and H Drive Programmable Phase Control:
– Fine step size: 0.6 ns
– Wide step: 8 ns
Programmable Gain Amplifier (PGA): –6dB to 42dB gain range
10-bit digital data output:
– Up to 25 MHz Slew Rate – No Missing Codes Signal-to-Noise Ratio: 79dB Portable Operation:
– Low voltage: 3.0 V to 3.6 V
– Low power: 138 mW at 3.0 V, 151 mW at 20 MHz at 3.0 V and 25 MHz – Standby plus power saving mode: 34 mW – MCLK off mode: 6 mW Recommended CCDs: MN39470, MN39471, MN39472 , MN39473, MN39474 (Panasonic)

block diagram

Introduction to Theory of Operation
The VSP2265 is a high-resolution mixed-signal integrated circuit that contains key features associated with CCD signal processing in digital still cameras (DSCs). The VSP2265 integrates an analog front end (AFE) and a CCD timing generator (TG) as well as H and R drivers.
The AFE module includes a correlated double sampler (CDS), 14-bit analog-to-digital converter (ADC), digital gain amplifier, black level clamp loop, input clamp, CDS timing generator and voltage reference. The built-in TG generates not only horizontal (H-rate) timing, but also vertical (V-rate) timing for several specific CCD models. Select the CCD model and operating mode through the serial interface to generate optimized timing.
Timing Generator (TG)
TG produces H-rate timing and V-rate timing.
Figure 2-1 shows the high-speed timing block of the TG. This section generates six high-speed pulses for H-rate timing, such as R, H1/H2, SHP/SHD, and ADCCK. These high-speed pulses are generated by the master clock, which is twice as fast as the pixel rate. The serial interface sets the amount of phase adjustment for these high-speed pulses in 16 steps (R is 8 steps) with a minimum spacing of 0.6 ns (R is 0.6 ns for 4 steps, and R is 1.2 ns for 4 steps). Power mode control output driver enable/disable. The on-chip decoder calculates H clear based on the CCD model and operating mode. H1, H2 and R can directly drive the CCD. The ADCCLK, SHP, SHD, R, H1, and H2 pulses can be selected to be internally generated or supplied externally.

An on-chip V-rate timing generator generates all the signals required for a specific CCD image sensor. The TG contains line counters and pixel counters used to generate V rate timing. Figure 2-2 is a block diagram of the line and pixel counter circuit. A maximum of 2047 lines and 4095 pixels per line are supported on the time scale.
VSP2265 Line and Pixel Counter Block Diagram

V-rate timing generator block diagram. 1 hour before the CCD readout (horizontal line), the user must complete the serial data transfer, and the data must be loaded into a register containing information on the CCD model, operating mode, integration time, and electronic zoom area. Just before the CCD readout, the information in the registers is automatically provided to the decoder, which uses the line counter and pixel counter data to generate the V rate signal. Not only signals for CCDs, but also gated light control signals are supported. CPOB, CLPD and PBLK can select internal power generation mode or external power supply mode

Analog front end
Simplified AFE block diagram of the VSP2265. The AFE circuit includes a correlated double sampler (CDS), 14-bit analog-to-digital converter (ADC), digital gain amplifier, black level clamp loop, input clamp, CDS timing generator and voltage reference. An off-chip emitter follower buffer or preamp register is required between the CCD output and the VSP2265
VSP2265 AFE Simplified Block Diagram

Correlated Double Sampler (CDS)
The output signal of a CCD image sensor is sampled twice in a pixel period: once in the reference interval and once in the data interval. Subtract these two samples to extract the video information of the pixel, remove the low frequency noise kTC and CCD reset noise.
CDS is driven by off-chip coupling capacitor CIN. (A 0.1-µF capacitor is recommended for CIN). AC coupling is strongly recommended because the DC level of the CCD output signal is often too high (a few volts) for the CDS to work properly. A suitable common mode voltage for CDS is around 0.5v–1.5v. Reference level sampling is performed while the SHP is active, and the voltage level is held on the sampling capacitor C1 on the trailing edge of the SHP. Data level sampling occurs when the SHD is active, and the voltage level is held on the sampling capacitor C2 on the trailing edge of the SHD. The two levels are then subtracted by a switched capacitor amplifier. The off-chip emitter follower or equivalent buffer must be able to drive more than 10 pF because the 10 pF sampling capacitor is visible at the input. (There is usually a small amount of pF of additional stray capacitance) The analog input signal range of the VSP2265 is about 1vp-p.

The input clip buffers the CCD output capacitively coupled to the VSP2265. Input clamping restores the DC component of the input signal, which is lost due to AC coupling, and establishes the desired DC bias point for CDS. Block diagram of the input clamp. During the dummy pixel interval, the input level is clamped to the internal reference voltage CM (1.5v). More specifically, the clamping function becomes active when both CLPD and SHP are active.
Bit A/D Converter
The ADC uses a fully differential pipeline structure with 1.5 bits per stage, making it ideal for low power, low voltage and high speed applications. The ADC provides 14-bit resolution for the entire scale. The 1.5-bit-per-stage structure of the ADC facilitates better linearity at smaller signal levels. Improved linearity occurs because large linearity errors tend to occur at specific points of full scale, and for signal levels below any such specific point, linearity improves.
Digital Programmable Gain Amplifier (DPGA)
Characteristics of DPGA gain. The DPGA offers a gain range of -6dB to 42dB, which is linear in decibels. Gain is controlled by a digital code with 10-bit resolution and can be set via the serial interface; see the Serial Interface Timing Specification (Section 3) for details. The default value of the gain control code is 128 (PGA gain = 0 dB).
After power-on, the gain control value is pending. Therefore, it must be set to an appropriate value using the serial interface, or reset to default by hitting the SYSRST terminal.

AFE working hours
The CDS and ADC are operated by derived timing clocks generated by the SHP, SHD and their internal on-chip timing generators. The DPGA output registers and decoder are operated by ADCCK. The digital output data is synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and output data is shown in the VSP2265 timing specification. CPOB activates the black level clamp cycle during OB pixel intervals and CLPD activates input clamp during dummy pixel intervals.

Black level clamp loop and 10-bit DAC
In order to correctly extract video information, the CCD signal must be referenced to a recognized black level. The VSP2265 has an auto-zero loop (calibration loop) to establish black levels using the CCD optical black (OB) pixels. Figure 2-8 shows a block diagram of this loop. The input signal level from the OB pixel is recognized as the true black level, and the loop is closed during this period (actually during CPOB=active). When the auto-zero loop is closed, the difference between the ADC output codes is evaluated and applied to the decoder, which then controls the 10-bit current DAC. The current DAC can charge or discharge an external capacitor at COB, depending on the sign of the code difference. The loop adjusts the voltage at the COB, which sets the offset of the CDS so that the code difference is zero. Therefore, the ADC output code converges to the black level during CPOB=ACTIVE and maintains the black level derived from the OB pixels after the loop has converged. CPOB performs OB clamping of both channels simultaneously.
To determine the loop time constant, an off-chip capacitor is required and should be connected to the COB terminal. The time constant T is calculated using the following formula:
where C is the value of the capacitor connected to C OB and IMIN is the minimum current (0.15µA) that controls the DAC in the OB level clamp loop, 0.15µA is equivalent to 1lsb of the DAC output current. When C is 0.1 μF, the time constant T of the ADC output code is 40.7 μs, from 0 LSB to 1543 LSB (the convergence curve becomes exponential).
For output codes above 1543 LSB, the current DAC injects a constant (maximum) current into the capacitor and the convergence curve becomes linear. The slew rate SR is calculated using the following formula.
where C is the value of the capacitor connected to COB. IMAX is the maximum current (153 μA) that controls the DAC in the OB level clamp loop, and 153 μA is equivalent to 1023 LSBs of the DAC output current.
In general, high-speed OB level clamping will generate clamping noise. However, noise can be reduced by increasing C. A large C, on the other hand, takes longer to recover from power saving mode, or as soon as power is turned on. Therefore, 0.1µF to 0.22µF is considered a reasonable value for C. If the application environment requires values outside this range, careful adjustment by trial and error is recommended.
The OB clamp (base seat) is programmable through the serial interface; see the Serial Interface Timing Specification (Section 3) for details. See also the Serial Interface Timing Specifications section for the relationship between input codes and OB clamp levels.
The black level clamp loop removes not only the black level offset of the CCD, but also the offset of the VSP2265 CDS and the ADC itself.
Pre-Blanking and Data Delay
The VSP2265 has a pre-blanking function. When PBLK = low, the digital outputs all go to zero at the ninth rising edge of ADCCK, starting counting from when PBLK goes low to accommodate the clock delay of the VSP2265.
The data latency for this device is seven clock cycles. The digital output data is output on the rising edge of ADCCK with a delay of seven clock cycles.
Some CCDs have large transient output signals during the blanking interval. If the input voltage is 0.3 V above the supply rails or below the ground rails, the protection diodes turn on, limiting the input voltage. Such high swing signals can cause equipment damage to the VSP2265 and should be avoided

Power Saving Mode To save power, the VSP2265 can be put into standby plus power saving mode through serial interface commands. In this mode, by configuring the serial interface command, all function blocks are disabled, the A/D outputs are all reset to zero, and the TG output goes into a high or low state. Current consumption drops to 34mA. Since all bypass capacitors discharge in this mode, it takes a considerable amount of time (typically 200-300 ms) to recover from standby plus power save mode.
Additional output delay control
VSP2265 can control the delay time of output data through serial interface setting register. In some cases, the transformation of output data can affect simulation performance. Usually, this is avoided by adjusting the timing of ADCCK. In cases where ADCCK timing cannot be adjusted, additional output delay control is effective in reducing the effect of transient noise. See the Serial Interface Timing Specification (Section 3) for details.
All reference voltages and bias currents used on voltage reference devices are generated by internal bandgap circuits.
There are mainly three reference voltages used by CDS and ADC: REFP (1.75v), REFN (1.25v) and CM (1.5v). REFP and REFN are buffered on-chip. CM is derived as the intermediate voltage of the resistor chain connecting REFP and REFN internally. The ADC full-scale range is determined by twice the voltage difference between REFP and REFN.
REFP, REFN, and CM should be severely decoupled with appropriate capacitors.

Working Mode Field Mode allows the summation of vertically adjacent pixels.
Frame mode supports per pixel output.
×2 Velocity mode enables output interval lines.
The ×2 monitor mode provides 2×8 lines or 2×10 lines of output for CCDs 2A or 2B, respectively.
Field mode, frame mode and x2 speed mode interleave between even/odd frames.

Function The long integration function stops the CCD readout (CH1, CH2, CH3, CH4 pulse) at the end of one frame according to the definition of the serial data command.
The power saving function stops all clocks and holds them high or low by serial data commands.
The strobe function allows external strobe operation to synchronize electronic shutter timing via serial data commands.
The electronic zoom function enables electronic zoom to select consecutive lines based on serial data commands.
The electronic shutter function enables electronic shutter operation via serial data commands.
, Substation 1/4 step function allows to select sub-pulse position from four points on a line by serial data command.
, TG vertical rate operation, 1 field mode operation, 1.1 operation outline
The horizontal output of the CCD is produced by summing the pixels that are vertically adjacent to each other and repeating the summation for each CCD pixel column in turn. Odd or even fields are optional.
, 1.2 Operation sequence one. Set serial data address 000100 bits 6–5=00.
, Odd/even numbers are defined by the relationship between VD and HD or by serial address 000100 bits 8–7.

Frame Mode Operation
2.1 Running Outline
The horizontal output of the CCD is produced by vertically reading out individual pixels at 2-pixel intervals and repeating the readout for each pixel column in succession. Odd or even fields are optional.
2.2 Operation sequence one. Set serial data address 000100 bits 6–5=01.
Odd/even numbers are defined by the relationship of VD and HD or by serial address 000100 bits 8–7.

The timing of readout of the running outline of the still function is selected by the TRG input. A smear dump operation synchronized with the mechanical shutter is available.
Sub-outputs are controlled by serial data commands and external TRG signals.
The SUBSW level follows quiescent mode conditions. When using a mechanical shutter, SUBSW can be used for the sub-bias control circuit. It is recommended to set the switch position of SUBW after the mechanical shutter is closed.
Operation sequence one. Set the serial data address 000101. Input bit 2=H and set to quiescent mode. Select trigger signal EDGSL bit 3=L (VD) or bit 3=H (TRG). Select sub output STLSUB bit 4=L (for TRG input) or bit 4=H (for serial data input).
(In this case, the sub output is defined by the TRG input. To use serial data instructions, the integration time is defined by ES 000111, which can be done after step 2 below.)
2. Input a pulse to SLOAD and send serial data.
three. Set serial data address 001010. Enter STVV data (bits 0–5) for wavelet rise time definition. Data is stored in the register 1h before the read operation. Upon entering the quiescent mode, a sub-output is generated every H during the horizontal scan time before the readout operation, and the charges are depleted.
Four. Input the falling edge signal of TRG if necessary. The falling edge of TRG is latched by the internal HD_flg. After the next horizontal blank, the sub output goes high and charge integration begins. See Note 1.
5. Input TRG rising edge or VD signal. SUBSW goes high at the location defined by the serial data. The SUBSW switching position is determined by counting the number of HD pulses following the rising edge of TRG or VD. Apply a vertical high-speed pulse, which is greater than the line number of a field.
6. Enter serial data into bit 3 = L at address 000101 and release the flip-flop select function during the vertical high-speed pulse operation initiated in step 5.
Number 7. After one field of CCD output signal is completed, input a VD pulse to keep SUBSW high.
8. Enter serial data for address 000101 and bit 2 = L to exit from quiescent mode.
No.9. After completing a CCD output signal field, a VD pulse is input. Submarine falls on the next HD rising edge.
Note: 1. In this mode, the mechanical shutter opens when the TRG input is low. 2. Do not use the electronic shutter in still mode when SUBW is high. three. For a VD-to-VD interval, more than 90 HD-to-HD interval counts are required.

Gating (STO output) function operation outline
The STO output is initiated by a serial data command, including the STO signal position and duration.
Operation sequence one. Set data bit 6=H for the STO (strobe) rising point instruction at address 001010. See Note 1.
2. Input a pulse to SLOAD and transfer serial data.
three. Data bits 0–9 are set at address 000110 for the STO (strobe) rising point instruction. In this case, use the binary code of data ST[9:0] starting from the rising edge of HD (10t), which is 2H after the readout pulse. The data range of ST is 0≤n1≤A-2, where A is the number of HD between VD-VD. See Note 3.
Four. Input a pulse to SLOAD and transfer serial data.
5. Set data bits 5–9 for the SWT duration instruction at address 000101. In this case, the binary code of data SWT[9:5] is used, starting from the rising edge of STO (10t). See Note 3.
6. Input a pulse to SLOAD and transfer serial data. Data is stored in the resistors 1 hour before the readout operation. STO goes high at the point determined by the serial data command. STO goes low when the duration of STO high exceeds SWT between two HD pulses. See Note 2.
Note: 1. The gating function can be used in normal mode and quiescent mode. So stroboscopic surgery is useful for preventing red eye. 2. The rise time and fall time of STO is 10t.3. Adjust the storage location and width so that the storage is 2 HD lower before the readout operation

Electronic zoom function operation outline Vertical CCD transmission can realize vertical image extraction.
The horizontal image extraction and scaling process requires signal processing outside the device.
This mode allows high-speed image output in a limited area.
Operation sequence one. Set the serial data address 000101. At the same time, input data bit 1=H to set the electronic zoom mode. The number of transfer stages is set using the code in binary address 001011 and data bits 0–9. See Note 4 for the range of data. See Notes 1-5.
2. Input a pulse to SLOAD and transfer serial data. High-speed vertical transfer of V1 to V4 outputs is achieved according to serial data-level instructions. After high-speed transmission, standard vertical transmission of V1 to V4 is performed for each H. In the next VD, the high-speed vertical transfer of V1 to V4 is output for about one field. See Note 2.
Note: 1. This mode cannot be combined with still mode. 2. In the electronic zoom function, the user's instruction only involves vertical high-speed transfer after the readout operation. Before the readout operation, the number of vertical high-speed transfers per CCD model is fixed. three. Signal performance is not guaranteed in 1 field after switching to and releasing from this mode. Four. The transmission level is set as follows: [2A CCD] 0≤n≤640 levels (parity selects 0.5 level pitch), note that n must be divided by 2. [2B CCD] 0≤n≤610 levels (parity selection can provide 0.5 level spacing) Note that n must be divided by 5. 5. The interval between VD to VD must be greater than 90 HD.

TG pixel rate operation

High-speed pulse adjustment For high-speed pulses, the CCD signal sampling time is adjustable (see serial data addresses from 001100 to 010111). The default value is set to the default timing value
R: The standard reset duration is 25% of the period.
SHP: Based on 3 ns CCD signal delay, standard rise point is 50% of cycle. Actual latency depends on the system.
SHD: Standard rise point is 100% period, based on 3 ns CCD signal delay. Actual latency depends on the system.
H1: The standard duration is 50% of the period.
H1 and H2 are complementary. The intersection of the rising edge of H1 and the falling edge of H2 should be higher than VDD/2.
H2: Standard duration is 50% of the cycle.
ADCCK: Based on a 3 ns CCD signal delay, the standard rise and fall points are 25% and 75% of the period, respectively.

H1, H2, R clocks can use corresponding I/O terminals for signal monitoring and signal input (H1, H2, R).

SHP, SHD, PBLK, CLPOB, CLPDM clocks can use the corresponding I/O terminals for signal monitoring and signal input to SHP, SHD, PBLK, CLPOB, and CLPDM.

Absolute Maximum Ratings for Electrical Characteristics Over Operating Free Air Temperature Range (unless otherwise stated)
Supply voltage, VDD 4 V
Power supply voltage difference, VDD±0.1v.
Ground voltage difference, VSS±0.1v.
Digital Input Voltage –0.3 V to (VDD+0.3 V).
Analog Input Voltage –0.3 V to (VCC + 0.3 V).
Input current (any terminal except power supply) ±10mA.
Ambient temperature under bias –25°C to 85°C.
Storage temperature –55°C to 125°C.
Junction temperature 150°C.
Package temperature (infrared reflow, peak) 250°C