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Logically 4-Mbit Ferroelectric Random Access Memory (F-RAM) organized as 256K x 16 10064 ; configured as 512K x 8 using UB and LB ❐ High endurance 100 trillion (1014) read/write ❐ 151 years of data retention Period (see Data Retention and Endurance Table) NoDelay 8482 ; Write Page Mode Runs to 25 ns Cycle Time Advanced High Reliability Ferroelectric Process SRAM Compatible Industry Standard 256K x 16 SRAM Pins 55 ns Access Time, 110 ns Cycle Time Advanced Features Software Programmable Block Write Protection Superior to Battery Backed SRAM Modules No Battery Issues Monolithic Reliability True Surface Mount Solution with No Rework Steps Suitable for Moisture, Shock and Vibration Low Power Consumption Active Current 8 mA (typ value) Standby current 90µA (typ) Low voltage operation: VDD=2.7 V to 3.6 V Industrial temperature: –40°C to +85°C? ? 48-Ball Fine Pitch Ball Grid Array (FBGA) Package Compliant with Restriction of Hazardous Substances (RoHS)

Functional Overview

FM22LD16 is a 256K×16 non-volatile memory, which can read and write similar to standard SRAM. Ferroelectric random number access memory, or F-RAM, is non-volatile, which means that data is retained after a power outage. It has been battery-backed SRAM (BBRAM) for 151 years while eliminating reliability issues, functional flaws and system design complexity. Fast write timing and high write endurance make F-RAM superior to other types of memory. The operation of the FM22LD16 is similar to that of other RAM devices, so it can be used as a standard SRAM in the system. Read and write cycles can be triggered by CE or by changing the address. F-RAM memory is a non-volatile process due to its unique ferroelectric memory. These features make the FM22LD16 ideal for applications requiring frequent or fast non-volatile memory writes. The FM22LD16 includes a low voltage monitor to access the memory array when VDD is below the VDD minimum value. The memory is protected against unintentional access and data corruption in this case. The device also has software-controlled write protection. The memory array is divided into 8 uniform blocks, each of which can be individually write-protected. The device is available in a 48-ball FBGA package. Equipment specifications are guaranteed over the industrial temperature range of -40°C to +85°C.

Device Operation The FM22LD16 is logically a word wide F-RAM memory organized as 262144 x 16 and uses an industry standard parallel interface. All data written to the component is immediately non-volatile. The device provides page mode operation, providing high-speed access to addresses in pages (rows). Access to other pages requires CE to translate low or high address (A17-A2) changes. See the functional truth table on page 17 for a complete description of the read and write modes. Memory Operations Users access 262,144 memory locations, each with 16 data bits via a parallel interface. The F-RAM array is organized into eight blocks, each with 8192 rows. Four columns per row allow quick access to locations in page mode. When the initial address is latched by the falling edge of CE, there is no need to access subsequent column locations to toggle CE. When the CE is de-high voltage, the pre-charge operation begins. Enter now. The WE pin operation must be toggled on every write. Write data is stored in an immediate array of non-volatile memory, a feature unique to F-RAM called Nordley writes. READ OPERATIONS A read operation begins with the falling edge of CE. A falling edge of CE causes the address to be latched and initiates a memory read cycle if we are high. Data is available to the bus after the access time. When the access is done when the address is locked, a new random location access (different row) may start while CE is still low. The minimum random address cycle time is tRC. Note that, unlike SRAM, the CE boot access time of the FM22LD16 is faster than the address access time. The FM22LD16 will drive the data bus byte enable (UB, LB) asserted low when run experience and at least one run experience. Upper data bytes are driven when UB is low, and low data bytes are driven when LB is low. If OE is asserted after the memory access time, the data bus will be driven with valid data. If operational experience is to assert before completing the memory access, the data bus will not be driven until valid data is available. This function will minimize invalidation by eliminating data driven to the bus. High when run experience is de-evaluated, the data bus will remain in the HI-Z state.

Write operation In the FM22LD16, the interval between writing and reading is the same. The FM22LD16 supports both CE and WE controlled write cycles. In both cases, addresses A17–A2 are locked to the chief engineer. In a CE-controlled write operation, the WE signal starts a memory cycle. That is, when CE is down, we are low. In this case, the device starts the memory cycle with a write. No matter what state this is in, the FM22LD16 will not drive the data bus as long as we are low when CE is de-assets high. In our controlled write, the memory cycle starts from the falling edge of CE. Our signal sometimes falls off later. Therefore, a store cycle begins with a read. Data will drive the bus if it is running low; however, when we are asserted low. We control the write timing. A write access to the array starts the memory loop. Write accesses are on the rising edge of US or CE, whichever comes first. Effective handwriting operations require users to meet access time specifications before we or the Chief Executive leave. Data setup time is indicated on write access (rising edge of WE or CE). Unlike other non-volatile memory technologies, it has no write latency to F-RAM.

Because the underlying memory is the same, the user experience does not experience a delay on the bus. The entire memory operation happens in a single bus cycle. Data polling, a technique used in eeprom does not require determining whether a write is complete. Page Mode Operation The F-RAM array is organized into eight blocks of 8192 rows each. There are four column address locations per row. Address inputs A1–A0 define the column address to be accessed. An access can start from any column address and other columns can be accessed without toggling the CE pin. For fast access reads, the column address inputs A1–A0 can be changed to the new value after the first data byte is driven onto the bus. A new data byte occurs no later than tAAP, less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. When CE is low, subsequent write pulses and new column addresses provide page-mode write access. Precharge Operation A precharge operation is an internal condition where the memory state is ready for a new access. Precharge is initiated by the user by driving the CE signal high. It must be left high for at least the minimum precharge time, tPC. Precharge can also be activated by changing the address above, A17–A2. The current row is visiting the new rowing boat. The device automatically detects a high-order address change and begins a precharge operation. The new address is locked, and the new read data is valid for access time within tAA address;. A similar sequence occurs for write cycles, where the speed random addresses can be tRC and tWC, respectively.

The software write-protected 256K×16 address space is divided into 8 sectors (blocks) of 32K×16 each. Each sector can be individually software write protected and the settings are non-volatile. A unique address and command sequence invokes write-protected mode. To modify write protection, the system host must issue six read commands, three write commands, and one final read command. A specific sequence of FM22LD16 read addresses must be provided to access write protected mode. Following the read address sequence, the host must write a data byte specifying the desired protection state for each sector. To confirm this then the system must write the complement of the guard byte immediately after the guard byte. Any errors that occur including reading addresses in the wrong order, issuing a seventh read address, or failing to supplement the protection value will remain write-protected. The write protection state machine monitors all addresses for no action until this particular read/write sequence occurs. During the address sequence, each read will occur as a valid operation and the data at the corresponding address will be driven to the data bus. Any address that is out of sequence will cause the software protection state machine to restart. After the address sequence is complete, the next operation must be a write cycle. The lower data bytes contain the write protection settings. This value is not written to the memory array, so the address is not a concern. Rather, it must be a supplement to the data set for protection before the next cycle. If the complement is correct, the write protection setting will be adjusted. Otherwise, the process aborts and the address sequence starts over. Data value addresses written after the correct 6 will not be entered into memory. The protection data byte consists of 8 bits, each bit is associated with the write protection status of a sector. Data bytes must be driven to the lower 8 bits of the data bus, DQ7–DQ0. Setting the bit written to "1" protects the corresponding sector; "0" enables writing for that sector. The following table shows the write protection sector settings with corresponding bits that control write protection.

SRAM Insert Replacement FM22LD16 is designed as standard asynchronous SRAM. The device does not need the CE to switch for each new address. CE may remain low indefinitely. When CE is low, the device automatically detects the address change and starts a new access. This feature allows CE to be grounded like you would with SRAM. It also allows page mode to run at speeds up to 40 MHz. The diagram shows a pull-up resistor on CE that will keep the pin high during power cycling, assuming the MCU/MPU pin is tri-stated in a reset condition. The pull-up resistor value should be chosen to ensure that the CE pin trace VDD is high enough, so the current drawn when CE is low is an issue. When CE is low and VDD=3.3V Note that if CE is tied to ground, the user must ensure that we are not low during a power-up or power-down event. If both CE and US are during low power cycles, the data will be corrupted. Figure 6 shows that we have a pull-up resistor on, during power cycling, assuming the MCU/MPU pins are in a reset condition. The pull-up resistor value should be chosen to ensure that the WE pin tracks VDD value is high enough so that when we are low, current consumption is not an issue. 10-k When we are at low voltage and VDD=3.3V, the resistor dissipates 330uA. Note that if CE is tied to ground, the user will forgo executing the software write protect sequence. For applications that require the lowest power consumption CE signals should only be active (low) during memory accesses. When CE is low, even address and control signals are static. The device does not exceed the maximum standby current when the CE value is high. CE toggling low on every address access is perfectly acceptable in the FM22LD16. The UB and LB byte select pins are active for both read and write cycles. They can be used to connect the device as 512K x 8 memory. The upper and lower data bytes can be bound and controlled together with the byte selection. A single byte enable or the next higher address line A18 is available from the system processor.

Note that if CE is tied to ground, the user must ensure that we are not low during a power-up or power-down event. If both CE and US are during low power cycles, the data will be corrupted. The diagram shows that we have a pull-up resistor on it, during power cycling, assuming the MCU/MPU pins are in a reset condition. The pull-up resistor value should be chosen to ensure that the WE pin tracks VDD value is high enough so that when we are low, current consumption is not an issue. 10-k When we are at low voltage and VDD=3.3V, the resistor dissipates 330uA.

Note that if CE is tied to ground, the user will forgo executing the software write protect sequence. For applications that require the lowest power consumption CE signals should only be active (low) during memory accesses. When CE is low, even address and control signals are static. The device does not exceed the maximum standby current when the CE value is high. CE toggling low on every address access is perfectly acceptable in the FM22LD16. The UB and LB byte select pins are active for both read and write cycles. They can be used to connect the device as 512K x 8 memory. The upper and lower data bytes can be bound and controlled together with the byte selection. A single byte enable or the next higher address line A18 is available from the system processor.