feature

Complete 16-bit converter with reference and clock; 60.003% maximum nonlinearity; no missing codes over temperature over 14 bits; fast conversion; 17 ms to 16 bits ( AD1376 ); 10 ms to 16 bits (AD1377); short cycle capability ; Adjustable clock rate; Parallel and serial outputs; Low power: 645 mW typical (AD1376); 585 mW typical (AD1377); industry standard pins.

Product Description

The AD1376/AD1377 are high-resolution 16-bit analog-to-digital converters with internal reference, clock, and laser-trimmed thin-film applied resistors. They are packaged in a compact 32-pin, ceramic dummy hermetic (hermetic) dual in-line package (DIP). Thin-film scaling resistors provide bipolar input ranges of ±2.5 V, ±5 V, ±10 V and unipolar input ranges of 0 V to +5 V, 0 V to +10 V, and 0 V to +20 V. The digital output data provides corresponding clock and status outputs in parallel and serial. All digital inputs and outputs are TTL compatible.

application

The AD1376/AD1377 are ideal for high resolution applications requiring moderate speed and high accuracy. Stability over the commercial (0°C to +70°C) temperature range (For extended temperature range, the pin-compatible AD1378 is recommended.) Typical applications include precision measurement and analysis instruments for medical and industrial robotics, automatic test equipment (ATE) and multi-channel data acquisition systems, servo control systems, or anywhere a wide dynamic range is required for dedicated monolithic DACs and laser trimmed thin film resistors guarantee maximum value . Non-linearity is ±0 003% (1/2 LSB14). The converter can be short-cycle for faster conversion times – 15 microseconds to 14 bits for the AD1376, or 8 microseconds to 14 bits for the AD1377.

Product Highlights

1. The AD1376/AD1377 provide 16-bit resolution at ±25°C with a maximum linearity error of ±0.003% (1/2 LSB14).

2. The AD1376 conversion time is 14 microseconds (typical), the short cycle is 14 bits, and 16 microseconds to 16 bits.

3. The AD1377 conversion time is 8 microseconds (typ), the short cycle is 14 bits, and 9 microseconds to 16 bits.

4. There are two binary codes on the digital output. They are the complementary straight binary voltage range for unipolar input and the COB (complementary offset binary) bipolar input range. Complementary Two's Complement (CTC) encoding is available by inverting pin 1 (MSB).

5. AD1376 and AD1377 include internal reference and clock, with external clock rate adjustment pins, and serial and parallel digital outputs.

Instructions

Upon receiving a conversion start command, the AD1376/AD1377 convert the voltage at its analog input to an equivalent 16-bit binary number. This conversion is done as follows: The 16-bit successive approximation register (SAR) has its 16-bit output, connected both to the device bit output pins and to the corresponding bit input of the feedback DAC. The analog input is compared to the feedback DAC output continuously, one at a time (MSB first, LSB last). The decision to reserve or reject each bit is then made at the end of each bit comparison period, depending on the state of the comparator at the time.

Gain adjustment

The gain adjustment circuit consists of a 100 ppm/°C potentiometer connected to the gain adjustment pin 29 through a 300 kΩ resistor with its slider connected to ±VS as shown in Figure 4.

Pin 27 (bias adjustment) and pin 29 (gain adjustment) may remain open if external trimming is not required.

offset adjustment

The zeroing circuit consists of a 100 ppm/°C potentiometer connected through a 1.8 MΩ resistor to comparator input pin 27 for all ranges, with its slider connected through a ±VS. As shown in Figure 5, the tolerance of this fixed resistor is not critical, the carbon composition type is usually sufficient. Using a carbon composition resistor, the temperature is –1200 ppm/°C, and the worst case offset temperature is 32 LSB14 361 ppm/LSB14 3 1200 ppm/°C = 2.3 ppm/°C of FSR, if the offset trim pot is set at its Adjust either end of the range. Since the maximum offset adjustment required is typically no greater than ±16 LSB14, the use of carbon composition offset summing resistors typically contributes no more than 1 ppm/°C of FSR offset TEMPCO.

As shown in Figure 6, if metal film resistors are used (tempco < 100ppm/°C), an alternative bias adjustment circuit for biasing tempco can be ignored.

In either regulation circuit, the fixed resistor connected to pin 27 should be close to this pin to keep the pin connections shorted. The comparator input pin 27 is quite sensitive to external noise sensors and should be protected with an analog common.

opportunity

The timing diagram is shown in Figure 7. Receipt of a conversion start signal sets a status flag to indicate that a conversion is in progress. This in turn removes the inhibition applied to the gated clock, allowing it to run for 17 cycles. All SAR parallel bits, status flip-flops, and gated clock inhibit signals are initialized on the trailing edge of the conversion start signal. At time t0, B1 is reset and B2–B16 are set unconditionally. At t1, bit 1 decides (holds) and bit 2 is unconditionally reset. This sequence continues until a bit 16 (LSB) decision (keep) is made at t16. The status flag is reset, indicating that the conversion is complete and the parallel output data is valid. Resetting the status flag will restore the gated clock inhibit signal, forcing the clock output to a low logic "0" state. Note that the clock is kept low until the next conversion. The corresponding parallel data bits become valid on the same positive clock edge.

Digital output data

Parallel and serial data from TTL memory registers are in negative true form (logic "1" = 0 V, logic "0" = 2.4 V). The parallel data output encoding is complementary binary for unipolar ranges and complementary offset binary for bipolar ranges. Parallel data is valid at least 20 ns before the status flag returns to a logic "0", allowing parallel data transfers to be clocked on a "1" to "0" transition of the status flag (see Figure 8).

Serial data encoding is complementary binary encoding for unipolar input ranges and complementary offset binary encoding for bipolar input ranges. Serial output is bitwise (1M4SB, then LSB) in NRZ (non-return-to-zero) format. Serial and parallel data outputs change state on positive clock edges. Serial data is guaranteed to be valid 120 ns after the rising clock edge, allowing serial data to go directly to the receive register on the negative-going clock edge, as shown in Figure 9. There are 17 negative clock edges throughout the 16-bit conversion cycle. The first negative edge shifts an invalid bit into the register, and the register is shifted out on the last negative clock edge.

All serial data bits will be transmitted correctly and appear in the receive shift register location at the end of the conversion cycle.

short cycle input

The short period input Pin 32 allows the timing period shown in Figure 7 to terminate after any number of desired bits have been converted, allowing for slightly shorter conversion times in applications that do not require full 16-bit resolution. When 10-bit resolution is required, pin 32 is connected to the 11th bit output pin 11. Then, the conversion cycle is terminated and the status flag is reset after bit 10 is determined (timing diagram in Figure 7). Table I summarizes the short-cycle connections and associated 8, 10, 12, 13, 14, and 15-bit conversion times for a 1.6MHz clock (AD1377) or 933kHz (AD1376).

input scaling

To take advantage of the maximum signal resolution of the A/D converter, the ADC (ADC) input should be as close as possible to the maximum input signal range. Connect the input signals as shown in Table 2. See Figure 10 for circuit details.

NOTE: Pin 27 is very sensitive to noise and should be protected by the analog common.

Calibration (14-bit resolution example)

External zero and gain adjustment potentiometers, connected as shown in Figures 4 and 5, are used for device calibration. To prevent interaction between these two adjustments, always adjust the zero first, then adjust the gain. The zero point is adjusted by the analog input near the most negative end of the analog range (0 for unipolar input range, –FS for bipolar input range). Gain is adjusted through the analog input near the positive end of the analog range.

The 0 V to +10 V range sets the analog input to +1 LSB14=0.00061 V. Zero the digital output to 11111111110.

The zero point is now calibrated. Set the analog input to +FSR–2 LSB=+9.99878 V. Adjust the gain of the 00000000000001 digital output code; now calibrate the full scale (gain). Half-Scale Calibration Check: Set the analog input to +5.00000V; the digital output code should be 011111111111.

The –10 V to +10 V range sets the analog input to 9.99878 V; adjusts zero for the 111111111 0 digital output (complementary offset binary) code. Set the analog input to 9.99756 V; adjust the gain of the 00000000000001 digital output (complementary offset binary) code. The half-scale calibration check sets the analog input to 0.00000V; the digital output (complementary offset binary) code should be 011111111111.

Other scope

Typical digital encodings for the 0 V to +10 V and -10 V to +10 V ranges are given above. Coding relationships and calibration points for the 0 V to +5 V, -2.5 V to +2.5 V, and -5 V to +5 V ranges can be achieved by scaling the 0 V to +10 V and -10 V to +10 V ranges The corresponding code equivalence values listed in halve are used to find the range, as shown in Table 3.

Using the static adjustment procedure described above, zero and full-scale calibration can be achieved with an accuracy of approximately ±1/2 LSB. By adding a small sine or triangle wave voltage to the signal applied to the analog input, the output can be cycled through each calibration code of interest to more accurately determine the center (or endpoint) of each discrete quantization level. A detailed description of this dynamic calibration technique can be found in "Handbook of Analog to Digital Conversion" edited by DH Sheingold, Prentice Hall, Inc., 1986.

Grounding, Decoupling, and Layout Considerations

Many data acquisition parts have two or more ground pins that are not connected together within the device. These "reasons" are often referred to as logic power return, analog common (analog power return), and analog signal ground. These grounds (pins 19 and 22) must be connected together at a point where the ADC is as close to the converter as possible. Ideally, a single solid-state analog ground plane is required under the converter. Current flows through the wires and etched stripes of the circuit card, and due to the resistance and inductance of these paths, hundreds of millivolts can be generated between the analog ground of the system and the ground pin of the ADC. A separate wide conductor bar ground return should be provided for high resolution converters to minimize noise and IR losses of current in the path from the converter to the system ground. In this way, the ADC supply current and other digital logic gate return currents do not add in the same return path as the analog signal, causing measurement errors.

Each ADC supply terminal should be as close as possible to the ADC for capacitive decoupling. A large value capacitor (eg 1µF) in parallel with a 0.1µF capacitor is usually sufficient. The analog power supply will be bypassed to the analog power supply return pin and the logic power supply will be bypassed to the logic power supply return pin.

The metal cover is internally grounded with respect to power, ground, and electrical signals. Do not ground the cover from the outside.

clock rate control

As shown in Figure 13, the AD1376/AD1377 can be operated with faster conversion times by connecting the clock rate control (pin 23) to an external multi-turn trim potentiometer (TCR < 100 ppm/°C).

High Resolution Data Acquisition System

The basic details of a high-resolution data acquisition system using the AD386 and AD1376 or AD1377 are shown in Figure 14. Conversions are initiated by a start pulse on the falling edge of the conversion. This edge drives the AD1376 or AD1377 state line high. The inverter then drives the AD386 into holdover mode. The state remains high throughout the conversion and returns low when the conversion is complete. This allows the AD386 to re-enter tracking mode.

The circuit exhibits nonlinearity during transients at the A/D input caused by the falling edge of conversion initiation. This edge resets the A/D's internal DAC; the resulting transient depends on the SHA's current output voltage and the A/D's previous conversion results. In the circuit of Figure 14, the falling edge of conversion initiation also puts the SHA into hold mode (via the A/D's state output), causing a reset transient to coincide with the SHA's track and hold transition. Timing skew and capacitive coupling can cause some transients to be added to the signal acquired by the SHA, introducing nonlinearity.

A safer approach is to add triggers, as shown in Figure 15. The conversion start rising edge places the T/H in hold mode before the A/D reset transient begins. A falling edge of state puts the AD386 back into tracking mode. System throughput will decrease if you use the start pulse for long transitions. Throughput can be from:

where TACQ is the T/H acquisition time, TCONV is the time required for the A/D conversion, and TCS is the duration of the conversion start. The combination of the AD1376 and AD386 will provide greater than 50 kHz throughput. If the width of the conversion start is small compared to the conversion time of the A/D, then no significant T/H droop error will be introduced.

Using the AD1376 or AD1377 with Slow Conversion Times To synchronize the A/D to an external clock, the user may wish to run the ADC with slow conversion times. This is achieved by running a slower clock than the internal clock in the start conversion input. This clock must consist of narrow negative-going clock pulses, as shown in Figure 16. The pulse width must be at least 100 nanoseconds, but not greater than 700 nanoseconds. A rising edge immediately after the falling edge suppresses the internal clock pulse. This allows the ADC to function properly and complete the conversion after 17 clock pulses.

The status command will work normally, switching high after the first clock pulse and falling to low after the 17th clock pulse. In this way, the ADC can be controlled with slower conversion times using an external clock.