feature

Complete 16-bit D/A function; on-chip output amplifier; on-chip embedded Zener voltage reference; 61 LSB integral linear; 15-bit monotonic overtemperature; microprocessor compatible; serial or byte input; double buffered latch; fast ( 40 ns) write pulse; asynchronous clear (to 0 V) function; serial output pin facilitates daisy chaining; unipolar or bipolar output; low fault: 15 nV-s; low THD+N: 0.009%.

Product Description

The AD660 DACPORT is a complete 16-bit monolithic D/A converter with an on-board voltage reference, double-buffered latch, and output amplifier. It is fabricated on the BiMOS II process for analog devices. The process allows low-power CMOS logic functions to be fabricated on the same chip as high-precision bipolar linear circuits.

The architecture of the AD660 guarantees 15-bit monotonicity over time and temperature. Integral and differential nonlinearity is maintained at a maximum of ±0.003%. On-chip output amplifiers provide voltage output settling times in the 10µs to 1/2 LSB range for full-scale steps.

The AD660 has an extremely flexible digital interface. Data can be loaded into the AD660 in serial mode or as two 8-bit bytes. This can be achieved through two digital input pins with dual functions. The serial mode input format is pin selectable, MSB or LSB first. The serial output pin allows the user to daisy-chain several AD660s by transferring data through the input latches to the next DAC, thereby minimizing the number of control lines required for SIN, CS, and LDAC. The byte-mode input format is also flexible, as either high-byte or low-byte data can be loaded first. The double-buffered latch structure eliminates data skew errors and provides synchronized updates for DACs in multi-DAC systems.

The AD660 has five grades. AN and BN models are specified between -40°C to +85°C and are packaged in 24-pin 300 mil plastic dip. AR and BR variants are also specified between -40°C to +85°C and are packaged in a 24-pin SOIC. The SQ type is packaged in a 24-pin 300 mil cerdip package and is also available per mil-STD-883. See the AD660/883B data sheet for specifications and test conditions.

DACPORT is a registered trademark of Analog Devices, Inc.

Product Highlights

1. AD660 is a complete 16-bit DAC with voltage reference, double-buffered latch and monolithic output amplifier.

2. Internally buried Zener reference is laser trimmed to 100,000 volts, ±0.1% maximum error and temperature drift performance ±15 ppm/°C.

3. The output range of the AD660 is pin programmable and can be set to provide a unipolar output range of 0 V to +10 V or a bipolar output range of -10 V to +10 V. No external components are required.

4. The AD660 specifies both DC and AC. DC specifications include ±1 LSB INL and ±1 LSB DNL errors. AC specifications include 0.009% THD+N and 83dB signal-to-noise ratio.

5. Double-buffered latches on the AD660 eliminate data storage errors, allowing simultaneous DAC updates in multi-DAC applications.

6. Whether the DAC is in unipolar or bipolar mode, the CLEAR function can asynchronously set the output to 0v.

7. The output amplifier performs a full-scale step in the range of 10 microseconds to ±1/2 LSB and a temperature step of 1 LSB in the range of 2.5 microseconds. The output fault is typically 15 nV-s when loaded with full-scale steps.

AD660 – Specifications (=25=+15 V, VE=-15 V, VLL=+5 V, unless otherwise noted)

canonical definition

Integral Nonlinearity: Analog devices define integral nonlinearity as the actual, adjusted maximum deviation of the DAC output from the ideal analog output (straight line from 0 to FS - 1 LSB) for any combination of bits. This is also known as relative precision.

Differential Nonlinearity: Differential nonlinearity is a measure of the change in analog output, normalized to full scale, relative to a 1LSB change in the digital input code. Monotonicity requires the differential linearity error to be greater than or equal to -1lsb over the temperature range of interest.

Monotonicity: A DAC is monotonic if the output increases or remains the same as the digital input is increased, with the result that the output is always a single-valued function of the input.

Gain Error: Gain error is a measure of the output error between the ideal DAC and the actual device output, loaded with all 1s after compensation error adjustment.

Offset Error: Offset error is the combined offset error of the voltage-mode DAC and output amplifier, measured with all 0s loaded in the DAC.

Bipolar Zero Error: When the AD660 is connected to the bipolar output and 10. . . 000 is loaded into the DAC, and the deviation of the analog output from the ideal midscale value of 0v is called the bipolar zero error.

Drift: Drift is the change in parameters such as gain, offset, and bipolar zero over a specified temperature range. The drift temperature coefficient in ppm/°C is calculated by measuring the parameters at TMIN, 25°C and TMAX and dividing the parameter change by the corresponding temperature change.

Total Harmonic Distortion + Noise: Total Harmonic - Unary Distortion + Noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the harmonic and noise values to the fundamental input frequency value. It is usually expressed as a percentage.

THD+N measures the magnitude and distribution of linearity error, differential linearity error, quantization error, and noise. Depending on the magnitude of the output signal, the distribution of these errors may vary. Therefore, to be most useful, THD+N should be specified for large and small signal amplitudes.

Signal-to-noise ratio: The signal-to-noise ratio is defined as the ratio of the output amplitude when a full-scale signal is present to the output amplitude when no signal is present. In decibels.

Digital-to-Analog Fault Pulse: This is the amount of charge injected from the digital input to the analog output when the input changes state. Measured at half-scale when the DAC switches around the MSB and as many switches as possible change state (i.e. starting at 011). . . 111 to 100 . . . 000.

Digital Feedthrough: When the DAC is not selected (i.e., CS is held high), high frequency logic activity on the digital input is capacitively coupled through the device and appears as noise on the VOUT pin. This noise is digital feedthrough.

theory of operation

The AD660 uses an array of bipolar current sources and MOS current-controlled switches to generate current proportional to the applied digital word, ranging from 0 to 2 mA. A segmented structure is used in which the most significant four data bits are decoded by the thermometer to drive 15 equal current sources. The smaller bits are scaled using an R-2R ladder and then applied to the summing node of the output amplifier along with the segmented source. An internal span/bipolar offset resistor can be connected to the DAC output to provide a 0 V to +10 V span, or to the reference input to provide a -10 V to +10 V span.

Analog circuit connection

The internal scaling resistors provided in the AD660 can be connected to produce a unipolar output range of 0 V to +10 V or a bipolar output range of -10 V to +10 V. Gain and offset drift in the AD660 is minimized due to thermal tracking of the scaling resistors with other device components.

Unipolar configuration

The configuration shown in Figure 3a will provide a unipolar 0 V to +10 V output range. In this mode, 50Ω resistors are connected between the jumper/bipolar bias terminal (Pin 22) and VOUT (Pin 21), and between REF OUT (Pin 24) and REF IN (Pin 23). By tying pin 24 directly to pin 23 and pin 22 directly to pin 21, the AD660 can be used without any external components. Eliminating these resistors will increase the gain error by 0.25% of the FSR.

If the gain and offset errors need to be adjusted to zero, this can be done using the circuit shown in Figure 3b. The adjustment steps are as follows:

Step 1.. Zero Adjust Turn off all bits and adjust zero trimmer R4 until the output reads 0.000000 volts (1 LSB = 153 microvolts).

Step 2.. Gain Adjustment Turn on all bits and adjust gain trimmer R1 until the output is 9.999847 volts. (Full scale adjusted to less than 1 LSB of nominal full scale of 10.000000 volts).

bipolar structure

The circuit shown in Figure 4a will provide a bipolar output voltage from -10.000000 V to +9.999694 V with a positive full scale with all bits on. In unipolar mode, resistors R1 and R2 can be completely eliminated to provide bipolar operation of the AD660 without any external components. In bipolar mode, removing these resistors will increase the gain error by 0.50% of FSR.

Using the circuit shown in Figure 4b, the gain offset and bipolar zero error can be adjusted to zero as follows:

Step 1. Offset adjustment turns off all bits. Adjust trimmer R2 to provide 10.000000 volts output.

Step 2.. Gain Adjust Turn on all bits and adjust R1 to give a reading of +9.999694 volts.

Step 3.. Bipolar Zeroing (Optional) In applications that require an exact zero output, set MSB to ON, all other bits to OFF, and rescale R2 for a zero volt output.

offset adjustment

It is important to note that the use of external resistors will introduce a small temperature drift component that exceeds the temperature drift component inherent to the AD660. The internal resistors are trimmed to match and temperature track the other resistors on the chip, even though they have an absolute tolerance of ±20% and an absolute temperature coefficient of about 50 ppm/°C. In the case of external resistors, the temperature coefficient mismatch between the internal and external resistors, multiplied by the circuit's sensitivity to changes in the external resistor value, will be the resulting additional temperature drift.

Internal/External Reference Use

The AD660 has an internal low noise buried Zener diode reference that is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for high speed DACs and will provide long term stability equal to or better than the best discrete Zener diode references. The performance of the AD660 is specified by the internal reference driving the DAC and a separate DAC (for a precision external reference).

The internal reference has enough buffered DACs (typically 1mA to reference input, 1mA to bipolar offset) in addition to the reference current needed to drive the external circuit. At least 2mA can be used to drive external loads. If the AD660 reference output is required to provide a total current greater than 4 mA, it should be buffered with an external op amp. Benchmarked and guaranteed to a maximum error of ±0.2%.

It is also possible to use an external reference voltage other than 10 volts, with a slightly reduced linearity specification. The recommended reference voltage range is +5 V to +10.24 V, with the 5 V, 8.192 V, and 10.24 V ranges allowed. For example, by using the AD586 5 V reference, a 0v to +5v unipolar or ±5v bipolar output can be achieved. The AD660 can be operated from a ±12 V supply with a 10% tolerance using the AD586 voltage reference.

Figure 5 shows the AD660 using the AD586 precision 5V reference in a bipolar configuration. The highest grade AD586MN specifies a drift of 2ppm/°C, a 7.5x improvement over the AD660's internal reference. The circuit includes two optional potentiometers and an optional resistor that can be used to adjust gain, offset, and bipolar zero error in a manner similar to that described in the Bipolar Configuration section. Use –5.000000 V and +4.999847 as output values.

The AD660 can also be used with the AD587 10 V reference, using the same configuration shown in Figure 5 to produce ±10 V outputs. The highest grade, the AD587LR, has N specified at 5 ppm/°C, a 3x improvement over the AD660's internal reference.

Figure 6 shows the AD660 using the AD680 precision ±10 V reference, in a unipolar configuration. The highest grade AD688BQ has a temperature coefficient of 1.5ppm/°C. The ±10V output is also ideal for providing precise biasing for the bias trimmer resistor R4.

Output stable and faulty

The output buffer amplifier of the AD660 typically settles to within 0.0008%FS (1/2 LSB) of its final value within 8 microseconds for a full-scale step. Figures 7a and 7b show the settling of the full-scale and LSB steps with a 2 kΩ, 1000 pF load applied, respectively. The guaranteed maximum settling time is 13 s at 25°C with a full load step. Typical settling time for a 1 lsb step is 2.5 microseconds.

Digital to analog fault pulses are specified at 15 nV-s typical. Figure 7c shows typical fault pulse characteristics at code 011. . . 111 to 100. . . 000 transitions when loading second-level registers from first-level registers.

Digital Circuit Details

The AD660 has several "dual-purpose" pins that allow flexible operation while maintaining the lowest possible pin count and therefore smallest package size. Therefore, the user should pay attention to the following information when applying the AD660.

Data can be loaded into the AD660 in serial or byte mode, as described below.

Serial mode operation is enabled by lowering SER (pin 17). This changes the function of DB0 (pin 12) to that of the serial input pin SIN. It also changes the function of DB1 (Pin 11) to a control input that tells the AD660 whether serial data will be loaded MSB or LSB first.

In serial mode, the dual function except LBE is to control whether the user wants the asynchronous clear function to go to unipolar or bipo-ral zero. (When CLR is gated, the low-pass LBE sends the DAC output to the unipolar zero and the high-pass to the bipolar zero.) The AD660 does not care about the state of the HBE in serial mode.

As shown in Figure 1b, data is recorded into the input register on the rising edge of CS. The data is then resident in the first column of latches and can be loaded into the DAC latches by leaving LDAC high. This will cause the DAC to change to the appropriate output value.

It should be noted that the clear function clears the DAC latch, but not the primary latch. Therefore, simply turning LDAC high after the necessary event occurs to reload the data previously resident in the one-stage latch pending CLR has ended. Alternatively, new data can be loaded into the first column latches if desired.

The serial output pin (SOUT) can be used to chain multiple DACs together in multiple DAC applications to minimize the number of isolators used to cross the intrinsically safe barrier. The first stage latch acts like a 16-bit shift register, and repeated movement of CS will transfer data from SOUT to the next DAC. Each DAC in the chain needs its own LDAC signal, unless all DACs are updated at the same time.

Byte mode operation is enabled simply by holding SER high, which configures DB0-DB7 as data inputs. In this mode HBELBE is used to identify data as the high or low byte of a 16-bit input word. (The user can load data into the primary latches in any order.) As in serial mode, when CLR is strobed, the state of the LBE determines whether the AD660 clears to a unipolar or bipolar zero. There - so when in byte mode the user must take care to set the LBE to the desired state before triggering the CLR. (In serial mode, the user can simply set the LBE hardware to the desired state.)

Note: CS is edge-triggered. HBE, LBE and LDAC are horizontal triggering.

AD660 – Microprocessor Interface Section

AD660 to MC68HC11 (SPI bus) interface

The interface between AD660 and Motorola SPI (Serial Peripheral Interface) is shown in Figure 8. The MOSI, SCK and SS pins of HC11 are connected to the LDAC pins of BIT0, CS and AD660 respectively. The SER pin of the AD660 is tied low, causing the first-stage latch to be transparent. Most interface issues are handled during software initialization. A typical routine, such as the one shown below, starts by initializing the state of the various SPI data and control registers.

The most significant data byte (MSBY) is then retrieved from the memory processed by the SENDAT subroutine. The SS pin is driven low by indexing into the PORTD data register and clearing bit 5. This makes the second stage latch of the AD660 transparent. Then, MSBY is set as the SPI data register and it is automatically transferred to the AD660.

The HC11 generates the required 8 clock pulses, and the data is valid on the rising edge. After the most meaningful byte is sent -ted, the least significant byte (LSBY) is loaded from memory and transferred in a similar fashion. To complete the transfer, the LDAC pin is driven, latching the complete 16-bit word into the AD660.

AD660 to Microwire Interface

The AD660's flexible serial interface is also compatible with the National Semiconductor Microwire Interface interface. The MICROWIRE interface is used on microcontrollers such as the COP400 and COP800 series processors. The general interface of the microwire interface is shown in Figure 9. The G1, SK, and SO pins of the microwire interface are - fully connected to the AD660's LDAC, CS, and BIT0 pins.

AD660 to ADSP-210x Family Interface

The serial mode of the AD660 minimizes the number of control and data lines required to interface with digital signal processors (DSPs) such as the ADSP-210x family. The application in Figure 10 shows the interface between the ADSP-2101 and AD660. The TFS pin and DT pin of the ADSP-2101 should be connected to the SER and BIT0 pins of the AD660, respectively. An inverter is required between the SCLK outputs and the CS input of the AD660 to ensure that data transfers to the BIT0 pin are valid on the rising edge of CS.

The DSP's serial port (SPORT) should be configured in alternate frame mode so that the TFS meets the -SER length frame requirements. Note that the INVTFS bit in the motion control register should be set to a signal that inverts TFS to make SER the correct polarity. The LDAC signal must meet a minimum hold specification of tIH, which is easily achieved by the 74HC74 flip-flop delaying the rising edge of SER. The CS signal clock triggers the flip-flop, resulting in a delay of approximately one CS clock cycle.

In applications such as waveform generation, precise timing of output samples is important to avoid noise caused by LDAC signal jitter. In this example, the ADSP-2101 is set up to use an internal timer to interrupt the processor at the exact and desired sample rate. When a timer interrupt occurs, the processor's 16-bit data word is written to the transmit register (TXn). This enables the DSP to automatically generate the TFS signal and start transmitting data.

AD660 to Z80 interface

Figure 11 shows a Zilog Z-80 8-bit microprocessor connected to the AD660 using the byte mode interface. The double-buffering capability of the AD660 allows the microprocessor to independently write to the low- and high-byte registers and update the DAC output. With processor speeds up to 6mhz on the Z-80B, using the 74ALS138 as an address decoder to interface with the AD660 requires no additional wait states.

Application Information - AD660

The address decoder analyzes the input and output addresses pro-guided by the processor to select the function to be performed by the AD660, defined by the coherence of the input and output request (IORQ*) and write (WR*) pins. The least significant address bit (A0) determines whether the AD660 low or high byte register is active. The more important address bits are selected between input register loads, DAC output updates, and unipolar or bipolar clears.

A typical Z-80 software routine first writes the low byte of the desired 16-bit DAC data to address 0, and then writes the high byte to address 1. Then, update the DAC output by activating the LDAC with write address 2 (or 3). The zero-to-unipolar case occurs when address 4 is written, and the zero-to-bipolar case is performed by writing to address 5. The actual data written to addresses 2 to 5 is irrelevant. The decoder can easily be extended to control the AD660 required.

noise

In high-resolution systems, noise is often the limiting factor. A 16-bit DAC with a 10-volt span has an LSB size of 153 microvolts (–96 dB). Therefore, the noise floor must be kept below this level in the frequency range of interest. The noise spectral density of the AD660 is shown in Figures 12 and 13. Figure 12 shows the DAC output noise voltage spectral density over the 20 V range (excluding the reference voltage). This graph shows the 1/f corner frequency at 100 Hz and the following broadband noise of 120 nV/√Hz. Figure 13 shows the reference noise voltage spectral density. This figure shows the reference broadband noise

board layout

Designing with high-resolution data converters requires careful attention to board layout. Tracking impedance is the first problem. A current of 306 microamps through a 0.5Ω trace will produce a voltage drop of 153 microvolts, which is 1 LSB at a 16-bit level for 10 volts full scale. In addition to ground drop, inductive and capacitive coupling also needs to be considered, especially when high-precision analog signals share a board with digital signals. Finally, to filter out AC noise, the power supply needs to be decoupled.

Analog and digital signals should not share the same path. Each signal should have an appropriate analog or digital loop. Using this method, the signal loop encloses a small area, minimizing the inductive coupling of noise. It is strongly recommended to use wide PC tracks, heavy gauge wires, and ground planes to provide low impedance signal paths. Separate analog and digital ground planes should also be used, with an interconnection point to minimize ground loops. Analog signals should be kept as far away as possible from digital signals and crossed at right angles.

A feature of the AD660 is that the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/BIP OFFSET, VOUT, and AGND) are adjacent to help isolate analog signals from digital signals.

Power decoupling

The AD660 power supply should be well filtered, well regulated, and free of high frequency noise. Switching power supplies are not recommended because they are prone to spikes that can create noise in analog systems.

Decoupling capacitors should be used in very close layout proximity between all power pins and ground. A 10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor provides adequate decoupling. VCC and VEE should be bypassed to analog ground, and VLL should be separated from digital ground.

The trace length between the capacitor leads and the corresponding converter power and common pins should be minimized. The circuit layout should try to keep the AD660, associated analog circuits, and interconnect circuits away from the logic circuits. A solid analog ground plane around the AD660 will isolate large switch ground currents. For these reasons, covered wire circuit construction is not recommended; careful printed circuit construction is preferred.

AD660

ground

The AD660 has two pins designated as analog ground (AGND) and digital ground (DGND). The analog ground pin is the "high quality" ground reference point for the device. Any external loads on the AD660 output should be returned to analog ground. If using an external reference, it should also be returned to analog ground.

If a single AD660 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND, keeping the lead lengths as short as possible. Then connect AGND and DGND on the AD660. If using multiple AD660s or AD660s to share the analog power supply with other components, connect the analog and digital returns together at the power supply rather than at each chip. This single interconnect to ground prevents large ground loops that prevent digital currents from flowing through the analog ground.