W9816G6IH is a high-speed synchronous dynamic random access memory (SDRAM) composed of 512K words × 2 rows × 16 bits. The W9816G6IH provides up to 2 million words per second of data bandwidth (-5). For different applications, the W9816G6IH is divided into the following speed grades: -5/6/-7/-6I and -7I, the -5 part can reach 200MHz/CL3 or 143MHz/CL2. -6/-6I parts up to 166MHz/CL3 (guaranteed to support -6I class at -40°C~85°C) -7/-7I parts up to 143MHz/CL3 (guaranteed to support -40°C~85°C -7I level). Access to SDRAM is burst-oriented. Contiguous memory locations within a page can be accessed in burst lengths of 1, 2, 4, 8, or a full page when rows and rows are selected using active commands. In burst operation, the SDRAM internal counter automatically generates the column address. A random column can also be read by providing its address every clock cycle. The multi-bank nature allows interleaving between internal banks to hide the precharge time. By having programmable mode registers, the system can vary the burst length, delay period, interleaving or sequential bursts to maximize its performance. The W9816G6IH is ideal for main memory in high performance applications.
Provide 2.7V~3.6V power supply, suitable for -7/-7I speed class 3.3V±0.3V power supply, suitable for -5/-6/-6I speed class 524288 words x 2 columns x 16 bits Organization self-refresh current: standard and Low Power CA Latency: 2 and 3 Burst Lengths: 1, 2, 4, 8 and Full Page Burst Read, Single Write Mode Byte Data Controlled by LDQM, UDQM Auto Precharge and Controlled Precharge 4K Refresh Cycle/64ms interface: LVTTL packaged in 50-pin, 400 mil TSOP II using RoHS compliant lead-free materials

Functional Description The default power-up state of the power-up and initialization mode registers is unspecified. The following power-up and initialization sequence needs to be followed to ensure that the device is preconditioned to each specific user need during power-up, all VCC and VCCQ pins must simultaneously rise to the specified voltage while the input signal remains in the "NOP" state. The power-on voltage must not exceed VCC+0.3V on any input pin or VCC supply. After power up, a 200 second pause is required, and then all cylinder banks are precharged using the precharge command. To prevent data races on the DQ bus during power-up, it is required to keep the DQM and CKE pins high during the initial suspend. Once all banks are precharged, the mode register set command must be issued to initialize the mode registers. An additional eight auto-refresh cycles (CBR) are required before or after programming the mode register to ensure proper subsequent operation.
After initial power-up of the programming mode register, the mode register set command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high for at least one cycle before issuing a mode register set command. The mode register set command is activated by the low signal of RA, SCAS, CS and WE on the positive edge of the clock. The address input data within this cycle defines the parameters to be set, as shown in the Mode Register Operations table. Once a delay equal to tRSC has been exceeded, a new command can be issued after the mode register set command. The mode register setting cycle and operation table are shown on the next page.
Bank Activation Command The bank activation command must be applied before any read or write operations can be performed. The operation is similar to activating RA in EDO DRAM. The delay from the application of the Bank Activate command to when the first read or write operation can begin shall not be less than the RAS to CAS delay time (t S RCD). Once a bank is activated, it must be precharged before another bank activation command can be issued to the same bank. The minimum time interval between consecutive group activation commands for the same group is determined by the device's RAS cycle time (tRC). The minimum time interval between staggered bank activation commands (Bank A to Bank B and vice versa) is the Interbank Delay Time (tRRD). The maximum time each bank can remain active is designated as tRAS(max).
Read-write access mode After the bank is activated, a read-write cycle can be followed. This is achieved by setting RAS high and CAS low on the rising clock edge after tRCD delay is minimal. The We pin voltage level defines whether the access cycle is a read operation (We high) or a write operation (We low). The address input determines the starting column address. Reading or writing to other rows in an activated bank requires precharging the bank and issuing a new bank activation command. When multiple banks are activated, cross-bank read and write operations are possible. Alternating access and precharge operations among multiple banks with a programmed burst length enables seamless data access operations between multiple different pages. Read or write commands can also be issued to the same group or between active groups every clock cycle.

The burst read command is initiated by applying a logic low to CS and CAS while holding RAS and WE high on the rising edge of the clock. The address input determines the starting column address of the burst. The mode register sets the burst type (sequential or interleaved) and burst length (1, 2, 4, 8 and full page) within the mode register setup cycle. Tables 2 and 3 on the next page explain the address sequences for interleaved and sequential modes.
A burst write command is initiated by applying a logic low to CS, CAS, and WE while holding RAS high on the rising edge of the clock. The address input determines the starting column address. The data for the first burst write cycle must be applied to the DQ pins on the same clock cycle that the write command was issued. The remaining data input must be available on each subsequent rising clock edge until the burst length is complete. Data supplied to the DQ pins after the burst ends will be ignored.
Read Interrupted by Read A burst read can be interrupted by another read command. When the previous burst is interrupted, the remaining addresses are overwritten with new read addresses with the full burst length. Data from the first read command continues to appear on the output until the CAS delay from the interrupted read command is met.
A read is interrupted by a write Interrupting a burst read with a write command may require the DQM to place the DQs (output drivers) in a high impedance state to avoid data races on the DQ bus. If a read command will issue data on the first and second clock cycles of a write operation, a DQM is required to ensure that the DQs are tri-stated. After that, the Write command will control the DQ bus, no longer needing DQM masking.
A write interrupted by a write The burst write can be interrupted before the burst write is completed by another write command. When the previous burst is interrupted, the remaining addresses will be overwritten by the new addresses and the data will be written device until the programmed burst length is met.
A write-read command interrupted by a read will interrupt a burst write operation on the same clock cycle that the read command was activated. Before new read data appears on the output, dq must be in a high impedance state for at least one cycle to avoid data races. When the Read command is activated, any remaining data from the burst write cycle will be ignored.

A burst stop command can be used to terminate an existing burst operation, but if the burst length is a full page, the bank is reserved for future read and write commands to the same page of the active bank. It is illegal to use the burst stop command during other burst length operations. The definition of a burst stop command is: RAS and CAS high, CS low, WE low, on the rising edge of the clock. The data dq enters the high impedance state after a delay equal to the CAS delay in the burst read cycle interrupted by the burst stop. If a burst stop command is issued during a full page burst write operation, any remaining data in the burst write cycle will be ignored

Auto Precharge Command If A10 is set high when a read or write command is issued, the auto precharge function is entered. During auto-precharge, the read command will execute normally, but the active bank will begin auto-precharge before all burst read cycles are complete. Regardless of the burst length, it will start a certain number of clocks before the end of the predetermined burst period. The number of clocks is determined by the CAS latency. A read or write command with automatic precharge cannot be interrupted until the entire burst operation is complete. Therefore, the use of read, write, or precharge commands is prohibited during an auto-precharge read or write cycle. Once the precharge operation begins, the battery pack cannot be reactivated until the precharge time (tRP) has been met. It is illegal to issue an auto precharge command if the burst is set to a full page length. If A10 is high when a write command is issued, a write with auto-precharge is initiated. SDRAM automatically enters precharge operation with a two clock delay from the last burst write cycle. This delay is called write tWR. Banks undergoing automatic precharging cannot be reactivated until tWR and tRP are satisfied. This is called tDAL, the data entry activity delay (tDAL=tWR+tRP). When using the automatic precharge command, the interval between the cylinder bank activation command and the start of the internal precharge operation must satisfy tRAS(min).
Precharge Command The precharge command is used to precharge or shut down an activated battery pack. The precharge command is entered when CS, RAS and WE are low on the rising edge of the clock and CAS is high. A precharge command can be used to precharge each cylinder bank individually or simultaneously. Address bits A10 and BA are used to define the bank to be precharged when a command is issued. After a precharge command is issued, the precharged bank must be reactivated before a new read or write access can be performed. The delay between the precharge command and the activate command must be greater than or equal to the precharge time (tRP).
Self-refresh command The definition of the self-refresh command is: on the rising edge of the clock, keep CS, RAS, CA, and CKE low, and WE high. All banks must be idle before issuing a self-refresh command. After command registration, CKE must be held low to keep the device in self-refresh mode. When the SDRAM enters self-refresh mode, all external control signals except CKE are disabled. During self-refresh operation, the clock is disabled internally to save power. After returning high, the device will exit self-refresh operation. After tRC, any subsequent commands can be issued from the end of the Self Refresh command. If during normal operation auto-refresh cycles are issued in bursts (rather than evenly distributed), a burst of 4096 auto-refresh cycles should complete before entering and just after exiting self-refresh mode.

Power-down mode Holds CKE low to initiate power-down mode. All receiver circuits except CKE are turned off to reduce power. Shutdown mode does not perform any refresh operations; therefore, the device cannot be in shutdown mode longer than the device's refresh period (tREF). Power-down mode is exited by taking CKE high. When CKE goes high, the next rising clock edge requires a no-op command according to tCK. The input buffer needs to be enabled with CKE held high for a period equal to tCK(min) + tCK(min).
Disable Operation Commands The Disable Operation command should be used when the SDRAM is in an idle or wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation command is registered when CS is low in RAS, CAS and we hold it high on the rising edge of the clock. A no-op command does not terminate a previous operation that is still executing, such as a burst read or write loop.
Deselect Command The Deselect command performs the same function as the No Action command. The deselect command occurs when CS is turned high and the RAS, CA and WE signals become unimportant.
Clock Suspend Mode In normal access mode, CKE must be held high to enable the clock. Clock pause mode is entered when CKE is registered low when at least one bank is active. Clock Suspend Mode disables the internal clock and suspends any currently executing timed operations. There is a clock delay between registering CKE low and when SDRAM operation is suspended. In clock halt mode, the SDRAM ignores any new commands issued. Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay when CKE exits when it returns to clock suspend mode.

Operation beyond the Absolute Maximum Ratings may cause permanent damage to the device. All voltages are referenced to VSS. • 2.7V~3.6V power supply for -7/-7I speed class. • 3.3V±0.3V power supply for -5/-6/-6I speed classes. These parameters depend on the cycle rate, the values listed are measured at the cycle rate, with minimum values of tCK and tRC. These parameters depend on output load conditions. Gets the specified value when the output is turned on. Please refer to the "Function Description" section described earlier for the power-up sequence. AC test load diagram.
tHZ defines the time for the output to reach the open state, not referenced to the output level. Assume input rise and fall time (tT) = 1nS. If TR and TF are greater than 1ns, transient time compensation should be considered, i.e. ([Tr+Tf)/2-1]NS should be added to the parameters (TT max cannot be greater than 10ns for low frequency applications). If the clock rise time (tT) is greater than 1nS, then (tT/2-0.5)nS should be added to the parameter.