feature

8 x 6 crosspoint switch matrix supports SD, PS and HD 1080i/1080p video inputs Clamp and bias circuits Double terminated 75Ω cable Drivers Programmable 0dB or 6dB gain One-to-many input-output switching I2CTM-compatible digital interface, standard mode 3.3V or 5V single-supply operation, lead-free TSSOP-24 package

application

Cable and Satellite Set-Top Boxes TVs and HDTVs A/V Switches Personal Video Recorders (PVRs) Security and Surveillance Video Distribution Automotive (In-Flight Entertainment)

illustrate

The FMS6502 provides eight inputs that can be routed to any of six outputs. Each input can be routed to one or more outputs, but only one input can be routed to any output. Each input supports an integrated clamp option to set the video at the output sync tip level, synced to ~ 300mV . Alternatively, the input can be internally biased at ~1.25V to a center output signal with no sync (chroma, Pb, Pr). All outputs are designed to drive 150Ω DC coupled loads. Each output can be programmed for 0dB or 6dB of signal gain. Input-output routing and input-bias mode functions are controlled through an I2C-compatible digital interface.

Digital Interface An I2C-compatible interface is used to program output enable, input-to-output routing, and input offset configuration. The I2C address of FMS6502 is 0x06 (00000110) and can be input according to ADDR0 and ADDR1. The offset address is defined as follows:

Data and address data are each written into 8-bit FMS6502 I2C address register function for access control. For efficiency, the output is selected between the two inputs. Multiple outputs can select the same input channel for one-to-many routing. The clamp/bias control bits are written to their own internal addresses because they should remain unchanged regardless of signal routing. They are based on the input signal connected to the FMS6502. All undefined addresses can be written without taking effect.

I2C Interface Bit Transfer Operations The I2C compatible interface conforms to the I2C Standard Mode specification. Personal addresses can be written, but not read. The interface consists of two lines: the serial data line (SDA) and the serial clock line (SCL). Both lines must be connected to the positive power supply through external resistors. Data transfers can only be initiated when the bus is not busy. Bit transfers transfer one data bit during each clock pulse. This is during the high period of the clock pulse. Changes in data lines are interpreted as control signals during this time.

Start and Stop conditions when the bus is not busy. A high-to-low transition of the data line, when the clock is high, is defined as a start condition. A low-to-high transition of the data line while the clock is high is defined as a stop condition (P).

Acknowledging the number of bytes of data transferred between the start and stop conditions from the transmitter to the receiver is infinite. Each octet is followed by an acknowledgement bit. The acknowledgment bit is a high signal on the bus controlled by the transmitter, and the master generates an additional clock pulse associated with the acknowledgment. The slave recipient address must be received on every byte. The master receiver must generate an acknowledgement clock from the transmitter after each byte is received. The acknowledging device must pull down the SDA line during the acknowledgment clock pulse, so the SDA line is stable low during the high period of the clock pulse associated with the acknowledgment (setup and hold times must be taken into account). The master receiver must signal an acknowledgement by not generating the last byte of the slave punch. During this event, the transmitter must hold the data line high for the host to generate a stop condition.

Application Information Input Clamp/Bias Circuit The FMS6502 can accommodate AC or DC coupled inputs. Internal clamping and bias circuits are provided to support AC-coupled inputs. These are optional via an I2C compatible interface via the CLMP bit. For DC-coupled inputs, the device should be programmed to use the "bias" input configuration. In this configuration, the input is internally biased to a 625mV 100kΩ resistor. Distortion is optimized by outputting levels between 250 mV and 500 mV above ground below the power supply. For AC coupled inputs, the FMS6502 uses a simple clamp instead of a full DC recovery circuit. For video signals with and without synchronization, (Y, CV, R, G, B), the lowest voltage at the output pins is clamped to approx. 300 mV from ground. If using symmetrical AC-coupled input signals (Chroma, Pb, Pr, Cb, Cr), a bias circuit can be used to center them within the input common range. The average DC value at the output is about 1.27 volts. The figure shows the clamp mode input circuit and the internal control voltage at the input of the AC-coupled input.

Figure shows the AC-coupled bias mode input circuit and the internal control voltage input for the input pins.

Output Configuration The FMS6502 outputs can be AC or DC coupled. Coupled loads can drive 150Ω loads. The AC-coupled outputs are capable of driving single-ended and double-ended video loads up to 150Ω. An external transistor is required to drive a DC low impedance load. The DC-coupled outputs should be connected as shown.

About 150 mV into the amplifier for a particular channel when the output channel is not connected to the input. The output amplifier remains active unless the I2C interface is specifically disabled. The voltage output level depends on the programmed gain channel. Driving a Capacitive Load When driving a capacitive load, buffer the output with a 10Ω series resistor as shown.

crosstalk when using the FMS6502. Input and output crosstalk represent the main coupling mode applications that can occur under typical conditions. Input crosstalk is the crosstalk in the input pins toggling when the jamming signal is turned on. It is primarily controlled by inductive coupling in the package lead frame between adjacent leads. It reduces when interfering signals move away from pins adjacent to the selected input signal. Output crosstalk is the effective output coupling from one driver output to another. It decreases with increasing load impedance, mainly caused by ground and power coupling between the output amplifiers. If the signal drives the switch on, its crosstalk is mainly input crosstalk. If so, the crosstalk is the primary output crosstalk when driving the load through the active output. The test configuration for making input and output crosstalk measurements is shown in the figure.

For input crosstalk, the switch is open and all inputs are in bias mode. The Channel 1 input is driven by a 1Vpp signal, while all other inputs are terminated with 75Ω AC. All outputs are enabled, and crosstalk is measured from 1 on any output. For output crosstalk, the switch is closed. Crosstalk source measurement output 1 to any output. Crosstalk from multiple sources to a given channel is measured using the setup shown. Input In1 is driven by a 1Vpp pulse source and connected to Output 1 to Output 8. Input In9 is driven by a secondary, asynchronous grayscale video signal and is connected to outlet 9. All other inputs are terminated with 75Ω AC. Based on the measured standard 1Vpp output, the crosstalk effect on the gray field is measured and calculated upon loading. Avoid using adjacent channels to reduce crosstalk if not required for all inputs and outputs.

Layout Considerations General layout and power supply bypass performance and thermal characteristics at high frequency. Fairchild provides a demo board to guide the layout as well as aid device evaluation. The demo board is a four-layer board with full power and ground plane. Following this layout configuration provides the best performance and thermal characteristics of the device. For best results, follow the steps and recommended routing rules listed below. Recommended routing/layout rules Do not run analog and digital signals in parallel. Powered using separate analog and digital power planes. The traces should be at the top epoch of the ground plane. There must be no traces on the ground/power shunt. Avoid wiring at 90-degree angles. Minimize clock and video data trace length differences. Includes 10µF and 0.1µF ceramic power supply bypass capacitors. Place a 0.1µF capacitor at the device power pins. Place a 10µF capacitor at the device power pins. For multi-layer boards, use a large ground plane to help dissipate heat. For two-layer boards, use an extended ground plane that extends at least 0.5 inches beyond the main body of the device. The top layer below the device.

Minimize all trace lengths to reduce series inductance. Thermal considerations Since the interior of most systems, such as set-top boxes, TVs and DVD players are +70°C; consideration must be given to providing adequate heat sinks to provide maximum heat dissipation for the device package. When designing your system board, make sure that power is dissipated from each device. Make sure that the device high power is not in the same location, for example directly above (top side) or (bottom side) below the other on the printed circuit board. PCB Thermal Layout Considerations Learn about system power requirements and environmental conditions. Maximize the thermal performance of your PCB. Consider using 70 micron copper for high power designs. Make the PCB as thin as possible by reducing FR4. Connect adjacent layers together using the vias on the power board. Remember, the base temperature is the board area, not the copper thickness. Modeling techniques can provide a first-order approximation. The worst case for power dissipation is that the increased die power due to the DC load is estimated as a Vcc2/4R load per output channel. This assumes a constant DC output voltage of Vcc/2.

For 5V Vcc with dual DC video load, add 25/(4*75)=83mW, per channel. Application Matrix of the FMS6502 Video Switch The increasing demand for consumer multimedia systems presents a formidable challenge for system designers to provide cost-effective solutions that take advantage of the growth potential of graphics display technology. These applications require cost-effective video switching and filtering solutions to quickly and efficiently deploy high-quality display technology to target audiences. Areas of particular interest include HDTVs, media centers, and automotive infotainment (eg, navigation, in-car entertainment, and backup cameras). In all cases the advantages offered by the integrated video switch matrix are high quality video switches for the specific application, as well as video input fixtures and on-chip, low impedance output cable drivers with switch gain. Typically, the largest application of video switches is the front end of high-definition television. This is used to input and route it to the appropriate signal path (main picture and picture within picture, or PiP). These are usually routed to the ADC, then the decoder. HDTV technologies include LCD, plasma, and CRT, with similar analog switching circuits. VIPDEMOTM control software FMS6502 through I2C compatible digital configuration interface. For demonstration purposes, Fairchild Semiconductor developed control software based on the VIPDEMOTM graphical user interface to write to the FMS6502 register map. This software is included in the FMS6502 Demonstration Kit. Parallel line port I2C adapter and connection to demo board are also included. In addition to making full use of the FMS6502 interface, VIPDEMOTM can also be used to control the single-register read and write of I2C.