feature

±0.2 LSB (±0.00031%) typical peak DNL and INL; ±0.5 LSB (±0.00076%) typical unipolar offset, bipolar zero; 17-bit monotonicity guaranteed; 18-bit resolution (serial mode); complete 16 /18-bit D/A function; on-chip output amplifier; on-chip buried zener voltage reference; microprocessor compatible; serial or byte input; double buffered latch; asynchronous clear function; serial output pin facilitates daisy-chaining chain; pins can be bundled for unipolar or bipolar output; low THD+N: 0.005%; multiple output control and power failure at power-up.

Product Description

The AD760 is a complete 16/18-bit self-calibrating monolithic DAC (DACPORT 174 ;) with an on-board voltage reference, double-buffered latch and output amplifier. It is fabricated on the BiMOS II process for analog devices. The process allows low-power CMOS logic functions to be fabricated on the same chip as high-precision bipolar linear circuits.

Self-calibration is initiated by simply pulsing the calibration pin low. The calibration pin indicates when the calibration has completed successfully. The output multiplexer (MUXOUT) can be used to route the output to the bottom of the output range during calibration.

Data can be loaded into the AD760 as straight binary, serial data, or two 8-bit bytes. In serial mode, either 16-bit or 18-bit data can be used, and the serial mode input format is pin selectable, MSB or LSB first. This is achieved through three digital input pins (pins 12, 13 and 14) with dual functions. In byte mode, the user can similarly define whether to load the high byte or the low byte first. The serial output (SOUT) pin allows the user to chain multiple AD760s in series by transferring data through the input latch to the next DAC, thereby minimizing the number of control lines required in multiple DAC applications. The double-buffered latch structure eliminates data skew errors and provides synchronized updates for DACs in multi-DAC systems.

The asynchronous CLR function can be configured to clear negative full-scale or mid-scale outputs, depending on the state of Pin 17 when CLR is strobed. The AD760 can also output multiplexers in predetermined states through digital and analog power supply detection circuits. This is especially useful for robotics and industrial control applications.

The AD760 is available in a 28-pin 600 mil cerdip package.

The AQ version is specified from -40°C to +85°C.

AC performance characteristics except total harmonic distortion + noise and signal-to-noise ratio

ratios, these characteristics are for design guidance only and are not subject to testing. THD+N and SNR 100% test. (TMIN

Timing Characteristics (VCC=+15 V, VE=-15 V, VLL=+5 V, VIH=2.4 V, VIL=0.4 V)

Absolute Maximum Ratings*

VCC to AGND. . .. . . –0.3 V to +17.0 V

Turn to AGND. . . . . . . . . . . . . . . +0.3 V to –17.0 V

VLL to DGND. . . . . . . . . . . . . –0.3 V to +17.0 V

From AGND to DGND. . . . . . . . .±1V

Digital Inputs (Pins 2, 7-14 and 16-21) to DGND. . . . . . . . –1.0V to +7.0V

Referenced to AGND . . . . .. . . . . . . . .±10.5 V

Span/Bipolar Offset to AGND. . . . . . . . . . . ±10.5 V

Reference output, output, output, output, output. . . . Infinitely shorter than AGND, DGND, VCC, VEE, and VLLθJA, thermal impedance. . . . 50°C/W

Junction Temperature . . . . . . . . . . . . . . . . 175°C

Storage temperature . . . . . . . . . . . . . . . –65°C to +150°C

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . + 300 °C

Stresses higher than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is only a pressure rating and the functioning of the device under the above conditions or any other conditions is not implied by the Operational section of this specification. Exposure to maximum rated conditions for absolutely extended periods may affect device reliability.

canonical definition

Integral Nonlinearity: The analog device defines integral nonlinearity as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (straight line from 0 to FS-1 LSB) for any combination of bits. This is also known as relative precision.

Differential Nonlinearity: Differential nonlinearity is a measure of the change in the analog output, normalized to full scale, relative to a 1LSB change in the digital input code. Monotonicity requires the differential linearity error to be greater than or equal to -1lsb over the temperature range of interest.

Monotonicity: A DAC is monotonic if the output increases or remains the same as the digital input is increased, with the result that the output is always a single-valued function of the input.

Gain Error: Gain error is a measure of the output error between the ideal DAC and the actual device output, loaded with all 1s after compensation error adjustment.

Offset Error: Offset error is the combined offset error of the voltage-mode DAC and output amplifier, measured with all 0s loaded in the DAC.

Bipolar Zero Error: When AD760 is connected to bipolar output and 10. . . 000 is loaded into the DAC, and the deviation of the analog output from the ideal midscale value of 0v is called the bipolar zero error.

Drift: Drift is the change in parameters such as gain, offset, and bipolar zero over a specified temperature range. The drift temperature coefficient in ppm/°C is calculated by measuring the parameters at TMIN, 25°C and TMAX and dividing the parameter change by the corresponding temperature change.

Total Harmonic Distortion + Noise: Total Harmonic - Unary Distortion + Noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the harmonic and noise values to the fundamental input frequency value. It is usually expressed as a percentage. THD+N measures the magnitude and distribution of linearity error, differential linearity error, quantization error, and noise. Depending on the magnitude of the output signal, the distribution of these errors may vary. Therefore, to be most useful, THD+N should be specified for large and small signal amplitudes.

Signal-to-noise ratio: The signal-to-noise ratio is defined as the ratio of the output amplitude when a full-scale signal is present to the output amplitude when no signal is present. In decibels.

Digital-to-Analog Fault Pulse: This is the amount of charge injected from the digital input to the analog output when the input changes state. Measured at half-scale when the DAC switches around the MSB and as many switches as possible change state (i.e. starting at 011). . . 111 to 100. . . zero digital feedthrough: When the DAC is not selected (ie, CS is held high), high frequency logic activity on the digital input is capacitively coupled through the device and appears as noise on the VOUT pin. This noise is digital feedthrough.

theory of operation

The AD760 uses an auto-calibration circuit to generate a 16-bit DAC with a typical 0.2 LSB integral and differential linearity error and 0.5 LSB offset error. The block diagram in Figure 2 shows the circuit components required for calibration.

The main DAC uses an array of bipolar current sources with MOS current-controlled switches to generate current proportional to the applied digital word, ranging from 0 mA to 2 mA. A segmented structure is used in which the most significant four data bits are decoded by the thermometer to drive 15 equal current sources. The smaller bits are scaled using an R-2R ladder and then applied to the summing node of the output amplifier along with the segmented source. An extra LSB is included in the main DAC for use during calibration.

The self-calibrating structure of the AD760 attempts to reduce the linearity error of its transfer function. The algorithm first checks for bipolar or unipolar operation, calibrates the bipolar zero or unipolar offset, and then removes the carry error (DNL error) associated with the upper 6 bits (64 yards).

Once calibrated, the first six bits of the code going into the main DAC simultaneously address the RAM, invoke a calibration code, and then apply it to the CALDAC. The output currents of the main DAC and CALDAC are combined into a summing amplifier to produce a corrected output voltage.

In the first step of DNL calibration, the output of the main DAC is set to a code just below the code to be calibrated. Turn on the extra LSB in the main DAC to find the extrapolated value for the next code. Then use the transmit STD DAC to zero the comparator. The voltage at VOUT is actually sampled at the code to be calibrated.

Next, the extra LSB is turned off and the main DAC code is incremented by one LSB. The comparator comes again this time using the CALDAC until VOUT is adjusted to be equal to the previous sampled output. The CALDAC code is stored in RAM and the process is repeated for the next code.

Calibrated Linearity Performance

The cumulative probability plots of the AD760INL and DNL shown in Figures 3 and 4 represent the maximum absolute value (peak) linearity error for each section. Approximately 100 parts in 3 wafer batches were used.

The calibrated DNL and INL performance of the population shown is also representative of the expected performance of individual parts that are often calibrated. The expected performance of many parts calibrated at one time is essentially indistinguishable from that of one part calibrated frequently. The AD760 calibration performance is guaranteed at any temperature within the operating temperature range. The peak nonlinearity of the sample population shown also represents the expected maximum linearity error for a single part recalibrated at temperature.

Analog circuit connection

The internal scaling resistors provided in the AD760 can be connected to produce a 0 V to +10 V unipolar output range or a -10 V to +10 V bipolar output range. Gain and offset drift in the AD760 is minimized due to thermal tracking of the scaling resistors with other device components.

Unipolar configuration

The configuration shown in Figure 5a will provide a unipolar 0 V to +10 V output range. In this mode, connect a 50 resistor between REF OUT (pin 26) and REF In (pin 25). By tying pin 26 directly to pin 25, the AD760 can be used without any external components. Removing this resistor will increase the gain error by 0.50% of FSR.

If the gain error needs to be adjusted to zero, this can be done using the circuit shown in Figure 5b. The adjustment steps are as follows:

first step. . . Offset adjustment starts the calibration procedure. CALIBRATE (Pin 1) must be held high throughout gain adjustment.

Step two. . . Gain Adjustment Turn on all bits and adjust gain trimmer R1 until the output is 9.999847 volts. (Full scale adjusted to 1 LSB less than 10.000000 volts nominal full scale.)

bipolar structure

The circuit shown in Figure 6a will provide a bipolar output voltage from -10.000000 V to +9.999694 V with a positive full scale with all bits on. In unipolar mode, resistor R1 can be completely eliminated to provide bipolar operation of the AD760 without any external components. In bipolar mode, removing this resistor will increase the gain error by 0.50% of FSR.

The gain error can be adjusted to zero using the circuit shown in Figure 6b. Note that the gain adjustment changes the bipolar zero to half the change in the full-scale output value. Therefore, to eliminate the iteration between zero (calibration) and gain adjustment, the following steps are recommended.

first step. . . Zero adjustment starts the calibration procedure.

Step two. . . The gain adjustment ensures that the CALOK pin remains high during gain adjustment. Turn on all bits and measure the output error relative to the 9.99695 V full-scale output. Adjust R1 until the output is negative twice the full-scale output error. For example, if the output error is –1 mV, adjust the output to be 2 mV above the last full-scale error.

third step. . . Zero adjustment starts the calibration procedure. The AD760 will calibrate the bipolar zero and the resulting gain error will be very small. Reload the DAC and all DACs to check for full-scale output errors.

It is important to note that the use of external resistors will introduce a small temperature drift component that exceeds the temperature drift component inherent to the AD760. The internal resistors are trimmed to match and temperature track the other resistors on the chip, even though they have an absolute tolerance of ±20% and an absolute temperature coefficient of about 50 ppm/°C. In the case of external resistors, the mismatch in temperature coefficients between the internal and external resistors, multiplied by the circuit's sensitivity to changes in the external resistance value, will give additional temperature drift.

Internal/External Reference Use

The AD760 has an internal low noise buried Zener diode reference, trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for high speed DACs and will provide long term stability equal to or better than the best discrete Zener diode references. The performance of the AD760 is specified by the internal reference driving the DAC and a separate DAC (for a precision external reference).

In addition to the reference current required by the DAC (typically 1mA to REF-in and 1mA to bipolar offset), the internal reference is buffered enough to drive external circuitry. At least 2mA can be used to drive external loads. If more than 4 mA of total current needs to be supplied, the AD760 reference output should be buffered with an external op amp. Benchmarked and guaranteed to a maximum error of ±0.1%.

It is also possible to use an external reference voltage other than 10 volts, with a slightly reduced linearity specification. The recommended range for the reference voltage is +5 V to +10.24 V. For example, by using the AD586 5 V reference, a 0 V to +5 V or ±5 V output can be achieved. The AD760 can be operated from a ±12 V supply with a 10% tolerance using the AD586 voltage reference.

Figure 7 shows the AD760 using the AD586 precision 5V reference in a bipolar configuration. The highest grade AD586MN specifies a drift of 2ppm/°C. The circuit includes an optional potentiometer that can be used to adjust the gain error in a manner similar to that described in the Bipolar Configuration section. Use +4.999847 V as the full-scale output value.

The AD760 can also be used with the AD587, 10V reference, using the same configuration shown in Figure 7 to produce ±10V outputs. The highest grade AD587L is specified at 5ppm/°C.

Output stable and faulty

The output buffer amplifier of the AD760 typically settles to within 0.0008%FS (1/2 LSB) of its final value within 8 microseconds for a full-scale step. Figures 8a and 8b show the settling for full scale and LSB steps when a 2k, 1000pf load is applied, respectively. The guaranteed maximum settling time is 13 s at 25°C with a full load step. Typical settling time for a 1 lsb step is 2.5 microseconds.

Digital to analog fault pulses are specified at 15 nV-s typical. Figure 8c shows typical fault pulse characteristics at code 011. . . 111 to 100. . . 000 transitions when loading second-level registers from first-level registers.

Digital Circuit Details

There are several "dual-purpose" pins that allow flexible operation while maintaining the lowest possible pin count and therefore smallest package size. The following information is very useful when applying the AD760.

The AD760 uses the internal output multiplexer to disconnect the DAC output from MUXOUT (pin 27) when the device is not calibrated or a calibration sequence is in progress. At these times, MUXOUT is switched to MUXIN (pin 28) so that the user can force a predetermined output voltage. See the following sections for information on using the output multiplexer.

The power-on reset function senses when any supply voltage is low enough to compromise the integrity of the calibration data in RAM. At power-up or in the event of a power supply transient, CALOK (pin 1) is low and the MUXOUT pin switches to MUXIN.

Self-calibration is initiated by tapping the CAL pin low (see Figure 1d). The CALOK pin will go low and the MUXOUT pin will be connected to MUXIN. During calibration, the second stage latch is transparent, allowing the calibration sequencer to control the main DAC. After the calibration is successfully completed, the input of the latch of the second column is switched to the latch of the first column, the DAC is loaded with the contents of the latch of the first column, and VOUT is set to the value represented by the data in the latch of the first column, Then CALOK will go high and MUXOUT switches to VOUT. Therefore, before starting calibration, the user should program the DAC with the required data. The secondary latch controlled by the LDAC is a transparent latch. Changes to the first stage latch are immediately reflected in the DAC output as long as LDAC remains high.

The state of calibration can be low through the HBE pin. CALOK toggles high if a calibration is in progress; CALOK remains low if a supply voltage transient interrupts the calibration and causes the AD760 to be set to the uncalibrated state.

When the CLR is strobed, pin 17 is used as the control input UNI/BIP CLR, which determines the asynchronous clear function-installation project (see Figure 1c). If the UNI/BIP CLR pin is logic low when CLR is toggled, the DAC is set to negative full scale; logic high sets the DAC to mid-scale. It should be noted that the clear function clears the DAC latch, but not the primary latch. Therefore, simply turning LDAC high again reloads the data left in the one-stage latch. Alternatively, new data can be loaded into the first column latches if desired.

Serial mode operation is enabled by lowering SER (pin 19). This changes the function of DB0 (pin 14) to that of the serial input pin SIN. The function of DB1 (pin 13) also changes the control input MSB/LSB which determines which bit is loaded first.

Sixteen or eighteen-bit operation with another selectable dual-purpose pin. DB2 (Pin 12) changed to control input 18/16SERIAL, it chooses to use 16-bit or 18-bit serial data. For 16-bit operation, the data inputs (pins 7–12) should be tied low. For 18-bit operation, pin 12 must be tied high.

Data was recorded to the CS as shown in Figure 1b. The data then resides in one level of latches and can be loaded into the DAC by driving the LDAC pin high. This will cause the DAC to change to the output value. In serial mode, the byte controls HBE (pin 18) and LBE (pin 17) are disabled. Pin 17 can be tied to logic high or low depending on how the user wants the asynchronous clear function to work. The serial output pin (SOUT) can be used to chain multiple DACs together in multiple DAC applications to minimize the number of control lines required. The pawn latch is just a shift register, the repeating stroke of CS shifts the data through SOUT into the next DAC. Each DAC in the chain needs its own LDAC signal, unless all DACs are updated at the same time.

Byte mode operation is enabled by setting SER high, which configures DB0–DB7 as data inputs. In this mode, HBE and LBE are used to identify data as the high or low byte of a 16-bit word. The user can load data into the primary latches in any order using the rising edge of the CS signal as shown in Figure 1a. When CLR is strobed, the state of Pin 17 determines whether the AD760 is cleared to unipolar or bipolar zero. (But it cannot be hardwired to the desired state, as in serial mode.)

Note: CS is edge-triggered. HBE, LBE, CLR, SER, CAL, and LDAC are level-triggered.

Using an output multiplexer

The on-board multiplexer allows the user to isolate the load from voltage changes during calibration. To minimize glitch pulses at MUXOUT, the multiplexer input MUXIN should be tied to a voltage equal to the negative full-scale voltage of the DAC. Since the DAC is loaded with the contents of the first stage latches before completing the calibration, the DAC should be programmed to negative full scale prior to calibration. This will minimize the voltage offset of MUXOUT at the beginning and end of calibration. If the fault pulse at the beginning of the calibration is not critical, but the user wishes to minimize the recovery time at MUXOUT, then MUXIN should be set to the voltage corresponding to the data in the first column latches before starting the calibration.

The multiplexer series resistance limits its load drive capability. To obtain 16-bit linearity, MUXOUT must be buffered with a suitable op amp. Amplifier open-loop gain and common-mode rejection contribute to gain errors, and the linearity of these parameters affects relative accuracy (or integral nonlinearity). In general, the linearity of an amplifier is not specified, so its effect must be determined empirically. Using the AD707, as shown in Figure 9, the overall linearity error is within 0.5LSB. The AD707C/T initial voltage offset and its temperature coefficient contribute no more than 0.1lsb to the bipolar zero error over the entire operating temperature range. Settling time for 1/2 lsb is typically 100 microseconds for a 20v step. For applications requiring faster settling, the AD820 can be used to achieve full-scale settling within 1/2 LSB in 20 microseconds. The additional linearity error of the AD820 will be no more than 0.25 LSB.

Use an external multiplexer

An external multiplexer like the ADG419 allows the user to minimize glitch pulses while holding the output at any predetermined voltage during calibration. As shown in Figure 10, the ADG419 can be used with the same high-speed op amp as the AD829 to obtain the fastest possible settling time while maintaining 16-bit linearity. The settling time for a 20v step to 1/2 lsb is typically 10 microseconds.

AD760 to HC11 product parameters, documentation and source information" target="_blank">MC68HC11 (SPI* bus) interface

The interface between AD760 and Motorola SPI (Serial Peripheral Interface) is shown in Figure 11. The MOSI, SCK, and SS pins of the HC11 are connected to the SIN, CS, and LDAC pins of the AD760, respectively. Most interface issues are handled during software initialization. A typical routine, such as the one shown below, starts by initializing the state of the various SPI data and control registers. The most significant data byte (MSBY) is then retrieved from the memory processed by the SENDAT subroutine. The SS pin is driven low by indexing into the PORTD data register and clearing bit 5. The MSBY is then sent to the SPI data register where it is automatically transferred to the AD760.

The HC11 generates the required 8 clock pulses, and the data is valid on the rising edge. After the most significant byte is transferred, the least significant byte (LSBY) is loaded from memory and transferred in a similar fashion. To complete the transfer, the LDAC pin is driven high to latch the complete 16-bit word into the AD760.

AD760 to Microwire Interface

The AD760's flexible serial interface is also compatible with the National Microwire* interface. The MICROWIRE* interface is used on microcontrollers such as the COP400 and COP800 series processors. The general interface of the microwire interface is shown in Figure 12. G1, SK, and SO pins of the microwire interface - connect to the LDAC, CS, and SIN pins of the AD760, respectively.

noise

In high-resolution systems, noise is often the limiting factor. A 16-bit DAC with a 10-volt span has an LSB size of 153 microvolts (–96 dB). Therefore, noise must be kept within *MICROWIRE is a registered trademark of National Semiconductor Corporation.

frequency range of interest. The noise spectral density of the AD760 is shown in Figures 13 and 14. Figure 13 shows the DAC output noise voltage spectral density over the 20 V range (excluding the reference voltage). This graph shows the l/f corner frequency at 100 Hz and broadband noise below 120 mV/Hz. Figure 14 shows the reference broadband noise below

board layout

Designing with high-resolution data converters requires careful attention to board layout. Tracking impedance is the first problem. A current of 306 microamps through 0.5 channel will produce a voltage drop of 153 microvolts, which is 1 LSB at 16-bit level for 10 volts full scale. In addition to ground drop, inductive and capacitive coupling also needs to be considered, especially when high-precision analog signals share a board with digital signals. Finally, to filter out AC noise, the power supply needs to be decoupled.

Analog and digital signals should not share the same path. Each signal should have an appropriate analog or digital loop. Using this method, the signal loop encloses a small area, minimizing the inductive coupling of noise. It is strongly recommended to use wide PC tracks, heavy gauge wires, and ground planes to provide low impedance signal paths. Separate analog and digital ground planes should also be used, with an interconnection point to minimize ground loops. Analog signals should be kept as far away as possible from digital signals and crossed at right angles.

A feature of the AD760 is that the analog pins (VCC, VEE, REF OUT, REF IN, SPAN/BIP OFFSET, VOUT, MUXOUT, MUXIN, and AGND) are adjacent to help isolate analog signals from digital signals.

Power decoupling

The AD760 power supply should be well filtered, well regulated, and free of high frequency noise. Switching power supplies are not recommended because they are prone to spikes that can create noise in analog systems.

Decoupling capacitors should be used in very close layout proximity between all power pins and ground. A 10µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor provides adequate decoupling. VCC and VEE should be bypassed to analog ground, and VLL should be separated from digital ground.

The trace length between the capacitor leads and the corresponding converter power and common pins should be minimized. The circuit layout should try to keep the AD760, associated analog circuits, and interconnect circuits away from the logic circuits. A solid analog ground plane around the AD760 will isolate large switch ground currents. For these reasons, covered wire circuit construction is not recommended; careful printed circuit construction is preferred.

ground

The AD760 has two pins designated as analog ground (AGND) and digital ground (DGND). The analog ground pin is the "high quality" ground reference point for the device. Any external loads on the AD760 output should be returned to analog ground. If using an external reference, it should also be returned to analog ground.

If a single AD760 is used with separate analog and digital ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND, keeping the lead lengths as short as possible. Then connect AGND and DGND to the AD760. If using multiple AD760s or AD760s to share analog power with other components, connect the analog and digital returns together at the power supply rather than at each chip. This single interconnect to ground prevents large ground loops that prevent digital currents from flowing through the analog ground.