feature

to 90mA constant current output; undervoltage lockout; low power CMOS logic and latches; high data input rate; functional replacement for TB62706BN /BF; always order by full part number, eg A6276EA .

The A6276EA and A6276ELW are specially designed for LED display applications. Each BiCMOS device includes a 16-bit CMOS shift register, accompanying data latches and 16 npn constant current sink drivers. The two devices are identical except for the packaging form and the allowable packaging power dissipation. CMOS shift registers and latches allow direct interfacing with microprocessor-based systems. With 5V logic supply, typical serial data input rates are up to 20 MHz. LED drive current is determined by user selection of a single resistor. CMOS serial data output allows for additional drive trains when required. For inter-digit blanking, all output drivers can be disabled to enable input high. Similar 8-bit devices are available as the A6275EA and A6275ELW. For through hole dipping (suffix A) or surface mount SOIC (suffix LW). Under normal conditions, the copper leadframe and low logic power dissipation allow the dual series package to pass the maximum output rated current through all outputs continuously over the operating temperature range (90mA, 0.75V drop, +85°C). Both devices can also be used over the standard operating temperature range of -20°C to +85°C. To order, change the suffix letter "E" to "S".

NOTE: The A6276EA (DIP) and A6276ELW (SOIC) are electrically identical and share a common terminal number assignment.

A. Data activation time before clock pulse (data setup time), tsu (D). . . . . 60 ns

B. Data activation time after clock pulse (data hold time), th(D). . . . . 20 ns

C. Clock pulse width, tw(CK). . . . . . . . . . 50 ns

D. Time between clock activation and latch enable, tsu(L). . . . . . . . . . 100 ns

E. Latch enable pulse width, tw(L). . . . . . . . . . 100 ns

F. Output enable pulse width, tw(OE). . . . . . . . 4.5 microseconds

Note: Timings represent 10 MHz clocks. Higher speeds are achievable. - Maximum clock transition time, tr or tf. . . . . . . 10 microseconds

When latch enable is high (serial-parallel conversion), the information present in any register is transferred to the corresponding latch. The latch will continue to accept new data as long as the latch enable remains high. When the latch is bypassed (latch enable tied high), the output enable input will demand high during serial data input.

When the output enable input is high, the output source driver is disabled (turned off). The information stored in the latches is not affected by the output enable input. When the output enable input is low, the outputs are controlled by the state of their respective latches.

Allowable output current of duty cycle A6276EA A6276ELW

Allowed output current as a function of duty cycle A6276EA A6276ELW

Terminal description

The products described herein are manufactured under one or more US patents or US patents pending.

Allegro MicroSystems, Inc. reserves the right to deviate from detailed specifications at any time to improve the performance, reliability or manufacturability of its products. Before placing an order, the user is reminded to confirm that the information relied upon is up to date.

Allegro products may not be used as critical components of life support equipment or systems without express written approval.

The information contained herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use, nor for any infringement of third party patents or other rights that may result from its use.

application information

The load current per bit (IO) is set by an external resistor (REXT) as shown in the figure below.

Package Power Dissipation (PD). The maximum allowable package power dissipation is determined as: PD(max) = (150 - TA)/RθJA.

Actual package power dissipation is: PD(act) = dc(VCE 8226 ; IO • 16) + (VDD • IDD).

When the load supply voltage is greater than 3v to 5v, consider the package power dissipation limitations of these devices, or if PD(act) > PD(max), an external voltage reducer (VDROP) should be used.

Load supply voltage (VLED). These devices are designed to operate with driver voltage drop (VCE) of 0.4v to 0.7v and LED forward voltage (VF) of 1.2v to 4.0v. If the voltage on the driver is reduced, the package power dissipation will increase significantly. To minimize package power dissipation, it is recommended to use the lowest possible load supply voltage or set any series drop voltage (VDROP) to: VDROP = VLED - VF - VCE with VDROP = IO RDROP for a single driver, or Zener diode ( VZ), or a series of diode strings (approximately 0.7 V per diode) for a set of drivers. If the available voltage source would cause unacceptable losses and series resistors or diodes are not desirable, a regulator such as the Sanken series SAI or series SI can be used to provide supply voltages as low as 3.3v.

For reference, a typical LED forward voltage is:

Pattern layout. The unit has a common logic ground and power ground terminals. These devices may not function properly if the ground-mode layout contains large common-mode resistors and the voltage between system ground and latch-enable or clock terminals exceeds 2.5 V (due to switching noise).