Description This solution is optimized for high-volume user applications, extending the benefits of transition-mode high-efficiency, low-cost components to higher power ratings than previously possible. By utilizing natural interleaving techniques, the two channels are synchronized to the same frequency as a master channel (ie, no slave channels). This approach provides inherently strong matching, faster response, and ensures that each channel operates in transition mode.
Complete system-level protection features include input undervoltage, output overvoltage, open loop, overload, soft-start, phase fault detection, and thermal shutdown. An additional failsafe Overvoltage Protection (OVP) function protects against shorts to intermediate voltages that, if undetected, could lead to catastrophic equipment failure.
This integrated circuit may be damaged by electrostatic discharge. Texas Instruments recommends taking proper precautions when handling all integrated circuits. Failure to follow proper operation and installation procedures may result in damage.
ESD damage can range from minor performance degradation to complete device failure. Precision integrated circuits can be more susceptible to damage because very small parameter changes can cause the device to not meet its published specifications.

Functional block diagram

Applied Information Operations Theory
The UCC28060 contains control circuits for two boost pulse width modulation (PWM) power converters. The ramping current of the boost-PWM power converter in the boost inductor is proportional to the voltage at the output of the error amplifier. Each power converter then turns off the power MOSFETs until the current in the boost inductor decays to 0, as detected on the zero current sense inputs (ZCDA and ZCDB). Once the inductor current decays to 0, the power converter begins another cycle. This on/off cycle produces a triangular current wave with peak current set by on/off time and power supply input voltage.
Vinyl Acetate(t)´T Open Ipec(t)=
L (a)
The average line current is exactly half the peak line current, as shown in Equation 2.
Vinyl Acetate (t)´T Open
IAVG(tons) =
2´one (two)
When t and L are substantially constant over the AC line cycle, the triangular current waveform produced during each switching cycle has an average value proportional to the instantaneous value of the rectified AC line voltage. This configuration produces a resistive input impedance characteristic at line frequency and near unity power factor.
The outputs of the two PWMs run 180 degrees out of phase, so the power line ripple current for both PWMs is greatly reduced from the ripple current for each individual PWM. This design reduces the ripple current at the input and output, thereby reducing the size and cost of the input and output filters.
The best phase balance occurs if the individual power levels and turn-on times are well matched. Inductor value mismatch does not affect the phase relationship.
Timing control, maximum frequency limit, and restart timer The gate drive turn-on time varies with the error amplifier output voltage by a factor called KT
t = K (VT compressor -125 mV) (3)
VCOMP is the output of the error amplifier and 125mV is the modulator offset.
To compensate for the effect of line voltage variation on loop gain, KT is three times larger in the low line range than in the high line range
K=3 K TL TH (4 pieces)
To provide a smooth transition between two-phase and single-phase operation, KT is increased by a factor of 2 in single-phase mode:
KTHS = 2 x KTH; active at high line range and single-phase operation
KTL = 2 × KTL; the clamped maximum output of the activated error amplifier is limited to 4.95 V in low line range and single-phase operation. This value, less than the 125 mV modulator offset, limits the on-time of Equation 5.
t(max) = KT'4.825V(5)
This on-time limit sets the maximum power delivered by the converter at a given input voltage level.
The switching frequency of each phase is limited by the minimum period timer. If the current decays to 0 before the minimum period timer expires, the turn-on is delayed, resulting in discontinuous phase current.
The restart timer ensures start-up under all conditions and restarts both phases if the input of both phases does not transition to approximately 200 kV s to prevent the circuit from operating in continuous conduction mode (CCM), restart time Turn-on will not be triggered until both phase currents return to 0.
Application Materials (continued)
The time factor (KTH, KTHS, KTL, KTLS) and the minimum switching period TMIN are proportional to the time setting resistor RTSET. The resistance from the test pin to ground is given by Equation 6 to Equation 8:
RTSET Mass Spectrometer
KTH = 1.35 miles; valid in high end range
133 kW Volts (6)
RTSET Mass Spectrometer
KTL=4.0; valid in the low end range of 133kw V(7)
RTSET device
TMIN = 2.2ms; minimum switching cycle 133kw (8)
The correct value of RTSET clamps the maximum on-time, Ton(max), required by the converter operating at minimum input line and maximum load.
Natural Interleaving Under normal operating conditions, the UCC28060 adjusts the relative phase of the channel A and channel B inductor currents very close to 180 degrees, thereby minimizing the ripple current seen at the line source and output capacitor. The phase control function differentially modulates the on-time of the A and B channels according to the phase and frequency relationship. This natural interleaving approach allows the converter to achieve 180° phase shift of the two phases and transition mode operation without requiring the tolerance of the boost inductor. As a result, the current sharing of the a and B channels is proportional to the inductance tolerance. The best current sharing is achieved when the two inductance values are exactly the same.
Easy Stage Management Under light load conditions, due to small current conduction losses and large switching losses due to MOSFET junction capacitance discharge, turning off one of the power stages can reduce switching losses and increase conduction losses. At a certain power level, the reduction in switching losses is greater than the increase in conduction losses, and better efficiency can be achieved. This feature is one of the main benefits of interleaved power function correction (PFC) and is especially valuable for meeting light-load efficiency standard design requirements.
The Easy Phase Management feature allows the user to shut down one of the power stages by connecting the COMP pin to the PHB pin for higher efficiency at light load conditions. On the basis of theoretical analysis and experimental results, the UC28060 preset phase management threshold can achieve the maximum efficiency improvement. Depending on the COMP pin voltage, easy phase management switches off phase B at the corresponding power stage. Table 1 lists the thresholds and corresponding power levels.

The PHB pins can also be driven by external logic signals to allow custom phase management. To disable phase management, connect the PHB pin to the VREF pin.
Zero-Crossing Detection and Valley Switching In a transition-mode PFC circuit, the MOSFET turns on when the boost inductor current crosses zero. Due to the resonance between the boost inductor and the parasitic capacitance of the MOSFET drain node, part of the energy stored in the MOSFET junction capacitance can be recovered, reducing switching losses. In addition, when the rectified input voltage is less than half of the output voltage, the energy stored in the MOSFET junction capacitor can be fully recovered, enabling zero-voltage switching (ZVS). By adding an appropriate delay, the MOSFET can be turned on at the valley of its resonant drain voltage (valley switching). In this way, energy recovery can be maximized and switching losses minimized.
The RC time constant is usually derived empirically, but a good starting point is a value equal to 25% of the resonant period of the drain circuit. Delay can be achieved with a simple RC filter. Because the ZCD pin is clamped internally, a more precise delay can also be achieved using Figure 28.
Simple RC Delay Circuit More Accurate Delay Circuit Gate Driver Design In transition mode operation, the turn-on and turn-off speeds of the MOSFETs are designed differently. Due to the large turn-off current, higher speed is required to reduce turn-off losses while still controlling the speed to reduce voltage spikes on the mosfet. When turned on, the slower the better. Due to the presence of zero current switching, slow turn-on speed does not significantly change switching losses, while when zero voltage switching is not achieved, it can significantly reduce dv/dt, especially for high input lines. This controlled dv/dt greatly reduces common-mode EMI noise and simplifies filter design. Therefore, the boot speed should be as slow as possible without reducing the overall efficiency of the system.
Use a series gate resistor between 5Ω and 15Ω to prevent EMI, ringing, and noise in the system. If ringing, EMI, or system noise is excessive, increase the resistance. To improve power supply efficiency, it may be beneficial to reduce resistance. To optimize efficiency and noise performance, parallel resistors and diodes can be used to increase turn-off speed while maintaining slow turn-off Optional gate drive circuit eyebrow protection As the supply line rms voltage decreases, the rms input current increases, to keep the output voltage constant for a specific load. Overvoltage protection prevents RMS input current from exceeding safe operating levels. Power line rms voltage detected at VINAC. When the voltage applied to VINAC does not exceed the power-on threshold within the power-on filter time, a power-on state is detected and both gate drive outputs are pulled low immediately. During the brownout period, COMP is actively pulled low. The gate drive output remains low until the voltage on VINAC rises above the threshold. After a brownout, COMP rises when the power stage is soft-started.
Fault Protection Over Voltage Protection The fault protection OVP prevents any single fault from raising the output above a safe level. Redundant paths for output voltage sensing provide additional output overvoltage protection. Overvoltage protection is achieved through two independent paths: VSENSE and HVSEN. If an overvoltage condition is detected on either input, the converter will shut down. In the event of failure of either circuit, the output voltage remains at a safe level. When both sense inputs return to normal range, the IC is re-enabled. At this point, the gate drive output resumes switching under PWM control. Output overvoltage will not cause soft-start, and the COMP pin will not discharge during an output overvoltage event.
Overcurrent Protection Under certain conditions (such as inrush current, overvoltage recovery, and output overload), the power factor corrected power stage draws high currents. In this case, it is critical to protect the power supply from being switched.
Traditional current sensing methods use a parallel resistor in series with the MOSFET source to sense the converter's current, resulting in multiple ground points and high power dissipation. Furthermore, since no current information is available when the mosfet is turned off, the source-resistive current sensing method requires the mosfet to be turned on repeatedly under overcurrent conditions. Therefore, the converter may temporarily operate in continuous current mode (CCM) and experience a fault caused by excessive reverse recovery current in the boost diode.
The UCC28060 continuously senses the total inductor (input) current using a single resistor. In this way, energization of the mosfet is completely avoided when the inductor current is too large. Drive to the mosfet is suppressed until the total inductor current drops to near zero, ruling out faults caused by reverse recovery (these faults are most likely to occur when the AC line recovers from a power outage).
During an overcurrent condition, when the input current drops close to 0, the two mosfets turn on in phase. Since the two-phase current operates temporarily on the phases, the overcurrent protection threshold is set to more than twice the maximum current ripple value per phase to allow normal operation to resume after an overcurrent event.
Phase loss protection
The UCC28060 detects single-phase faults by monitoring the ZCD pulse train. In normal two-phase operation, if one input is idle for more than about 14 milliseconds while the other 8-bit inputs switch normally, the input voltage is too high, indicating that the power stage is not functioning properly. During normal single-phase operation, phase faults are not monitored.
Distortion reduction Due to the resonance of the capacitance between the drain-source of the switching MOSFET and the boost inductor, when the input voltage is around 0v, the traditional transition mode power factor correction circuit may not be able to draw power from the input line, this limitation causes waveform distortion and harmonic distortion increases. To reduce line current distortion to the lowest possible level, the UCC28060 increases the on-time of the switching MOSFET at input voltages around 0v to increase power absorption and compensate for this effect.
Improved Error Amplifier The voltage error amplifier is a transconductance amplifier. The voltage loop compensation is connected from the error amplifier output COMP to the analog ground AGND.

Typical Error Amplifier Compensation To improve transient response, the error amplifier output current is increased by 100 microamps when the error amplifier input is below 5.815v. This increase allows faster charging of the compensation components after a sudden increase in load current. Error Amplifier Block Diagram with Soft Start Open-Loop Protection If the feedback loop is disconnected from the IC, a current source inside the UCC28060 pulls the VSENSE pin voltage toward ground. When VSENSE is below 1.20 V, the IC is disabled. When disabled, the supply current is reduced and both the gate drive output and COMP are actively pulled low. When VSENSE rises above 1.25 V, the IC is re-enabled. At this point, the gate drive output starts to switch under PWM control.
The IC can be disabled externally by connecting the VSENSE pin to ground using an open-drain or open-collector driver. When disabled, the IC supply current drops and COMP is actively pulled low. When VSENSE is released, the IC soft-starts. This disabling method forces the integrated circuit into a standby mode and minimizes its power consumption. This feature is especially useful when backup power is a critical design aspect.
If the feedback loop is disconnected from ground, the VSENSE voltage will go high. When VSENSE rises above the overvoltage protection threshold, both gate drive outputs go low and COMP is actively pulled low. When VSENSE returns to range, the IC is re-enabled. At this point, the gate drive output starts to switch under PWM control. In this case, the VSENSE pin is clamped internally to protect the IC from damage.
Soft-Start As the compensation capacitor charges from COMP to AGND from low to final value, the PWM gradually transitions from zero on-time to normal on-time. This process achieves a soft-start with a time constant set by the output current of the error amplifier and the value of the compensation capacitor. In the event of a power-down, logic disable, or VCC undervoltage fault, COMP will be actively pulled low, so after this event is cleared, the PWM soft-starts. Soft-start ensures soft-start by fully discharging the compensation components before resuming operation, even if the fault event is short-lived.
Light Load Operation As the load current decreases, the error amplifier reduces the input current by lowering the COMP voltage. If the PHB (usually connected to COMP) goes below 0.8v on the low input line (or 1.1v on the high input line), channel B stops switching and channel A is on for double the time to compensate. If COMP falls below 150 mV, Channel A also stops switching and the loop enters hysteretic control mode. Pulse width modulation skips cycles to maintain regulation.
Downstream Converter Instructions In the UCC28060, the PWMCNTL pin is used to coordinate the PFC stage with the downstream converter. The output voltage is detected by the HVSEN pin. When the output voltage is within the desired range, the PWMCNTL pin is pulled to internal ground and can be used to enable downstream converters. Enable threshold and hysteresis can be independently adjusted by divider ratio and resistor value. The HVSEN pin is also used for fault protection over voltage protection. When designing the voltage divider, be sure to set the failsafe overvoltage protection level higher than the normal operating level.
VCC undervoltage protection
VCC must rise above the undervoltage threshold for the PWM to start working. If VCC falls below the threshold during operation, both the gate drive output and COMP are actively pulled low. VCC must rise above the threshold to restart the PWM function.
VCC
VCC is connected to a bias supply between 13 V and 21 V. When powered by a poorly regulated supply, an external Zener diode is recommended to prevent excessive current flowing into VCC.
Overvoltage protection and line distance detection
VINAC is connected to a voltage divider at the rectified supply input, providing undervoltage detection and selection of low or high supply operation. The browser timer asserts the browser state when the VINAC peak voltage is below the browser detection threshold for longer than the browser filtering time. The fault protection is cleared when the VINAC peak voltage is above the fault recovery threshold. After soft-start, the circuit resumes normal operation.
The voltage divider ratio and resistor value determine the voltage mutation detection threshold and its hysteresis. This pin also senses the input line range to set the corresponding on-time factor. Overvoltage protection and distance detection are both based on VINAC peak voltage; threshold and hysteresis are also based on peak voltage. The peak voltage can be easily converted to an rms value. The suggested resistor values for the voltage divider are: 3 MΩ ±1% from the rectified input voltage to VINAC and 46.4 kΩ ±1% from VINAC to ground. These resistors set the typical threshold for rms line voltage

The recommended PCB device layout staggered transition mode PFC system structure greatly reduces the input and output ripple current, enabling the circuit to use smaller, less expensive filters. To maximize the benefits of interleaving, the input and output filter capacitors should be located after the two phase currents are combined. Similar to other power management ICs, when laying out the printed circuit board (PCB) it is imperative to use a star ground technique and ground the filter capacitors as close to the IC as possible. To minimize interference from capacitive coupling from the boost inductor, the IC should be located at least 1 in (25.4 mm) from the boost inductor. It is also recommended not to place integrated circuits under magnetic components. Due to precise timing requirements, the timing setting resistor RTSET should be placed as close as possible to the TSET pin and back to analog ground.

Inductor Selection The boost inductor is selected based on the requirements of the low line peak inductor ripple current. Selecting the inductor requires calculating the boost converter duty cycle at the peak of the low voltage line (DPEAK_low_line), as shown in Equation 9.
VOUT-VINêMINê2 390V-85V
DPEAK_LOW_LINE=0.69
Voltage 390 Volts (9)
The converter's minimum switching frequency (fMIN) occurs at the peak of the low-side line and is set between 25 kHz and 50 kHz to avoid hearing noise. For this design example, fMIN is set to 45 kHz:
h' five in minutes 2 x axis peak low line 0.92 (85 volts) 0.692
L1=L2==340 hours»m
POUT'fMIN 300 watts 45 kHz (10)
The peak current (ILPEAK) of this designed inductor is 5.4 a, as shown in Equation 11, while the root mean square current (ILRMS) is 2.2 a,.
POUTÖ2 300 Watt Ö2
ILPEAK==? 5.4A, 85V minimum, 0.92 (11)
I L peak 5.4 A
I==; 2.2A
The converter of LRMS Company uses constant conduction (TON) and zero current switching (ZCS) to set the timing of the converter. The auxiliary windings of L1 and L2 detect when the inductor current is 0. The turns ratio in Equation 13 is chosen to ensure that at least 2v is available at the peak of the high line to reset the ZCD comparator after each switching cycle.
The turns ratio of each auxiliary winding is:
S 2 volts 2 volts (13)
ZCD Resistor Selection (RZA, RZB)
The minimum value of the ZCD resistor was chosen based on the internal Zener clamp's maximum current rating of 5mA.
VN type
Output S 390 V
R=R3=10kw zazip
N'5mA 8'5mA
Page (14)
In this design, the ZCD resistor is set to 20kΩ
R=R=20kW ZA ZP(15)
Hefsons
The HVSENSE pin programs the PWMCNTL output of the UCC28060. The PWMCNTL open-drain output can be used to disable downstream converters when the PFC output capacitor is charged. PWMCNTL starts up with high impedance and is pulled to ground when HVSENSE increases above 2.5v. Setting the point at which PWMCNTL activates requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 16 to Equation 20 illustrate how to set the PWMCNTL pin to the active state when the output voltage is within 90% of its nominal value.
VOUT_OK = VOUT' 0.90? 351 volts (16)
The resistor resets the high side of the divider and programs the hysteresis of the PWMCNTL signal. For this example, RE is selected to provide a hysteresis resistor of 99 V. RF is used to program the PWMCNTL activation threshold. The PWMCNTRL output remains activated until the minimum output voltage (VOUT_MIN) is reached,
2.5V (R+RE F) 2.5V (3MW+30kW)
VOUT_MIN==? 252 Volt RF 30 kW (19)
Based on the resistor value, the fault protection OVP threshold should be set according to Equation 20:
4.87V (R+RE F) 4.87V (3MW+30kW)
VOV_FAULT_PROTECTION = 487V
RF 30 kW (20)
OUTPUT CAPACITOR SELECTION The output capacitor (COUT) is selected based on the holdup requirements, as shown in Equation 21.
POUT 1 300 wide 1
0.92 47 Hz Coot 3 2 2 2 2 ? 156 MF
VOUT - (VOUT_MIN) 390 volts - (252 volts) (21)
Two 100µF capacitors in parallel for the output capacitor:
COUT=200 microfiltration (22)
For a capacitor of this size, the output voltage ripple (V ripple) is about 11 V
VRIPPLE==11 volts »
High 0.637V 4p Forint x High 0.92V 0.637V 390V 4p 47Hz 200µV (23)
In addition to the holdup requirements, the capacitor must be selected to withstand both low frequency rms current (ICOUT_100 Hz) and high frequency rms current (ICOUT_HF); see Equation 24 through Equation 26. High voltage electrolytic capacitors typically have low frequency and high frequency rms current ratings on the product data sheet.