1.0 main functions Fully programmable control via I2C 8482 ; bus selectable CMOS or PECL compatible output External feedback loop function allows generator lock Tunable VCXO loop for jitter attenuation

2.0 General Description The FS6131-01 is a monolithic CMOS clock generator/regenerator integrated circuit designed for use in various electronic systems. Through the I2C bus interface, the FS6131-01 can accommodate a variety of clock generation requirements. The ability to adjust the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feedback dividers, and the flexibility of granularity and postscaler make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock. Generator available.

3.0 Applications Frequency Synthesis Line Lock and Genlock Applications Clock Multiplication Telecom Jitter Attenuation

4.0 Function block description 4.1 Main loop PLL The main loop phase-locked loop (ML-PLL) is a standard phase-locked loop and frequency phase-locked loop structure. As shown by the error! Reference source not found. The ML-PLL consists of a reference divider, a phase frequency detector (PFD), a charge pump, an internal loop filter, a voltage controlled oscillator (VCO), a feedback divider, and a postscaler. During operation, the reference frequency (fREF) generated by the on-board crystal oscillator or external frequency source is first reduced by the reference voltage divider. The integer value by which the frequency is divided is called the modulus and is represented as a reference divider. The segmented reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through a charge pump and loop filter. The VCO provides a high-speed, low-noise, continuously variable frequency clock source for ML-PLLs. The output of the VCO is fed back to the PFD divider (modulo is denoted by NF) through the feedback feedback to close the loop. The PFD will drive the VCO frequency up or down until the divided reference frequency and divided VCO frequency appear equal at the input of the PFD. The input/output relationship between the reference frequency and the VCO frequency is

4.1.1. Reference divider The reference divider is designed for low phase jitter. The divider accepts either the output of the crystal loop (VCXO output) or an external reference frequency and provides a down-divided frequency to the PFD. The reference divider is a 12-bit divider and can be programmed to any modulus from 1 to 4095 . See Table 3 and Table 8. Clause 4.1.2 for additional programming information. Feedback Divider The feedback divider is based on a dual-modulus prescaler technique. This technique allows for a fully programmable feedback divider while still allowing the programmable part to operate at low speed. A high-speed prescaler (also called a prescaler), due to the high speed of the VCO, is placed between the VCO and the programmable feedback divider to operate. Dual-mode technology ensures reliable operation of the VCO at any speed and reduces the power consumption of the voltage divider. For example, a fixed division of 8 can be used in the feedback divider. Unfortunately, dividing by 8 limits the modulus of the feedback divider path to multiples of 8. This limitation will limit the ability of the PLL to achieve the desired input-to-output frequency ratio without making both the reference and feedback divider values relatively large. Large dividers usually do not require modulo due to increased phase jitter.

To learn what to do, see Errors! Reference source not found. . M counter (modulo M) with dual modulo prescaler. If the prescaler modulus is fixed at N, the total modulus of the feedback divider chain will be MXN. However, the A counter causes the prescaler modulus to change to N+1 in the prescaler's first A output. The A-counter restores the dual modulo prescaler to modulo N until the M counter reaches its terminal state and resets the entire delimiter. The total modulus can be expressed as

4.1.3. The requirement to program the feedback divider M≥A means that the feedback divider can only be programmed to some value less than the divider modulo 56. The choice of divider value is shown in Table 2. If the desired feedback divider is less than 56, look up the divider value in the table. Find A counter program value by column. Find the M counter value along the left row. Above a modulo of 56, the feedback divider can be programmed to any value below 16383. See Table 3 and Table 8 for other programming information.

Change the voltage on the XTUNE pin. The total change in effective load capacitance (from one extreme to the other) is 1.5pF nominally, the effect is wrong! Reference source not found. . The oscillator operates the crystal resonator in parallel resonance mode. Crystal warping, or "pulling" of the crystal's oscillation frequency, is the capacitance supplied to the crystal by the oscillator circuit by changing the payload. The actual amount by which changing the load capacitance changes the oscillator frequency will depend on the characteristics of the crystal as well as the oscillator circuit itself. The crystal's moving capacitance (often referred to as C1 by crystal manufacturers), the crystal's static capacitance (C0), and the oscillator's load capacitance determine the crystal's ability to warp in the oscillator circuit. A simple formula to determine the total warpage capacity of a crystal is

where CL1 and CL2 are the two extreme values of the applied load capacitance obtained from Table 11. Example: A crystal with the following parameters is used for the FS6131. The total coarse adjustment range is:

The VCXO can be coarsely tuned by programmable adjustment of the crystal load capacitance through the XCT[3:0] control bits. See Table 11 for the control code and associated load capacitance. The actual amount of frequency distortion caused by the tuning capacitor will depend on the crystal used. The VCXO tuning capacitors include an external 6pF load capacitor (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The trim feature of this VCXO can be enabled by setting the XLVTEN bit to 1 or disabled by setting it to 0. mistake! Reference source not found. Typical effects of coarse and fine-tuning mechanisms are shown. The total coarse tuning range is about 350 ppm. The parts per million (ppm) difference in VCXO frequency is shown as the trim voltage on the XTUNE pin varies from 0V to 5V. Note that as the crystal load capacitance increases, the frequency of the VCXO decreases with coarse steps and fine-tuning range. The fine-tuning range always overlaps with some coarse fine-tuning range, eliminating possible holes in the VCXO's response. Different crystal warping properties can alter the scaling on the Y-axis, but not. General characteristics of the curve.

4.5 Crystal Ring This crystal ring is designed to attenuate jitter on high jitter, low Q, low frequency references. The crystal loop can also maintain a constant frequency output of the main loop if the low frequency reference is intermittent. The crystal loop consists of a voltage-controlled crystal oscillator (VCXO), a frequency divider, a PFD, and a charge pump that tunes the VCXO to form a frequency reference. The frequency reference is phase-locked to a divider of an external high-Q jitter-free crystal, which locks the VCXO to the reference frequency. The VCXO can continue to escape from the crystal even if the frequency reference becomes intermittent. 4.5.1. Lock to External Frequency Source When the crystal loop is synchronized with an external frequency source, the FS6131 can monitor the crystal loop and detect if the loop is unlocked from the external source. If the external power is disconnected, the crystal loop will try to drive to zero frequency and set a lock status error flag. The crystal loop can also detect if the VCXO has come out of fine tuning range and needs to be changed to coarse tuning. The lock state also locks the direction of out of range (high or low) when the loop is unlocked. 4.5.1.1 Crystal Ring Lock Status Flag To enable this mode, clear the STAT[1] and STAT[0] bits to zero. If the CMOS bit is set to 1, if the crystal ring is unlocked. This flag is always available under software control by reading the STAT[1] bit, i.e. overriding with a status flag (low = unlocked) in this mode (see table). 4.5.1.2 Out of Range High/Low The direction of looping out of range can be determined by clearing STAT[1] to zero and setting the STAT[0] bit to 1. If the CMOS bit is set to 1, the LOCK/IPRG pin will go high if the crystal loop is out of range. If the pin goes logic low, the loop is out of range low. Under software control, out-of-range information can also be obtained by reading the STAT[1] bit, which is covered by flags (high = out-of-range high, low = out-of-range low) in this mode. This bit is only set or cleared when the crystal loop loses lock (see table).

4.5.1.3 Crystal Loop Disable The crystal loop is disabled by setting the XLPDEN bit to logic high (1). This bit disables the charge pump circuit in the loop. Setting the XLPDEN bit low (0) allows the crystal ring to operate as a control ring. 4.6 Connect the FS6131 to an external reference frequency If a crystal oscillator is not used, ground XIN and turn off the crystal oscillator by setting XLROM[2:0]=1. The REF and FBK pins have no pull-up or pull-down current, but have a small amount of hysteresis to reduce extra edges. Signals can be AC coupled to these inputs through an external DC bias circuit to produce a DC bias of 2.5V. The reference or feedback signal should be square for best results and the signal should be rail-to-rail. Unused inputs should be grounded to avoid unwanted signal injection. 4.7 Differential output stage The differential output stage supports both CMOS and pseudo ECL (PECL) signals. The desired output interface is through program registers (see table). If a PECL interface is used, a Thévenin termination is usually used to terminate the transmission line. The output stage can sink only the current in PECL mode, and the sinking current set by the programming resistor on the LOCK/IPRG pin. The current of the IPRG ratio output drive current is shown in the figure. The source current is terminated by a pull-up resistor that is part of Thévenin.