feature

Low power consumption with minimal impact on battery life – Multiple power down modes – AC-coupled with DC balancing 100nA in standby mode, 5mA typical operation

condition

Cable Reduction Ratio: 25:4 or greater bidirectional operation 50:7 or greater Differential Signaling: – -90dBm EMI when using CTL under laboratory conditions using near field probes – Minimize shielding – Minimize EMI filters – To external interference Minimum Sensitivity of Up to 22 Bits in Any Direction Up to 20MHz Parallel Interface Operating Voltage Conversion from 1.65V to 3.6V Ultra-Small and Cost-Effective Package High ESD Protection: >8kV HBM Parallel I/O Power Supply (VDDP) ranging from 1.65V to 3.6 volts

application

Microcontrollers or Pixel Interface Image Sensors Small Displays – LCDs, Cell Phones, Digital Cameras, Portable Game Consoles, Printers, PDAs, Video Cameras, Automotive

General Instructions

FIN24AC μSerDes 8482 ; is a low power serializer/deserializer (SerDes) that can help minimize cost and the ability to transmit wide signal paths. By using serialization, the number of signals transmitted from one point to another can be significantly reduced. Typical reduction ratios for unidirectional paths are 4:1 to 6:1. For bidirectional operation, the signal reduction can be increased to nearly 10:1 using a half-duplex source. By using differential signaling, shielding and EMI filters can also be minimized, further reducing the cost of serialization. Differential signaling is also important to provide a noise-insensitive signal that can withstand radio and electrical noise sources. The dramatic reduction in power consumption makes an impact on battery life in ultraportable applications. A unique word boundary technology ensures word boundaries are identified when deserializing data. This ensures that each word is properly aligned in the deserializer word by word through a unique sequence of clocks and data that does not repeat except word boundaries. One PLL is sufficient for most applications, including bidirectional operation.

Control logic: FIN24AC can be used as a 24-bit serializer or a 24-bit deserializer. Pins S1 and S2 must be set to accommodate the range of the clock reference input frequency serializer. Table 1 shows the pin programming pins for these options based on the S1 and S2 controls. The DIRI pin controls whether the device is a serializer or deserializer. The device is configured as a deserializer when DIRI is asserted low. When the pin is asserted high, the device is configured as a serializer. Changing the state of the DIRI signal reverses the direction of the I/O signal and produces the opposite state signal on DIRO. For unidirectional operation the DIRI pin should be hardwired to a high or low state. The DIRI pin should be floating. For bidirectional operation, the master's directory is the directory used to drive the slave device driven by the DIRO signal of the system and the host. Serializer/Deserializer Variation with dedicated I/O Serialization and deserialization circuitry is 24-bit. Due to dedicated inputs and outputs, only 22 bits of data are serialized or deserialized. Regardless of the mode of operation, the serializer always sends 24-bit data and the two boundary bits The deserializer always receives 24-bit data on the boundary of two words. Bits 23 and 24 of the serializer always contain a value of 0 and are discarded by the deserializer. The input to the DP[21:22] serializer is deserialized to DP[23:24] respectively.

The U-turn function device is asynchronous to the DIRO signal by passing and inverting the DIRI signal device. Care must be taken during design to ensure that no contention occurs between deserializer output and other devices on this port. Peripherals driving the serializer should preferably be in a high impedance state before the DIRI signal is asserted. When a device with private data output goes from deserializer to serializer, the private output remains at the last logical value of the assertion. This value will only change if the device is converted to a deserializer again and the value is overwritten. Shutdown Mode: (Mode 0) Mode 0 is used to power off and reset the unit. When both mode signals are driven low, the PLL and reference are disabled, the differential input buffers are turned off, the differential output buffers are turned off and placed in a high-impedance state, the LVCMOS outputs are in a high-impedance state, and the LVCMOS inputs are driven internally to a valid level, all internal circuits are reset. Loss of CKREF state is also enabled to ensure that the PLL is only present when a valid CKREF signal is present. In a typical application, the signal does not change other states between the desired frequency range and power-down mode. This allows system-level power outages through a single wire to achieve the functionality of the seds pair. Operating modes that have them driven to "logic 0" should be hardwired to GND. The S1 and S2 signals should be connected to the operating mode system level power down signals that are driven to "logic 1".

Serializer Operation Mode Serializer configuration is described in the following sections. The basic serial circuit works basically the same in these modes, but the actual data flow and clock flow depends on whether CKREF is connected to a strobe signal or not. When CKREF is equal to strobe, the CKREF and strobe signals have the same operating frequency, but may or may not be phase aligned. When CKREF is not equal to strobe, each signal is different and CKREF must run at a high enough frequency to avoid any data loss conditions. CKREF must never be lower than the strobe frequency.

A phase-locked loop (PLL) must receive a stable CKREF signal to achieve lock before any valid data is sent. The CKREF signal can be used as a data strobe signal, provided that the data can be ignored during the phase locked loop lock phase. Once the PLL is stable and locked, the device can begin capturing and serializing data. Data is captured and serialized on the rising edge of the strobe signal. Serialized data stream with bit clocks embedded in word boundaries. In this mode, the internal deserializer circuits are disabled; including serial clock, serial data input buffer, bidirectional parallel output, and CKP word clock. The CKP word clock is on high.

If the same signal is not used for CKREF and STROBE, the CKREF signal must run at a frequency higher than the strobe rate to serialize the data correctly. The actual serial transfer rate remains at 26 times the CKREF frequency. Data A value of zero is sent when no valid data is present in the serial bit stream. This otherwise serializer's operation will remain unchanged. The exact frequency required for the reference clock depends on the stability of the CKREF and strobe signals. The maximum frequency for this spread spectrum if the source of the CKREF signal implements spread spectrum techniques. When calculating the strobe frequency and the CKREF frequency. Similarly, if the strobe signal has significant cycle variation, the maximum cycle-to-cycle time needs to be broken down to select the CKREF frequency.

A third serialization method can be implemented on the CKSI signal with a free-running bit clock. This mode works by grounding the CKREF signal and driving the DIRI signal high. At power-up, the device is configured to accept a serialized clock from CKSI. This device will enable CKREF serialization mode if a CKREF is received. The device remains in this mode even if CKREF is stopped. To re-enable this mode, the device must be powered off and the reference restarted with "logic 0" on.

Embedded Word Clock Operation The FIN24AC transmits and receives serial data sources synchronized to the bit clock. The bit clock has been modified to create word boundaries at the end of each word Data word word boundaries have been implemented to skip a low clock pulse. This occurs in a sequence where the clock stream is continuous 3 bit times, where the signal CKSO is still high. To implement this scheme, two additional data bits are required. During the word boundary phase, the data switches to high then low or low then high depending on the last bit of the actual data word. Table 2 provides some actual data words and data words with word boundary bits added. Note that during serial transfers, 24-bit words are expanded to 26 bits. Bits 25 and 26 are defined relative to bit 24. Bit 25 is always the reciprocal of bit 24, and bit 26 is always the same as bit 24. This ensures that "0"→"1" and "1"-"0" transitions are always in the embedded word stage with CKSO high. The serializer generates and embeds word boundary data bits and boundary clock conditions into the serial data stream. The deserializer looks for the word boundary condition data at the end to capture and transfer to the parallel port. The deserializer only uses the data to find and capture. These boundary bits are in the words sent to the parallel port. The LVCMOS data I/OLVCMOS input buffers have nominal thresholds equal to half VDDP. Input buffers are only operational when the device is running as a serializer.

When the device is running as a deserializer, the input is turned off to save power. The LVCMOS tri-state output buffers are rated for 2mA source/sink current at 1.8V, and the output is active when the DIRI signal is asserted low. When the DIRI signal is asserted high, the bidirectional LVCMOS I/O is in the high-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. Unused LVCMOS input buffers must be tied to an active logic low or active logic high to prevent quiescent current consumption caused by floating inputs. Unused LVCMOS outputs should be left floating. Unused bidirectional pins should be connected to GND with a high value resistor. If the FIN24AC device is configured as a unidirectional serializer, unused data I/O can be treated as unused input. If FIN24AC is hardwired as a deserializer, unused data I/O can be treated as unused output.

The differential I/O circuit FIN24AC adopts FSC's proprietary CTL I/O technology. CTL is a low power, low EMI, differential swing I/O technology. The CTL output driver generates a constant output source and sink current. The CTL input receiver senses current difference and direction from its connected output buffer. This is the same as LVDS, which uses a constant current source output, but a voltage sense receiver. As with LVDs, an input source termination resistor is required to properly terminate the transmission line. The FIN24AC device contains internal termination resistors on the CKSI receiver and gated internal termination resistors on the DS input receiver. Gated termination resistors ensure termination regardless of the direction of data flow. The relatively high sensitivity of the current sensor CTL allows it to be driven at lower currents and lower voltages. In power-down mode, the differential input is disabled and powered down, and the differential output is in a high-Z state. The CTL inputs have an inherent failsafe feature that supports floating inputs. when? The serializer's CKSI input pair is unused, it can be left floating reliably. Or both inputs can be grounded. The CTL input can never be connected to VDD. It should be allowed to float when the deserializer's CKSO output is unused.

The phase locked loop circuit CKREF input signal is used to provide the PLL. The PLL generates internal timing signals capable of transmitting data signals at 26 times the speed of the input CKREF. The output of the PLL is a bit clock, which is used to serialize the data. The bit clock is also sent to the source in synchronization with the serial data stream. There are two ways to disable the PLL: enter the Mode 0 state (S1=S2=0) or by detecting the low power-on S1 and S2 signals. When others enter the mode by asserting S1 or S2 HIGH by supplying the CKREF signal. The phase-locked loop is powered up through a locking sequence. The parallel port waits the specified number of clock cycles before capturing valid data. When the μSerDes chipset transitions from a powered-off state (S1, S2=0, 0) to a powered-on state (example S1, S2=1, 1), CKP on the deserializer transitions low for a short time, then returns high. After that, the signal level of the deserializer at CKP corresponds to the serializer signal level. Another way to turn off the PLL is to stop the CKREF signal (high or low). Internal circuitry detects the lack of conversion and turns off the PLL serial I/O off. However, the internal reference is not disabled, allowing the PLL to power up and relock in fewer clock cycles than exiting mode 0. When a transition is seen on the CKREF signal, the PLL reactivates.

The figure shows the basic operation when configuring a pair of SerDes in one-way operation mode. In main operation, the device: 1. Configured as a serializer at power-on, based on the value of the DIRI signal. 2. Accepts the CKREF M-word clock and generates a clock with bits embedded in the word boundary. This bit clock is sent to the slave device through the CKSO port. 3. Receive parallel data strobe on the rising edge of . 4. Generate and transmit serialized data on DS signal source synchronized with CKSO. 5. Generate an embedded word clock signal for each strobe. In slave operation, the device: 1. Configured as a deserializer at boot, based on the value of the DIRI signal. 2. Accepts embedded word boundary bit clock Kerxi. 3. Deserialize the DS stream clock using the CKSI input. 4. Write parallel data to DP_S port and generate data word only when valid.

Figure shows a half-duplex connection diagram. This connection allows two unidirectional data streams to be sent through a pair of SerDes devices. Data is sent frame by frame. For this mode, there must be synchronization data between the camera sending the data frame and the LCD sending the data frame. One option is to have the LCD in the camera blanking period. External logic may be required for this mode of operation. Alternate device control and sense of direction by a direction-controlled data frame. When DIRI is high on the right FIN24AC, data is sent from the camera to the camera interface on the bottom. When FIN24AC on the right goes low, it is sent from the baseband process to the LCD. Then change direction to Diro on the right hand side, FIN24AC, and change direction to FIN24AC on the left hand side. Data has been sent from the base LCD unit to the LCD. The FIN24AC on the left side of the Diro pin above is used to indicate the direction of the signal to the basic controls to change the direction of the unit and the LCD can be used to receive data. On the right is the Diri FIN24AC that can usually use a timing reference signal, such as VSYNC from the camera interface, to indicate orientation changes. The derivative of this signal may be required to ensure that there is no data loss transfer in the final data.

Flexible Circuit Design Guidelines Serial I/O information is transmitted at high serial rates. Care must be taken to implement this serial I/O flex cable. When developing flex routing or flex PCB, the following best practice should be used: Keep all four differential wires the same length. No noise signals are allowed on or near the differential serial lines. Example: There are no LVCMOS traces on the differential wires. Use only one ground plane or differential serial line. Don't run the ground from top to bottom. Do not place test points on differential serial lines. Use a differential serial line, at least 2 cm from the antenna.