feature

Drives N-channel high-side and low-side mosfet synchronous buck configuration 12V high-side and 12V low-side drivers Internal adaptive "shoot-through" protection Integrated bootstrap diodes for high-side drive Fast rise and fall times Switching frequency up to 500kHz Output disabled OD Input - Allows Synchronous Band PWM Controller SOIC-8 Package Available in Low Thermal Resistance MLP Package

application

Multiphase VRM/VRD Regulators for Microprocessors Power High Current/High Frequency DC/DC Converters High Power Modular Power Supplies

General Instructions

The FAN5009 is a dual frequency high frequency MOSFET driver designed for driving N-channel power MOSFETs in a synchronous rectifier buck converter. These drivers, combined with Fairchild polyphase PWM controllers and power mosfets, form a complete core voltage regulator advanced microprocessor solution. Fan 5009 drives a synchronous buck regulator to 12VGS. The top gate driver includes an integrated boot diode and only requires an external bootstrap capacitor (CBOOT). The output drivers in the Fan 5009 have the ability to efficiently switch power mosfets with frequencies up to 500kHz. The circuit is adaptive penetration protection preventing the mosfet from not being able to command at the same time. The Fan 5009 is rated to operate from 0°C to +85°C and is available in a low-cost SOIC-8 or MLP package.

Absolute Maximum Ratings The stresses listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress ratings only and functional operation of the device under these or other conditions, beyond the operating portion of this specification is not implied. Extended exposure to absolute maximum rating conditions may affect device reliability. Absolute Maximum Ratings apply individually, not in combination. Voltages are referenced to PGND unless otherwise specified.

Circuit Description

The FAN5009 is a dual MOSFET driver for driving N-channel MOSFET topologies in synchronous buck converters. Only a single PWM input signal is required to properly drive the high-side and low-side MOSFETs. Each driver can operate at up to 500 Hz. Regarding the FAN5009 and its features, the low-side driver low-side driver (LDRV) is designed to drive a ground referenced low RDS(on) N-channel mosfet. Bias LDRV is internally connected between VCC and PGND. When the driver is enabled, the driver's output is in phase with the PWM input. When fan 5009 is disabled (OD=0V), LDRV remains low. High-Side Driver The high-side driver (HDRV) is designed to drive floating N-channel MOSFETs. The bias driver for the high side is developed by a bootstrap power supply circuit including internal diodes and external bootstrap capacitors (CBOOT). During startup, SW is held at PGND, allowing CBOOT to charge VCC through the internal diode. When the PWM input goes high, HDRV will start charging the high side of the MOSFET gate (Q1). During this transition, charge is removed from CBOOT and delivered to Q1's gate. As Q1 is turned on, the switch goes up to VIN, forcing the boot pin VIN+VC (BOOT) to provide enough VGS to enhance Q1. To complete the switching cycle, turn off Q1HDRV by pulling it to SW. When the switch is turned on, CBOOT recharges until VCC falls on PGND. The HDRV output is in phase with the PWM input. When the driver is disabled, the high side door remains in the low position. The adaptive gate drive circuit FAN5009 uses an advanced design to ensure minimum MOSFET dead-time penetration (cross-conduction) currents that eliminate the potential.

It senses the state of the mosfet and adaptively adjusts the gate drive to make sure they don't happen at the same time. The reference figure shows the relevant timing waveforms. To prevent overlap during a low-to-high transition (Q2 off to Q1 on), the adaptive circuit monitors the voltage at the LDRV pin. High when the PWM signal disappears, Q2 will start off delay (tpdl(LDRV)) after some propagation. Once the LDRV pin discharges below ~1.2V, Q1 starts to turn on after the adaptive delay tpdh(HDRV). During high-low transitions (Q1) to prevent overlapping from off to Q2 on), the adaptive circuit monitors the voltage at the switch pins. When the PWM signal goes low, Q1 will start to turn off after some propagation delay (tpdl(HDRV)). Once the switch pin drops below ~2.2V, Q2 starts to turn on after the adaptive delay tpdh(LDRV). In addition, the VGS for the first quarter was also monitored. When VGS(Q1) is discharged below ~1.2V, a secondary adaptive delay is initiated, causing Q2 to be driven after tpdh(ODRV) regardless of software state. This function is implemented to ensure that CBOOT is charged every switching cycle, especially for power converter sink current and switching voltage not lower than the 2.2V adaptive threshold. The secondary delay tpdh (ODRV) is greater than tpdh (LDRV)

application information

Power Supply Capacitor Selection For the power supply input (VCC) of the FAN5009, a local ceramic bypass capacitor is recommended to reduce noise and provide peak current. Use at least 1µF, X7R or X5R capacitors. Place this capacitor close to the fan 5009 VCC and PGND pins. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBOOT) and an internal diode, as shown in Figure 1. The selection of these parts should be made after the high side MOSFET is selected. The required capacitance is determined using the following formula:

where QG is the total gate charge of the high-side MOSFET, and ∏VBOOT is the allowable voltage drop on the high-side MOSFET driver. For example, the QG of FDD6696 is about 35nC@12VGS. The bootstrap capacitor required for an allowable voltage drop of ~300 mV is 100nF. Good quality must use ceramic capacitors. The average diode forward current IF(AVG) can be:

where FSW is the switching frequency of the controller. The peak inrush current rating of the internal diodes should be for the pickup circuit, as this depends on the impedance of the entire boot circuit of the equivalent circuit, including the PCB trace. For applications requiring higher IF, an external diode can be used in parallel with the internal diode.

As stated above in Equations 8 and 9, the total power dissipation when driving the gate is proportional to the resistance of the gate in series with the internal gate node of the MOSFET, as shown below

RG is the polysilicon gate resistance inside the FET. RE is many designs. Note that introducing RE can reduce driver power consumption, but excessive RE may lead to "adaptive gate drive" circuits. For more information, see "Through-Through" Synchronous Buck Converters in Fairchild Application Note AN-6003.

Layout Considerations

When designing your print, follow these general guidelines

Circuit board (see picture):

1. Find high current paths and use short and wide (>25 mil) traces for these connections.

2. Place the PGND pin of the fan 5009 as close as possible to what could be the source of the low MOSFET.

3. The VCC bypass capacitors should be placed as close as possible to the pins available for VCC and PGND.

4. Where possible, use vias to other layers away from the thermal conduction of the integrated circuit.

5. The paddle on the MLP package is the ground referenced internally. It can be left floating or grounded. For best thermal performance, it should be connected to ground as shown.

6. Recommended land type mechanical dimensions shown in MLP are for MLP-8 as well as SO-8 packages. The circuit in the figure demonstrates a typical implementation of VCORE with a single-phase buck converter application. For a complete VR10 design example, see the FAN5019 or FAN5018 datasheet.