describe
The UCCx817/18 family provides all the functions required for an active power factor correction preconditioner. By shaping the AC input line current waveform to make it correspond to the AC input line voltage waveform, the controller achieves the goal of approaching unity power factor. Average current mode control maintains stable, low distortion string current.
UCC2817/UCC2818 are designed in BiCMOS process from Texas Instruments and feature low start-up current, low power consumption, over-voltage protection, parallel UVLO detection circuit, leading-edge modulation technique to reduce bulk capacitor ripple current, and improved low offset (±2mv) New features such as current amplifier Deformation under light load conditions.

Description (continued)
The UCC2817 provides an on-chip shunt regulator with low start-up current for applications using a bootstrap power supply. The UCC2818 is suitable for fixed power supply (VCC) applications.
Available in 16-pin D, DW, N, and PW packages.
Absolute Maximum Ratings for Operating Free Air Temperature (unless otherwise stated): Supply Voltage VCC 18 V. . . . . .
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and do not imply that the functional operation of the device under these or any other conditions exceeds that indicated under the recommended operating conditions. Prolonged exposure to absolute maximum rating conditions may affect device reliability.

PIN Description The current amplifier non-reversing input is located between the Product and the front of the current sense resistor. This input and the inverted input ("Mout") function down to and down to GND.
The current amplifier output is the output of a wideband operational amplifier that senses the line current and controls the PFC pulse wideband modulator (PWM) to force the correct power cycling. The compensating part is located between the rubber and the cork.
Oscillator Timing Capacitor (Oscillator Timing Capacitor) From CT to GND According to: F 0.6 RT CT Capacitor from Oscillator Timing Capacitor to GND should be as short and direct as possible.
The output drive of the switch is the largest gate drive on a totem pole. A series of gate resistors are used to prevent the interaction between the gate impedance and the output drive, which can cause excessive interference. See characteristic curve to determine minimum required gate resister value. Some spillover value of the dryer output is always expected when inducing capacitive loading.

Pin Description (continued)
IAC: (Current proportional to input voltage) This current input to the analog multiplier is proportional to the instantaneous line voltage. The multiplier is tailored for very low distortion from this current input (IIAC) to the multiplier output. The recommended maximum voltage is 500 kV A: (Multiplier output and current amplifier inverting input) The output of the analog multiplier and the inverting input of the current amplifier are connected together at 10:30 am. Since the multiplier output is current, which is a high impedance input, the amplifier can be configured as a differential amplifier. This structure improves noise immunity and allows leading edge modulation operation. The multiplier output current is limited to 2 IIAC. The multiplier output current is given by:
where K 1 V is the multiplier gain constant.
OVP/EN: (Over Voltage/Enable) A window comparator input that disables the output driver when the boost output voltage is above nominal, or disables the PFC output driver and resets when the voltage is below 1.9 V (typ) SS.
PKLMT: (PFC Peak Current Limit) The threshold for the peak limit is 0v. Using a resistive divider to shift the signal from the negative side of the current sense resistor to the VREF level moves the signal to a voltage level defined by the value of the sense resistor and the peak current limit. The peak current limit is reached when the PKLMT voltage is below 0v.
RT: (Oscillator Charge Current) A resistor from RT to GND is used to program the oscillator charge current. A resistor between 10 kΩ and 100 kΩ is recommended. The nominal voltage on this pin is 3 V. SS: (Soft Start) VSS is discharged under VVCC low condition. When enabled, SS charges an external capacitor with a current source. This voltage is used as a voltage error signal during startup, causing the PWM duty cycle to slowly increase. With VVCC out, OVP/EN is forced below 1.9 V (typ) and SS is quickly discharged to disable PWM.
Note: Grounding the SS pin does not ensure a 0% duty cycle in an open loop test circuit. See the application section for details.
VAOUT: (Voltage Amplifier Output) This is the output of the op amp that regulates the output voltage. The output of the voltage amplifier is internally limited to approximately 5.5 V to prevent overshoot.
VCC: (Positive Supply Voltage) Connect to a stable supply of at least 20 mA between 10 V and 17 V for proper operation. Bypass VCC directly to GND to sink the peak supply current required to charge the gate capacitance of the external MOSFET. To prevent insufficient gate drive signal, the output device is disabled unless VVCC exceeds the upper undervoltage lockout voltage threshold and remains above the lower threshold.
VFF: (Voltage Feed Forward) The rms voltage signal produced at this pin by mirroring 1/2 of the IIAC to a single pole external filter. At low voltage, the VFF voltage should be 1.4V.
VSENSE: (Voltage Amplifier Inverting Input) This is usually connected to a compensation network and a boost converter output through a voltage divider network.
VREF: (Voltage Reference Output) VREF is the output of an accurate 7.5-V voltage reference. This output is capable of outputting 20 mA to peripheral circuits and is internally limited in short-circuit current. When VVCC is below the UVLO threshold, VREF is disabled and held at 0V. Bypass VREF to GND with a 0.1-micron or larger ceramic capacitor for best stability. About VREF Line and Load Regulation Characteristics

power stage
LBOOST: The boost inductor value is determined by:
Promote
VIN(min) D(I fs), where D is the duty cycle, ∏I is the inductor ripple current, and fs is the switching frequency. For this example circuit, a switching frequency of 100 kHz, a ripple current of 875 mA, a maximum duty cycle of 0.688, and a minimum input voltage of 85 VRMS provide a boost inductor value of about 1 mH. The value used in this equation is the peak value at the low line, where the inductor current and its ripple are at their maximum value.
COUT: Two main criteria, capacitance and voltage rating, determine the choice of output capacitor. The capacitance value is determined by the hold-up time required to support the load after the input AC voltage is removed. Hold time is the amount of time that the output remains in regulation after the input is removed. For this circuit, the required dwell time is about 16. Capacitor values are given in terms of output power, output voltage and dwell time:
In practice, the calculated minimum capacitor value may be insufficient due to the output ripple voltage specification limiting the amount of allowable output capacitor ESR. Achieving a sufficiently low ESR value usually requires using a much larger capacitor value than the calculated value. The amount of allowable output capacitor ESR can be determined by dividing the maximum specified output ripple voltage by the inductor ripple current. In this design, dwell time was the main determining factor, and a 220-µF, 450-V capacitor was chosen to give an output voltage of 385 V DC at 250 W.
Power switch selection: In any power supply design, there must be trade-offs between performance, cost, and size. When selecting a power switch, it is useful to calculate the total switching power dissipation of several different devices when considering the switching frequency of the converter. The total power dissipation of the switch is the sum of switching losses and conduction losses. Switching losses are the combination of gate charge losses, COSS losses, and switching losses:
At POFF 12 VOFF IL tON tOFF fs, where QGATE is the total gate charge, VGATE is the gate drive voltage, fs is the clock frequency, COSS is the drain-source capacitance of the MOSFET, IL is the peak inductor current, and tON and tOFF are the switching times (estimated using the device parameters RGATE, QGD and VTH) and VOFF is the voltage of the switch during the off time, in this case VOFF = VOUT.

Application Information Conduction losses are calculated as the product of the switch's RDS(on) (at worst junction temperature) and the square of the rms current:
where K is the temperature coefficient in the manufacturer's RDS(on) vs. junction temperature curve. Calculating these losses and plotting against frequency enables designers to determine which manufacturer's device has the best performance at the desired switching frequency, or which switching frequency has the smallest total loss for a particular power switch. In this design example, an IRFP450 HEXFET from International Rectifier was chosen because of its low RDS(on) and its VDSS rating. With an RDS(ON) of 0.4 and a maximum VDSS of 500 V, the IrpP450 is ideal. For a detailed description of this procedure, see the Unipolar Power Supply Design Workshop (SEM1200, Topic 6, Design Review: 140 W, [Multiple Output High Density DC/DC Converters]).
Soft Starter The soft start circuit is used to prevent overshoot of the output voltage during startup. This is achieved by slowly increasing the output of the voltage amplifier (VVAOUT), which causes the PWM duty cycle to slowly increase. Use the following formula to select a capacitor for the soft-start pin.
In this example, tDELAY is equal to 7.5ms, which results in 10nf of CSS.
In the open loop test circuit, shorting the soft-start pin to ground does not ensure a 0% duty cycle. This is due to the current amplifier input bias voltage, which may force the current amplifier output high or low depending on the polarity of the bias voltage. However, in a typical application, there is enough inrush and bias current to overcome the bias voltage of the current amplifier.
multiplier
The output of the UCC3817 multiplier is a signal representing the desired input line current. It is an input to a current amplifier that programs the current loop to control the input current for high power factor operation. Therefore, the normal operation of the multiplier is the key to the success of the design. The inputs to the multiplier are VAOUT, the voltage amplifier error signal IIAC, a representation of the input rectified AC line voltage, and the input voltage feedforward signal VVFF. The output of the multiplier IMOUT can be expressed as:
VVAOUT 1k VVFF 2, where K is a constant typically equal to 1v Electrical characteristics table covers all operating conditions required for multiplier design