Features

DAC/Voltage Monitor and PWM Combo with Synchronous Rectification
5 digital to analog converters
1% DAC/Reference Combo Accuracy Compatible with 5V and 12V Systems and 12V Only Low Offset Current Sense Amplifier Programmable Oscillator Frequency for 700kHz
Folded Current-Limited Overvoltage and Undervoltage Fault Windows
2Ω Totem Pole Output with Programmable Dead Time to Eliminate Cross Conduction Chip Disable Function Average Current Mode Synchronous Controller with 5-Bit DAC Block Diagram
Model UDG-97047-1 Description The UCC3882 combines a high precision reference voltage monitoring circuit with an average current mode PWM synchronous rectification controller circuit to power high-end microprocessors with minimal external components. With 1% DC system accuracy, the UCC3882 converts 5V or 12V into an adjustable output with 50mV steps ranging from 1.8VDC to 2.05VDC and 100mV steps ranging from 2.1VDC to 3.5VDC.
The DAC output voltage is directly compatible with Intel's 5-digit VID code (Table 1), which covers 1.3V to 2.05V in 50mV steps and 2.1V to 3.5V in 100mV steps. The accuracy of the DAC/reference combination is better than 1%. Undervoltage lockout circuitry ensures the correct logic state of the outputs during power up and power down. Overvoltage and undervoltage comparators monitor the system output voltage and indicate when it is above or below its design value by more than 9%. A second overvoltage comparator digitally forces GATEHI off and GATELO on when the system output voltage exceeds its design value by more than 17.5%.

Absolute Maximum Ratings
VDRVHI, GATEHI (Note 1). . . . . . . . . . . . . . . –0.3 volts to 20 volts Verdwello, Gateway. . . . . . . . . . . . . . . . . . . –0.3V to 15V
All other GND related pins. . . . . . . . . . . . –0.3 volts to 5.3 volts
+15V storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
junction temperature. . . . . . . . . . . . . . . . . –55°C to +150°C
Lead temperature (soldering, 10 seconds). . . . . . . . . . . . . +300 degrees Celsius current stored to, negative output to designated terminal. Packaging section of the data sheet for heat distortion and packaging considerations.
Note 1: 20V without load. The capacitive load used in series with Derateto18.5V is greater than 1000pF and less than 20Ω.

Description (continued)
For all parts, grounding the EN pin disables the GATEHI and GATELO outputs and turns off the power. For the 2882 and 3882 only, programming the DAC output voltage below 1.8V, or programming all VID pins high, also disables the GATEHI and GATELO outputs. For the "-1" option section, the GATEHI and GATELO outputs are switching and the supply output voltage is regulated at the programmed DAC output voltage for all VID codes.
The voltage and current amplifiers have a gain-bandwidth product of 2.5MHz to meet the requirements of high-performance systems. An internal current-sense amplifier allows the use of a low-value current-sense resistor, minimizing power loss. Oscillator frequency is external -

Pin Description Cam: This pin is the inverting input of the current amplifier. Average load current feedback from the ISOUT pin is applied to this pin through a resistor. The current loop compensation network is also connected to this pin (see CAO below).
Cao: This pin is the output of the current amplifier. The current loop compensation network is connected between this pin and the CAM pin. The voltage on this pin is the input to the PWM comparator and regulates the output voltage of the system. The output voltage ranges from below 0.5V (forcing 0% duty cycle) to above 2.5V forcing the maximum duty cycle. A 3V clamp circuit prevents the calcium oxide voltage from rising excessively beyond the oscillator peak voltage for good transient response.
Company: This pin is the output voltage of the voltage error amplifier. A system voltage compensation network is applied between COMP and VFB. When the output is shorted, a 1.37V clamp command is used to force the power supply into current-limit mode. See the application section for programming the current limit.
Command: This pin is the output of the 5-bit digital-to-analog converter (DAC) and is the non-inverting input of the voltage error amplifier. The voltage on this pin sets the switching regulator output voltage. According to Table 1, the command voltage is set by the DAC input pins D0-D4. The command source impedance is typically 1.2kΩ, so if accuracy is to be maintained, only high impedance inputs must be driven. Bypass command with 0.01µF, low ESR, low ESL capacitor for best circuit noise immunity.
Computed Tomography: This pin is used with RT to program the internal PWM oscillator frequency. Use high quality capacitors for best oscillator accuracy. See the Applications section for programming the oscillator.
D0-D4: These are the digital input control codes for the DAC (see Table 1). The DAC consists of two ranges set by D4, D0 for the least significant bit (LSB) and D3 for the most significant bit (MSB). One bit is set low by grounding; one bit is set high by floating or connecting to a 5V supply. Each control pin is pulled up to about 5V by an internal pull-up.
English: This input is used to disable GATEHI and
GATELO output, causing the power supply to be disabled. Pulling EN to GND causes the GATEHI and GATELO outputs to remain low, while floating the pin or pulling it to 5V ensures proper operation. EN is internally pulled up to 5V.
Getty: This output provides a low impedance totem pole driver to drive the high side external MOSFET. A series resistor between this pin and the gate of the external MOSFET is recommended to prevent gate drive ringing and overshoot. Good layout techniques should be used to prevent GATEHI from ringing below PGND by more than 0.3V. The VDRVHI pin provides power to the GATEHI pin. GATEHI is disabled during UVLO and overvoltage conditions. For the 2882/3882 only, when the command voltage is programmed between 1.3 and 1.75V, or when the D0-D4 pins are all logic high, GATEHI is also disabled, indicating the absence of a processor.
Pin Description (continued)
Gatelow: This output provides a low-impedance totem pole driver to drive a low-side synchronous external MOSFET. A series resistor between this pin and the gate of the external MOSFET is recommended to prevent gate drive ringing and overshoot. Good layout techniques should be used to prevent GATELO from ringing below PGND by more than 0.3V. The VDRVLO pin provides power to GATELO. Under UVLO conditions, GATELO is disabled. For the 2882/3882 only, when the command voltage is programmed between 1.3 and 1.75V, or when the D0-D4 pins are all logic high, GATELO is also disabled, indicating the absence of a processor.
Ground: The ground reference for the device. Except for the gate voltage, all voltages are measured relative to GND. Bypass capacitors on VIN, VREF, VSNS, and COMMAND should be connected directly to a ground plane near ground.
Yes -: This pin is the inverting input of the current sense amplifier and connects to the low side of the average current sense resistor.
IS+: This pin is the non-inverting input of the current sense amplifier and connects to the high side of the average current sense resistor.
ISOUT: This pin is the output of the current sense amplifier. The voltage on this pin is equal to the voltage on the sense resistor multiplied by 16, plus the command voltage. This voltage is used for average current mode control and current limiting.
PGND: Page This pin provides a dedicated ground for the output gate driver. The GND and PGND pins should be connected externally using short PC board traces or planes. Separate VDRVHI and VDRVLO from PGND with a low ESR capacitor of at least 0.1µF.
PWRGD: This pin is an open-drain output that drives a low level to reset the microprocessor when VSN is above or below 9% of its nominal value. The on-resistance of an open-drain switch will be no higher than 470Ω. This output should be pulled high to a logic level voltage and should be programmed to receive 1 mA or less.
Room temperature: This pin is used with CT to program the internal PWM oscillator frequency. It is also used to program the delay time between on and off cycles of external MOSFETs, thereby eliminating cross-conduction in these MOSFETs. See the Applications section for information on oscillator programming and controlling cross-conduction.
VDRVHI: This pin powers the high-side output driver GATEHI. Connect VDRVHI to a 18V or lower voltage source (for converting 12VDC to a lower voltage power supply) and to a 12V voltage source (for converting 5VDC to a lower voltage power supply system). This pin should be bypassed directly to PGND with a low ESR capacitor.
VDRV LOW: This pin powers the low-side output driver GATELO. VDRVLO is usually connected to a 12V supply, but can also be connected to a 5V supply to drive logic level mosfets. This pin should be bypassed directly to PGND with a low ESR capacitor.
VIN: This pin powers the chip. Connect the vehicle identification number (VIN) to a stable voltage source that is at least 10.8 volts above ground. The GATEHI, GATELO, and PWRGD outputs will remain low until VCC exceeds the high undervoltage lockout threshold. This pin should be bypassed directly to ground.
Ventricular Fibrillation: This pin is the inverting input of the error amplifier. This input is connected to COMP through a feedback network and to the power supply output through a resistor or voltage divider network.
REFERENCE VOLTAGE: This pin provides an accurate 5V reference voltage with limited internal short-circuit current. VREF powers the D/A converter and also provides the threshold voltage for the UVLO comparator. For best reference stability, bypass VREF directly to GND with a low ESR, low ESL capacitor of at least 0.01µF.

Virtual Storage Network: This pin is connected to the system output voltage through a low-pass RC filter. When the voltage on VSN is 9% above or below the command voltage, the PWRGD output is driven low to reset the microprocessor. When the voltage on VSN is 17.5% above the commanded voltage, the OVP comparator disables the GATEHI output and enables the GATELO output, forcing a 0% duty cycle on the supply. This pin is also used by the folding current limiting circuit to indicate when the output voltage is shorted. VSN should be very closely separated from the IC with a capacitor to ground. The hysteresis of the OV and UV comparators is typically 20mV and requires good layout and filtering techniques to ensure that noise and ground bounce do not inadvertently trip the OV and UV comparators. An R-C filter set to approximately FS/10 is recommended for filtering noise from the system output, where Fs is the oscillator frequency.
DAC information
The 5 digital-to-analog converters (DACs) are programmed according to Table 1. The command voltage is always active as long as the UCC3882 VIN pin is above the undervoltage lockout voltage. For 2882/3882 only, the output gate drives GATEHI and

Application Information This IC is used for high performance power supplies to power a Pentium II or similar processor. Figure 1 shows a typical power application circuit that converts +5V to the lower voltage required by the Pentium II processor. ®®
Synchronous switching delay time
The basic difference between buck and synchronous buck regulators is not a Schottky diode as a low side or free spin switch.
To maintain safe and efficient operation of the synchronous buck regulator, the mosfets (Q1 and Q2) should not be turned on at the same time. Turning on two mosfets at the same time can cause cross conduction, which can cause excessive power dissipation in one or both mosfets. The UCC3882 has a built-in delay between the turn-off of one MOSFET and the turn-on of the other MOSFET. This delay is a controlled delay between the GATEHI and GATELO drive outputs, programmable by selecting resistor RT. Controlling the delay between the GATEHI and GATELO drive outputs is only part of the solution. Power supply designers must also understand the inherent delays involving MOSFET turn-on, turn-off, rise and fall times to ensure there is no cross-conduction.
A value between 10kΩ and 15kΩ is recommended for RT, which will minimize latency and result in the most efficient operation. Higher RT values will result in larger delays between MOSFET gate transitions. RT should be between 10K min and 50K max.
Oscillator Programming The first step in programming the oscillator is to select the value of RT as described above. The second step is to program the frequency by choosing the appropriate capacitor value according to the curve shown in Figure 3.
For convenience, nominal frequency values of 100kHz to 700kHz for standard resistor and capacitor values are used.

Too much delay time between gate drive signals, or too little delay time, will result in an inefficient power supply design. The third step in oscillator programming is to observe the actual circuit waveforms to ensure that the delay is optimal. The designer should change RT and CT accordingly to adjust the delay time and program the appropriate oscillator frequency.
Use an external Schottky diode in parallel with the low-side MOSFET

The purpose of using a synchronous buck regulator is to replace the Schottky diode with a low-dropout MOSFET as the low-side switch. However, an external Schottky diode is still required to reduce losses due to reverse recovery of the body diode of the low-side MOSFET. Figure 4 illustrates the effect on power loss due to the non-ideal nature of a typical MOSFET body diode. IRM is the peak recovery current of the body diode of Q2, and ILOUT is the current of the output inductor. Using parallel Schottky diodes can reduce these losses and improve circuit efficiency. Diode size should increase with load current, input voltage, and operating frequency. The diode should be as close as possible to the lower MOSFET, Q2, to reduce stray inductance.
APPLICATION INFORMATION SELECTING RSENSE SETTING CURRENT LIMIT The short-circuit current limit is not a function of the switching regulator's output inductance value and operating frequency, as high values of ripple current reduce the average short-circuit current limit. Changes in Isc given public values for UCC3882. The UCC38 822 is nominally configured so that a 0.00 5MΩ resistor sets the current limit to about 17A.
The UCC3882 includes short-circuit current folding, which reduces the output voltage when the power supply output is shorted. When the output voltage reaches 1/2 of its nominal voltage (command/2), the output current decreases. This feature reduces the amount of current in the mosfet and capacitor and ensures high reliability.

Select VDRVLO, VDRVHI and VIN
The UCC3882 requires a nominal 12 volt input at the VIN. VDRVLO and VDRVHI can be set to any voltage below 18.5V and can be set individually. Power supplies derived from +5V should use +12V at the VDRVHI pin, but either +5V or +12V can be used depending on the drive requirements of the synchronous low-side MOSFET. Supplies that draw power from +12V should use +18V at VDRVHI to provide sufficient voltage (6V) gate drive for the high-side MOSFET. The VIN must be less than +15V.
Input Capacitors Input capacitors are selected primarily based on their switching frequency rms current handling capability and voltage rating. Even if the circuit has no input inductance, the input capacitor must handle nearly all of the rms current at the switching frequency. The switch current in the input capacitor is shown in Figure 7.
Aluminum or tantalum capacitors can be used. The size of the rms current in the electrolytic capacitor has a great influence on the reliability and life of the capacitor. Other factors that affect the life of the input capacitor are internal thermal rise, external airflow, the amount of time the circuit operates at maximum current, and the operating voltage. The curves in Figure 8 show the rms current handled by the total input capacitance in a VRM circuit with a typical voltage of 5V or 12V.

Application Materials (continued)

UCC3882 5-Bit Synchronous Rectifier PWM Controller for Intel Pentium II Processors