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Industry Standard Pinout 4.5-V to 18-V Operating Range 3-A Peak Sink/Source at VDD=12 V; 2.4 A Peak Sink/1.6-A Source at VOUT=6 V; TTL or CMOS Input Threshold Choose from four versions of dual independent drivers: - Dual Inverted + Enable ( FAN3226 ) - Dual Non-Inverted + Enable (FAN3227) - Dual Input in Two o Pin-Out Configurations: o Compatible with FAN3225x (FAN3228) o With TPS2814D (FAN3229) Compatible Internal resistor turns off driver MillerDrive 8482 if no input; technology 12 ns/9 ns typical rise/fall time (1-nF load); 20 ns typical propagation delay matched to another channel with 1ns parallel channel Dual current capability 8-lead 3x3 mm MLP or 8-lead SOIC package ambient temperature -40°C to +125°C Automotive Qualified AEC-Q100 (Version F085)

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Software Itch Mode Power Supply High Efficiency MOSFET Switch Itch Synchronous Rectifier Circuit DC-DC Converter Motor Control Server Automotive Qualification System (Version F085)

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The FA N3226-29 dual 2a gate driver family is designed to drive N-channel enhancement mode mosfet applications in low-side sw-itch applications to deliver high peak current pulses in short sw intervals. The driver has two options for TTL or CMOS input thresholds. Internal circuitry provides an undervoltage lockout function by keeping the output low until the supply voltage is within the operating range. Additionally, the driver characteristics and the internal propagation delay between the A and B channels are timed for applications that require dual gate drivers, such as synchronous rectifiers. This enables two drivers to be connected in parallel for efficient dual current capability of driving a single MOSFET. The FA N322X driver contains the architecture of the final output stage of MillerDrive™. This bipolar MOSFET combination minimizes switching losses at the Miller platform stage of MOSFET switching while providing rail-to-rail voltage switching and reverse current capability. The FAN3226 provides two inverting drivers and the FAN3227 provides two non-inverting drivers. Each device has dual independent enable pins, which are open and unconnected by default. In the FAN3228 and FAN3229, dual inputs with opposite polarity per channel allow the use of an optional enable function using the second input. If either or neither of the inputs are connected, internal resistors bias the inputs to pull the outputs low to keep the power MOSFETs off.

Notes: 2. Estimated value from thermal simulation; actual value depends on application. 3.ThetaΘJL (ΘJL): The semiconductor junction with all leads (including thermal pads), usually soldered to the PCB. 4. ThetaΘJT (ΘJT): The thermal resistance between the semiconductor junction and the top surface of the package, assuming a uniform temperature is maintained by a heat sink on top. 5. ThetaΘJA (ΘJA): Thermal resistance between connection and ambient, depending on PCB design, heat dissipation and airflow. Values given are for natural convection without heatsink using 2S2P boards, as specified by JEDEC standards JESD51-2, JESD51-5 and JESD51-7 (as applicable). 6. Psi_JB (ΨJB): Provides the application board reference point for the semiconductor junction temperature and thermal environment defined in Note 5. For the MLP-8 package, the board reference is defined as the PCB copper that is connected to the thermal pads and protrudes from both ends of the package. For the SOIC-8 package, the board reference is defined as pin 6.7 near the PCB copper trace. Psi_JT (ΨJT): Provides the semiconductor junction temperature with the thermal environment defined in Note 5 at the top center of the package.

Application Information Input Thresholds FA N322x Driver family includes two identical channel current ratings for each member of the N322x driver series that can be used independently or a single current capacity in parallel. In FA N3226 and FA N3227, channels A and B can be enabled or disabled independently using ENA or ENB respectively. UK for thresholds with CMOS or TTL inputs. If ENA and ENB are not connected, internal pull-up resistors make the drivers default to channel. If Channel A and Channel B inputs and outputs are connected in parallel to increase the driver current capacity, ENA and ENB should be connected together and driven together. The FA N322x series are available with TTL or CMOS input thresholds. In the FA N322xT, the input threshold meets the industry standard TTL logic threshold independent of the VDD voltage and the hysteresis voltage is approximately 0.4 V. Allows input logic to be driven from a range of inputs to account for signal level logic high at voltages over 2V. The drive signal for the TTL input should have fast rising and falling edges with a slew rate of 6 V/µs or faster, so the rise time from 0 to 3.3 V should be 550 ns or less. Reduced slew rate and circuit noise can cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, resulting in unstable operation. In the FA N322xC, the logic input threshold is approximately 55% of the input falling edge threshold of approximately 38% of VDD based on the VDD level and a VDD logic rising edge threshold of 12 V.

The CMOS input configuration provides a hysteresis voltage of approximately 17% of VDD. This CMOS input can use relatively slow edges (near DC) if good decoupling and bypassing techniques are included in the system design to prevent noise from corrupting the input voltage hysteresis window. This allows to pass in the control signal and the driver's latch. The slowly rising edge of the driver's pin is the control signal and the driver's output pin. Quiescent Supply Current While generating curves in IDD (Static) Typical Performance Characteristics, all inputs/enables floating (OUT low) indicate est quiescent IDD current is low for the configuration tested. For other states, additional current flows through a 100 kΩ resistor on the input output shown as n in the block diagram of each section. In these cases the quiescent IDD current is the value obtained from the curve plus this additional current.

MillerDrive™ Door Drive Technology The FA N322x door drives incorporate the MillerDrive™ architecture as shown. For the output stage, a combination of bipolar and MOS devices provides variations in supply voltage and temperature. Bipolar devices carry most of the current between 1/3 and 2/3 of the output switch VDD and MOS devices pull the output high or low rail. The MillerDrive™ architecture is designed to act as an on/off process through the gate-to-drain capacitance of the MOSFET in the Miller plateau region. For the MOSFET switching interval, the driver provides high peak current for fast switching although the Miller plateau does not exist. This situation often occurs in synchronous rectifier applications because the body diode is usually switched on when the MOSFET is switched on. The output pin slew rate is determined by the VDD voltage and the output load. It's not user adjustable, but if the current slows down the rise or fall time, you can increase the series resistance needed at the MOSFET gate.

Undervoltage Lockout The FAN322x startup logic is optimized to drive the low-voltage grounded N-channel mosfet lockout (UVLO) function, ensuring that the IC starts up in an orderly manner. When VDD rises, but falls below the 3.9V operating voltage, the circuit maintains a low output regardless of the state of the input pins. When activating after that part, the supply voltage must be turned off in the part down. This hysteresis helps prevent chattering when low VDD supply voltages have itching from the power switch. This configuration is not suitable for driving high-side P-channel MOSFETs because the output voltage of the driver will turn the MOSFET on w with P-channel VDD below 3.9 V.

VDD Bypass Capacitor Guidelines To enable this IC to quickly turn on a device, a local high frequency bypass capacitor CBYP w with low ESR and ESL should be connected between the VDD and GND pins with a minimum trace length. This capacitor is a bulk electrolytic capacitor typically 10 to 47 µF found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply less than or equal to 5%. This usually reaches the load capacitance CEQV when the value is greater than or equal to 20 times, defined here as QGATE/VDD. A common choice for 0.1µF to 1µF or larger ceramic capacitors, such as X5R and with good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, CBYP can be increased to 50-100 times CEQV, or CBYP can be divided into tw-o capacitors.

One should be a larger value based on the equivalent load capacitance, and another smaller value like 1-10nf mounted closest to the VDD and GND pins to carry the higher frequency content of the current pulse. This bypass capacitor must be supplied from both driver channels, and if the driver sw is firing simultaneously, the composite peak current from the CBYP ice should be as large as the w-hen one channel is sw-itching. Layout and Hookup Guidelines The FA N3226-26 series gate drivers include fast-reacting input circuitry, short propagation delays, and power stages capable of outputting current peaks in excess of 2 A to facilitate voltage transition times below 10 ns to over 150 ns. The following layout and hookup guidelines are strongly recommended: Keep high current output and power ground paths separate from logic and enable input signal and signal ground paths. It is especially important to handle TTL level logic threshold inputs and enable pins in the driver. Keeping the driver as close to the load as possible minimizes the length of the high current trace. This reduces series inductance to improve high-speed switching itch while reducing the amount of circuitry available to and around the driver input. If the input of the channel is not connected externally, instruct the internal 100 kΩ resistor on the block diagram to command the low output. In noisy environments, it may be necessary to switch an unused channel to a short output switch to prevent noise from causing spurious traces. Many high-speed power circuits can be affected from their outputs or other external sources, possibly causing the output to retrigger. Test layouts with long input, enable, or output leads if the circuit is on a breadboard or non-optimal circuit. For best results, keep all pin connections as short and direct as possible.

The Fan 322X is compatible with many other industry standard drivers. To enable pins in single-input parts, there is an internal 100 kΩ resistor connected to VDD to enable the driver by default; this should be considered in the PCB layout. On and off current paths should be minimized, as described in the next section. The diagram shows the pulsed gate drive current path when the gate driver provides the gate charge to turn the MOSFET on. Current is provided locally by the bypass capacitor, CBYP, and through the driver's s-current MOSFET gate and ground. To reach the peak possible peak current, resistive and inductive paths should be minimized. The localized CBYP behavior contains peak current pulses in the driver bank circuits, preventing them from interfering with sensitive analog circuits in the PWM controller.

The diagram shows the current path of the gate driver to turn off the MOSFET. Ideally, the driver shuns the current loop loop directly to the MOSFET source. For fast turn-off times, resistance and inductance in this path are minimized.