feature

Dual symmetric 600 MHz high-performance Blackfin cores 328K bytes of on-chip memory; each Blackfin core includes two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifters RISC-like registers and instruction model , easy programming and compiler friendly support for advanced debugging, tracing and performance monitoring Wide operating voltage range; 256 -ball CSP_BGA (2 sizes) and 297-ball PBGA; package options; peripherals; dual 12-channel DMA controllers (supports 24 Peripheral dma); 2 memory-to-memory dma; 2 memory-to-memory dma and 1 memory DMA controller; 12 general-purpose 32-bit timers/counters with PWM capability; SPI-compatible port; IrDA-capable UART; dual Watchdog timer; dual 32-bit core timers; 48 programmable flags (GPIO); on-chip phase-locked loop multiplication with a frequency of 0.5×64×; supports 2 parallel input/output peripheral interface units; ITU-R656 video And analog front end glueless interface; ADC company; 2 dual-channel, full-duplex synchronous serial ports, supporting 8 stereo I2; S channel.

General Instructions

The Blackfin family of products targets a variety of multi-method ADSP-BF561 processors, which are 174 ; dia, industrial and telecom applications. At the heart of the device are two separate analog devices Blackfin processors. These Blackfin processors combine the advantages of a dual-mac state-of-the-art signal processing engine, a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities in a single instruction-set architecture The advantages.

The ADSP-BF561 processor has 328K bytes of on-chip memory. Each Blackfin core includes:

(1), 16K bytes of instruction SRAM/cache

(2), 16K bytes of instruction SRAM

(3), 32K bytes of data SRAM/cache

(4), 32K bytes of data SRAM

(5), 4K bytes scratchpad SRAM

Other on-chip memory peripherals include:

(1), 128K bytes of low-latency on-chip L2 SRAM

(2), four-channel memory DMA controller

(3), external memory controller, support SDRAM, mobile SDRAM, SRAM and flash memory.

Portable Low Power Architecture

Blackfin processors provide world-class power management and performance. Blackfin processors use a low-power and low-voltage design methodology with dynamic power management capabilities that vary voltage and operating frequency to significantly reduce overall power consumption. Changing the voltage and frequency can significantly reduce power consumption compared to just changing the operating frequency. This means longer battery life for portable devices.

Blackfin processor core

As shown in Figure 2, each Blackfin core contains two multipliers/accumulators (macs), two 40-bit alus, four video alus, and a shifter computational unit processing 8-bit, 16-bit or 32-bit data.

Each MAC performs a 16-bit by 16-bit multiplication per cycle, accumulating a 40-bit result, providing 8-bit extended precision. The ALU performs a standard set of arithmetic and logical operations. With two ALUs capable of operating on 16-bit or 32-bit data, the flexibility of the compute unit covers the signal processing requirements of a diverse set of application requirements.

Each of the two 32-bit input registers can be seen as two 16-bit halves, so each ALU can complete a very flexible stand-alone.

16-bit arithmetic operations. Dual 16-bit or single 32-bit operations can be done in one cycle by treating registers as 16-bit operand pairs. By further utilizing the second ALU, four 16-bit operations can be simply done, resulting in faster throughput per cycle.

The powerful 40-bit shifter has a wide range of functions to perform shifting, rotation, normalization, extraction and storage of data. The data for the compute unit can be found in a multiport register file with 16 16-bit entries or 8 32-bit entries.

A powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. The sequencer supports conditional jumps and subroutine calls, as well as zero-overhead loops. Circular buffers store instructions locally, eliminating instruction memory accesses to tight loop code.

Two data address generators (DAGs) provide addresses for simultaneously fetching dual operands from memory. DAGs share a register file containing four sets of 32-bit index, modify, length, and base registers. Eight additional 32-bit registers provide pointers to common indices for variables and stack locations.

Blackfin processors support an improved Harvard architecture and a hierarchical memory structure. Level 1 (L1) memory typically runs at full processor speed with little or no latency. Level 2 (L2) memory is other memory, on-chip or off-chip, that can take multiple processor cycles to access. At the L1 level, the instruction memory only holds instructions. Two data memories hold data, and a dedicated scratch line data memory stores stack and local variable information. In a secondary system, there is only one unified memory space where instructions and data can be stored.

In addition, half of the L1 instruction memory and half of the L1 data memory can be configured as static ram (SRAM) or cache. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be running on the core, and can protect system registers from accidental access.

The architecture provides three modes of operation: user mode, management mode, and emulation mode. User mode provides a protected software environment by restricting access to certain system resources, while admin mode has unrestricted access to system and core resources.

The Blackfin instruction set is optimized so that the 16-bit opcodes represent the most commonly used instructions, resulting in excellent compiled code density. Complex DSP instructions are encoded into 32-bit opcodes representing full-featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instructions can be issued in parallel with two 16-bit instructions, allowing programmers to use many core resources in one instruction cycle.

Blackfin assembly language uses an algebraic syntax for ease of coding and readability. This architecture has been optimized for use with the VisualDSP C/C++ compiler for fast and efficient software implementation.

memory structure

The ADSP-BF561 uses 32-bit addresses to treat memory as a single unified 4Gbyte address space. All resources, including internal memory, external memory, and I/O control registers, occupy a separate portion of this common address space. The memory portion of this address space is arranged in a hierarchy to provide a good cost/performance balance for some very fast, low-latency memory, such as cache or SRAM very close to the processor, and larger , lower cost and performance memory systems. The ADSP-BF561 memory map is shown in Figure 3.

The L1 memory system in each core is the highest performance memory available to each Blackfin core. Secondary memory provides additional capacity but lower performance. Finally, an off-chip memory system accessed through an external bus interface unit (EBIU) provides SDRAM, flash and SRAM expansion, optionally accessing more than 768M bytes of physical memory. The memory DMA controller provides high bandwidth data movement capabilities. They can perform block transfers of code or data between internal L1/L2 memory and external memory spaces.

Internal (on-chip) memory

The ADSP-BF561 has four on-chip memories that provide high bandwidth access to the core.

The first is the L1 instruction memory of each Blackfin core, consisting of 16K bytes of four-way set-associative cache memory and 16K bytes of SRAM. The cache memory can also be configured as SRAM. This memory is accessed at the maximum speed of the processor. When configured as SRAM, each of the two 16K banks is divided into 4K subgroups that can be accessed independently by the processor and DMA.

The second on-chip memory block is the L1 data memory for each Blackfin core, which consists of four groups of 16K bytes. Two of the L1 data memory banks can be configured as a way of bidirectional set associative cache or SRAM. The other two banks are configured as SRAM. All banks are accessed at full processor speed. When configured as SRAM, each of the four 16K memory banks is divided into 4K subgroups that can be accessed independently by the processor and DMA.

The third memory block associated with each core is the 4Kbyte scratchpad SRAM, which runs at the same speed as the L1 memory, but is only accessible as data SRAM (it cannot be configured as cache memory, nor can it be accessed via DMA) .

The fourth on-chip memory system is the L2 SRAM memory array, which provides 128K bytes of high-speed SRAM, operates at half the core frequency, and has slightly longer latency than the L1 memory bank. Secondary memory is a unified instruction and data memory that can store any mix of code and data required by the system design. The Blackfin cores share a dedicated low-latency 64-bit wide datapath port that connects to the L2 SRAM memory.

Each Blackfin core processor has its own set of core memory mapped registers (MMR), but shares the same system MMR registers and 128K bytes of L2 SRAM memory.

External (off-chip) memory

The ADSP-BF561 external memory is accessed through the External Bus Interface Unit (EBIU). The interface provides a glue-free connection to connect up to four sets of synchronous DRAM (SDRAM) and four sets of asynchronous memory devices, including flash, EPROM, ROM, SRAM, and memory-mapped I/O devices.

The PC133-compatible SDRAM controller can be programmed to interface with up to four SDRAM banks, each containing 16Mbytes to 128Mbytes, and can access up to 512Mbytes of SDRAM. Each bank is independently programmable and adjacent to adjacent banks, regardless of the size of the different banks or their location. This allows flexible configuration and scalability of system memory, while allowing the kernel to treat all SDRAM as a single, contiguous physical address space.

The asynchronous memory controller can also be programmed to control up to four device banks of various devices with very flexible timing parameters. Regardless of the size of the device used, each storage group occupies a 64M-byte segment, so the storage groups are only contiguous when the 64M-byte memory is completely filled.

I/O memory space

Blackfin processors do not define a separate I/O space. All resources are mapped through a flat 32-bit address space. Onchip I/O devices map their control registers to memory mapped registers (mmr) at addresses near the top of the 4Gbyte address space. They are divided into two smaller blocks, one contains the control mmr for all core functions, and the other contains the registers needed for setup and control of the peripherals on the chip outside the core. The core mmr is only accessible by the core, and only in supervisor mode, and is shown as reserved space by on-chip peripherals. In admin mode, the core has access to the system mmr and can be mapped as visible or reserved to other devices, depending on the desired system protection model.

start up

The ADSP-BF561 contains a small boot kernel that configures the appropriate peripherals for booting. If the ADSP-BF561 is configured to boot from the boot ROM memory space, the processor will begin execution from the on-chip boot ROM.

event handling

The event controller on the ADSP-BF561 handles all asynchronous and synchronous events for the processor. The ADSP-BF561 provides event handling that supports nesting and prioritization. Nesting allows multiple event service routines to be active at the same time. Prioritization ensures that the service of high-priority events takes precedence over the service of low-priority events. Controllers support five different types of events:

(1) Emulation - An emulation event causes the processor to enter emulation mode, allowing the processor to be commanded and controlled through the JTAG interface.

(2), reset – this event resets the processor.

(3), Non-Maskable Interrupt (NMI) – NMI events can be generated to the processor by a software watchdog timer or an NMI input signal. NMI events are often used as power outage indicators to initiate an orderly shutdown of the system.

(4) Exception – an event that occurs synchronously with program flow, i.e., an exception will be executed before the instruction is allowed to complete. Conditions such as data alignment violations or undefined instructions cause exceptions.

(5) Interrupt - an event that occurs asynchronously with the program flow. They are caused by timers, peripherals, input pins, and explicit software instructions.

Each event has an associated register to hold the return address and an associated "return from event" instruction. When an event is fired, the state of the processor is saved in the manager stack.

The ADSP-BF561 event controller consists of two stages: the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works in conjunction with the system interrupt controller to prioritize and control all system events.

Conceptually, interrupts from peripherals go into the SIC, which are then routed directly to the CEC's generic interrupts.

Core Event Controller (CEC)

In addition to dedicated interrupts and exception events, CEC supports 9 general purpose interrupts (IVG15–7). Of these general purpose interrupts, it is recommended to reserve two lowest priority interrupts (IVG15-14) for software interrupt handlers and seven priority interrupt inputs to support peripherals of the ADSP-BF561. Table 1 describes the inputs to CEC, identifying their names in the event vector table (EVT) and listing their priorities.

System Interrupt Controller (SIC)

The System Interrupt Controller provides event mapping and routing from many peripheral interrupt sources to the CEC's priority general purpose interrupt inputs. Although the ADSP-BF561 provides a default mapping, the user can do this by writing the appropriate values to the Interrupt Assignment Registers (SIC_IAR7–0). Table 2 describes the input to SIC and the default mapping to CEC.

event control

The ADSP-BF561 provides the user with a very flexible mechanism to control the processing of events. In CEC, three registers are used to coordinate and control events. Each register is 16 bits wide, and each bit represents a specific event class.

• CEC Interrupt Latch Register (ILAT) – The ILAT register indicates when the event is latched. The appropriate bits are set when the processor locks the event and cleared when the event is accepted by the system. This register is automatically updated by the controller, but can also be written to clear (un)lock a lock event. This register can be read in supervisor mode and can only be written in supervisor mode when the corresponding IMASK bit is cleared.

• CEC Interrupt Mask Register (IMASK) – The IMASK register controls the masking and unmasking of individual events. When a bit is set in the IMASK register, the event is unmasked and handled by CEC when asserted. The clear bit in the IMASK register masks the event, preventing the processor from servicing the event

Even events may be locked in the ILAT register. In supervisor mode, this register can be read or written.

Note that general purpose interrupts can be globally enabled and disabled using STI and CLI instructions, respectively.

• CEC Interrupt Pending Register (IPEND) – The IPEND register tracks all nested events. A set bit in the IPEND register indicates that the event is currently active or nested at some level. This register is automatically updated by the controller, but can be read in supervisor mode.

The SIC allows further control of event handling by providing six 32-bit interrupt control and status registers. Each register contains bits corresponding to each peripheral interrupt event shown in Table 2.

• SIC Interrupt Mask Registers (SIC_IMASKx) – These registers control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that peripheral event is unmasked and handled by the system when asserted. A clear bit in these registers masks the peripheral event, preventing the processor from processing the event.

• SIC Interrupt Status Registers (SIC_ISRx) – Since multiple peripherals can be mapped to a single event, these registers allow software to determine the source of the peripheral event that triggered the interrupt. A set bit indicates that the peripheral is asserting an interrupt; a cleared bit indicates that the peripheral is not asserting an event.

• SIC Interrupt Wake-Up Enable Registers (SIC_IWRx) – By enabling the corresponding bits in these registers, each peripheral can be configured to wake up the processor when the processor is in shutdown mode when an event is generated.

Since multiple interrupt sources can be mapped to a common interrupt, multiple pulses of interrupt events that have been detected on this interrupt input can be asserted simultaneously before or during interrupt processing. As an interrupt acknowledgement, the SIC monitors the contents of the IPEND register.

When an interrupt rising edge is detected, the appropriate ILAT register bits are set (detection takes two core clock cycles). This bit is cleared when the corresponding IPEND register bit is set. The IPEND bit indicates that the event has entered the processor pipeline. At this point, the CEC will recognize the next rising edge event and queue it on the corresponding event input. The minimum delay from a rising edge transition of a general purpose interrupt to an asserted IPEND output is three core clock cycles; however, the delay may be much higher, depending on the activity and mode inside the processor.

DMA controller

The ADSP-BF561 has two independent DMA controllers that support automatic data transfer with minimal DSP core overhead. DMA transfers can occur between the ADSP-BF561 internal memory and any DMA-capable peripheral. In addition, DMA transfers can be done between any DMA-capable peripheral device and an external device connected to an external memory interface, including SDRAM controllers and asynchronous memory controllers. Peripherals that support DMA include motion, SPI ports, UART, and PPI. Every DMA-capable peripheral has at least one dedicated DMA channel.

The ADSP-BF561 DMA controller supports one-dimensional (1-D) and two-dimensional (2-D) DMA transfers. DMA transfer initialization can be implemented from registers or parameter sets called descriptor blocks.

The 2D DMA function supports arbitrary row and column sizes (up to 64K elements by 64K elements), arbitrary row and column steps (up to ±32K elements). Furthermore, the column step size can be smaller than the row step size, allowing for interleaved data flow. This feature is especially useful in video applications where data can be deinterleaved on the fly.

Examples of DMA types supported by the ADSP-BF561 DMA controller include:

• A single linear buffer that stops when finished.

• A loop automatically flushes buffers, breaking on every full or partially full buffer.

• 1-D or 2-D DMA using a linked list of descriptors.

• Two-dimensional DMA using an array of descriptors, specifying only the base DMA address in the common page.

In addition to dedicated peripheral DMA channels, each DMA controller also has four memory DMA channels for transfer systems between the various memories of the ADSP-BF561. This enables the transfer of blocks of data between any memory, including external SDRAM, ROM, SRAM and flash memory, with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based method or by an automatic buffering mechanism based on standard registers.

In addition, the ADSP-BF561 has a four-channel internal memory DMA (IMDMA) controller. The IMDMA controller allows data transfers between any of the internal L1 and L2 memories.

watchdog timer

Each ADSP-BF561 core includes a 32-bit timer that can be used to implement a software watchdog function. If the timer expires before being reset by software, a software watchdog can improve system availability by generating a hardware reset, non-maskable interrupt (NMI), or general purpose interrupt to force the processor to a known state. The programmer initializes the count value of the timer, enables the appropriate interrupt, and then enables the timer. After this, software must reload the counter before it counts from the programmed value to zero. This protects the system from an unknown state where the software that normally resets the timer stops functioning due to external noise conditions or software bugs.

After a reset, software can determine if the watchdog is the source of a hardware reset by interrogating the status bit in the timer control register, which is only set when the watchdog generates a reset.

The timer is clocked by the system clock (SCLK) at the maximum frequency F.

timer

There are 14 programmable timer units in ADSP-BF561.

Each of the 12 general-purpose timer units can be independently programmed as a pulse width modulator (PWM), an internally or externally clocked timer, or a pulse width counter. A general purpose timer unit can be used with the UART to measure the width of pulses in a data stream to provide automatic tone detection for serial channels. General purpose timers can generate interrupts to the processor core, providing periodic events for synchronization of processor clock or external signal counts.

In addition to 12 general-purpose programmable timers, another timer is provided for each core. These additional timers are clocked by the internal processor clock (CCLK), which is typically used as the system clock to generate periodic interrupts to the operating system.

Serial port (sport)

The ADSP-BF561 contains two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. Movement supports the following

feature:

•I2S operation is possible.

• Bidirectional Operation – Each sport has two independent sets of transmit and receive pins, supporting eight I2S stereo audio channels.

• Buffered (8-deep) transmit and receive ports - each port has a data register for transferring data words between other DSP components and shift registers for shifting data in and out of the data register.

• Clock - Each transmit and receive port can use an external serial clock or generate its own clock with frequencies ranging from (f/131070) Hz to (f/2) Hz. SCLK Corporation SCLK Corporation

• Word Length – Each motion supports serial data words from 3 bits to 32 bits in length, with the most significant or least significant bit transmitted first.

• Frame - Each transmit and receive port can operate with or without a frame sync signal per data word. The frame sync signal can be generated internally or externally, high or low, with two pulse widths and early or late frame sync.

• Hardware companding - According to ITU recommendation G.711, A-law or μ-law companding can be performed for each movement. Companding can be selected on moving transmit and/or receive channels without additional delay.

• DMA operations with single-cycle overhead – Multiple memory data buffers can be automatically received and transferred per movement. DSPs can chain or chain motion and sequences of DMA transfers between memories.

• Interrupts - Each transmit and receive port generates an interrupt when completing a data word transfer, or when going through a DMA system.

• Multi-Channel Capability – Each sport supports 128 channels in a 1024-channel window and is compatible with H.100, H.110, MVIP-90 and HMVIP standards.

An additional 250 mV of motion input hysteresis can be enabled by setting Bit 15 of the PLL control register. When this bit is set, the hysteresis of all motion input pins is increased.

Serial Peripheral Interface (SPI) port

The ADSP-BF561 processor has an SPI compatible port that enables the processor to communicate with multiple SPI compatible devices.

The SPI interface uses three pins to transfer data: two data pins (Master Out Slave In, MOSI and Master In Slave Out, MISO) and one clock pin (Serial Clock, SCK). The SPI chip select input pins (SPIS) let other SPI devices select the process sor and the seven SPI chip select output pins (SPISEL7–1) let the processor select other SPI devices. The SPI select pins are programmable flag pins for reconfiguration. Using these pins, the SPI port provides a full-duplex, synchronous serial interface that supports master/slave mode and multi-master environments.

The baud rate and clock phase/polarity of the SPI port is programmable, and it has an integrated DMA controller that can be configured to support transmit or receive data streams. The SPI-DMA controller can only service one-way access at any given time.

The SPI port clock rate is calculated as follows:

During a transfer, the SPI port sends and receives data simultaneously by serially shifting data in and out on its two serial data lines. The serial clock line synchronizes data shifting and sampling on the two serial data lines.

UART port

The ADSP-BF561 processor provides a full-duplex Universal Asynchronous Receiver Transmitter (UART) port that is fully compatible with PC standard UARTs. The UART port provides a simplified UART interface for other peripherals or hosts, supports full duplex, supports DMA, and asynchronous serial data transfer. The UART port supports 5 data bits to 8 data bits, 1 stop bit or 2 stop bits, and no parity. The UART port supports two modes of operation:

• PIO (Programmed I/O) - The processor sends or receives data by writing or reading I/O-mapped UART registers. Data is double-buffered both when sent and received.

• DMA (Direct Memory Access) – The DMA controller transfers transmit and receive data. This reduces the number and frequency of interrupts required to transfer data between memories. The UART has two dedicated DMA channels, one for transmit and one for receive. The default priority for these DMA channels is lower than most DMA channels because of their relatively low service rate.

The baud rate, serial data format, error code generation and status, and interrupts for the UART port are all programmable.

UART programmable features include:

• Supports bit rates from (f/1048576) bits/sec to (f/16) bits/sec. SCLK Corporation SCLK Corporation

• Supports data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

The clock rate of the UART port is calculated as follows:

where the 16-bit UART_Divisor comes from the UART_DLH register (most significant 8 bits) and the UART_DLL register (least significant 8 bits).

Combined with the general timer function, it supports automatic audio detection.

The functionality of the UART is further extended with support for the Infrared Data Association (IrDA) Serial Infrared Physical Link Specification (SIR) protocol.

Programmable Flags (PFx)

The ADSP-BF561 has 48 bidirectional, general purpose I/O, programmable flag (PF47–0) pins. The peripheral uses some programmable flag pins (see pin descriptions on page 17). When not used as peripheral pins, each programmable flag can be individually controlled by manipulating the Flag Control, Status and Interrupt registers as follows:

• Flag Direction Control Register - Specifies the direction of each individual PFx pin as an input or output.

• Flag Control and Status Registers - The ADSP-BF561 employs a "write a set" and "write a clear" mechanism, allowing any combination of individual flags to be set or cleared in a single instruction, rather than forcing software to use a read-modify-write process to control the setting of individual flags, without affecting the level of any other flags. Two control registers are provided, one register is written to set the flag value and the other register is written to clear the flag value. Reading the flags status register allows software to interrogate the meaning of the flags.

• Flag Interrupt Mask Registers – These registers allow each individual PFx pin to act as an interrupt to the processor. Similar to the flag control registers used to set and clear a single flag value, one flag interrupt mask register sets bits to enable interrupt functionality and the other flag interrupt mask register clears bits to disable interrupt functionality. PFx pins defined as inputs can be configured to generate hardware interrupts, while PFx pins defined as outputs can be configured to generate software interrupts.

• Flag Interrupt Sensitive Registers - These registers specify whether a single PFx pin is level-sensitive or edge-sensitive, and if edge-sensitive, specifies whether the signal's rising edge or both rising and falling edges are active. One register selects the type of sensitivity, and one register selects which edges are important for edge sensitivity.

Parallel Peripheral Interface

The ADSP-BF561 processor provides two parallel peripheral interfaces (PPI0, PPI1), which can directly connect parallel A/D and D/A converters, video codecs and other general-purpose peripherals. PPI consists of a dedicated input clock pin, up to 3 frame sync pins, and up to 16 data pins. The input clock supports parallel data rates up to f/2MHz, and the sync signal can be configured as input or output. SCLK Corporation

PPI supports several general and ITU-R 656 modes of operation. In general mode, PPI provides half-duplex bidirectional data transfer of up to 16 bits of data. Up to 3 frame sync signals are also provided. In ITU-R 656 mode, PPI provides half-duplex bidirectional transmission of 8-bit or 10-bit video data. In addition, on-chip decoding of embedded Start of Line (SOL) and Start of Field (SOF) preamble packets is supported.

General Mode Description

The general mode of PPI is designed to accommodate a wide variety of data capture and transmission applications. Three different sub-modes are supported:

• Input Mode - Frame sync and data input to PPI.

• Frame Capture Mode – Frame sync is the output of the PPI, but data is the input.

• Output Mode – Frame sync and data are output from the PPI.

input mode

Input mode is used for ADC applications, and video communication with hardware signaling. In its simplest form, PPI_FS1 is an external frame sync input that controls when data is read. PPI_Delay MMR allows a delay (in PPI_CLK cycles) between receiving this frame sync and initiating a data read. The number of input data samples is user programmable and defined by the contents of the PPI count register. PPI supports 8-bit and 10-bit to 16-bit data, programmable in the PPI_Control register.

frame capture mode

Frame capture mode allows the video source to act as a slave (for example, for frame capture). The ADSP-BF561 processor controls when the video source is read. PPI_FS1 is the HSYNC output and PPI_FS2 is the VSYNC output.

output mode

The output mode is used to transmit video or other data, and up to three output frames are synchronized. Typically, single-frame sync is suitable for data converter applications, while two- or three-frame sync can be used to send video via hardware signaling.

ITU-R 656 mode description

PPI's ITU-R 656 mode is designed to accommodate a wide variety of video capture, processing and transmission applications. Three different sub-modes are supported:

• Active video only mode

• Vertical blanking mode only

• Full field mode

Active video only mode

Active video unique mode is only used when the active video part of a field is of interest and not any blanking interval. The PPI does not read any data between the end of active video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking interval. In this mode, control byte sequences are not stored into memory; they are filtered by PPI. After syncing to the beginning of field 1, the PPI will ignore incoming samples until it sees the SAV code. The user specifies the number of active video lines per frame (in the PPI count register).

Vertical Blanking Interval Mode

In this mode, the PPI only transmits vertical blanking interval (VBI) data.

full field mode

In this mode, the entire incoming bitstream is read via PPI. This includes active video, control preamble sequences and auxiliary data that can be embedded in horizontal and vertical blanking intervals. Data transfer starts immediately after synchronization with field 1.

Dynamic Power Management

The ADSP-BF561 offers four power management modes and one power management state, each with a different performance/power profile. In addition, dynamic power management provides control to dynamically change the processor core supply voltage, further reducing power consumption. Controlling the clock for each ADSP-BF561 peripheral also reduces power consumption.

Full working mode maximum performance

In full conduction mode, the PLL is enabled and not bypassed, providing maximum operating frequency capability. This is the default execution state for maximum performance. The processor core and all enabled peripherals run at full speed.

Moderate energy saving in active operation mode

In active mode, the PLL is enabled but bypassed. Since the PLL is bypassed, the processor's core clock (CCLK) and system clock (SCLK) run at the frequency of the input clock (CLKIN). In this mode, the CLKIN to CCLK multiplication ratio can be changed, although these changes are not possible until fully on mode is entered. DMA access is available for appropriately configured L1 and L2 memory.

In active mode, the PLL can be disabled through the PLL Control Register (PLL_CTL). If disabled, the PLL must be re-enabled before transitioning to fully on or sleep mode.

High dynamic energy saving in sleep mode

Sleep mode reduces power consumption by disabling the processor core's clock (CCLK). However, the PLL and system clock (SCLK) continue to operate in this mode. Usually, external events wake up the processor. When in sleep mode, the wake-up assertion will cause the processor to detect the value of the bypass bit in the PLL Control Register (PLL Control Register).

When in sleep mode, system DMA access is only available to external memory, not to L1 or on-chip L2 memory.

Deep-sleep operating mode for maximum dynamic power savings

Deep-sleep mode maximizes power savings by disabling the clock to the processor core (CCLK) and all synchronous peripherals (SCLK). Asynchronous peripherals will not be able to access internal resources or external memory. This power-down mode can only be exited by asserting the reset pin. (reset). If bypass is disabled, the processor will transition to fully on mode. If bypass is enabled, the processor will transition to active mode.

Maximum Static Power Savings in Sleep State

The sleep state maximizes static power savings by disabling the voltage and clock to the processor core (CCLK) and all synchronous peripherals (SCLK). The processor's internal voltage regulator can be turned off by writing b#00 to the frequency bits of the VR#CTL register. This will disable both CCLK and SCLK. Additionally, it sets the internal supply voltage (V) to 0 V to provide the lowest static power consumption. If the processor state is to be preserved, any internally stored critical information (memory contents, register contents, etc.) must be written to a non-volatile storage device before power is removed. Since V is still available in this mode, all external pins are tri-stated unless otherwise specified. This allows other devices that can be connected to the processor to still be powered without drawing unnecessary current. The internal supply regulator can reset the pin by asserting the dot text.

power saving

The ADSP-BF561 supports two different power domains. The use of multiple power domains maximizes flexibility while maintaining compliance with industry standards and conventions. By isolating the internal logic of the ADSP-BF561 into its own power domain, separate from the I/O, the processor can take advantage of dynamic power management without affecting I/O devices. There are no sequencing requirements for different power domains.

The power consumed by the processor is largely a function of the processor clock frequency and the square of the operating voltage. For example, a 25% reduction in clock frequency reduces dynamic power consumption by 25%, while a 25% reduction in voltage reduces dynamic power consumption by more than 40%. Furthermore, these power savings are additive because power savings can be significant if both clock frequency and supply voltage are reduced.

The dynamic power management feature of the ADSP-BF561 allows dynamic control of the processor's input voltage (V) and clock frequency (f).

Power savings can be modeled using power savings factor and power savings percentage calculations.

The power saving factor is calculated as follows:

The variables in the formula are:

fCCLKNOM is the nominal core clock frequency; fCCLKRED is the reduced core clock frequency; VDDINTNOM is the nominal internal supply voltage; VDDINTRED is the reduced internal supply voltage; NOM is the duration of operation at fCCLKNOM; tRED is the duration of operation at fCCLKRED; The percent power savings is calculated as: % power savings = (1 – power savings factor) × 100%.

Voltage regulation

The ADSP-BF561 processor provides an on-chip voltage regulator that can generate the appropriate V voltage level from the V supply. See Operating Conditions on page 20 for model specific regulator tolerances and acceptable V ranges.

Figure 4 shows the typical external components required to complete a power management system. The regulator controls the internal logic voltage levels and is programmable in 50 mV increments through the Voltage Regulator Control Register (VR_CTL). To reduce standby power consumption, an internal voltage regulator can be programmed to cut power to the processor core while maintaining the I/O power (V) supply. In hibernate state, V can still be applied, so no external buffer is needed.

RESET will then initiate the boot sequence by asserting that RESET is activated from the powered down state. Users can also disable and bypass the regulator at their discretion.

Internal voltage regulation is not available on any 600 MHz speed grade models or automotive grade models. External voltage regulation is required to ensure proper operation of these parts at 600 MHz.

Voltage Regulator Layout Guidelines

Regulator external component placement, board routing, and bypass capacitors all have a significant impact on the noise injected into other analog circuits on the chip. During board layout, the VROUT1–0 traces and voltage regulator external components should be considered noise sources and should not be routed or placed near sensitive circuits or components on the board. All internal and I/O supplies should be bypassed with bypass capacitors as close as possible to the ADSP-BF561 processor.

For more details on on-chip voltage regulators and related board design guidelines, see Switching Regulator Design Considerations on the Analog Devices website (ADSP-BF533 Blackfin Processor (EE-228) Application Note - Using "EE- 228" on site search.

clock signal

The ADSP-BF561 processor can be clocked by an external crystal, a sine wave input, or a buffered shaped clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal and must not stop, change or run below the specified frequency during normal operation. This signal is connected to the CLKIN pin of the processor. When using an external clock, the external pins must be left unconnected.

Alternatively, since the ADSP-BF561 processor includes an on-chip oscillator circuit, an external crystal can be used. For fundamental frequency operation, use the circuit shown in Figure 5. A parallel resonant, fundamental frequency, microprocessor grade crystal is connected between the CLKIN and XTAL pins. The on-chip resistance between the CLKIN and XTAL pins is in the range of 500 kΩ. Further paralleling of resistors is generally not recommended. The two capacitors and series resistor shown in Figure 5 trim the phase and amplitude of the sinusoidal frequency. The capacitor and resistor values shown in Figure 5 are typical values only. Capacitance values depend on the crystal manufacturer's load capacitance recommendations and physical PCB layout. The resistor value depends on the drive level specified by the crystal manufacturer. System design should validate custom values based on careful investigation of multiple devices that exceed the allowable temperature range.

The third overtone crystal can be used at frequencies above 25 MHz. Then, as shown in Figure 5, the circuit is modified by adding a tuned inductive circuit to ensure that the crystal operates only at the third overtone.

As shown in Figure 6, the core clock (CCLK) and the system peripheral clock (SCLK) are derived from the input clock (CLKIN) signal. The on-chip PLL can multiply the CLKIN signal by a user-programmable 0.5× to 64× multiplication. The default multiplier is 10x, but it can be modified by a sequence of software instructions. Real-time frequency changes can be achieved by simply writing to the PLL_DIV register.

All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency can be set by bit 0 of the SSEL3–PLL_DIV register. The programmed value defines the division ratio between the PLL output (VCO) and the system clock in the SSEL field. The SCLK divider value is 1 to 15.

System Clock Ratio Example

The maximum frequency of the system clock is F. Note that the divisor ratio must be chosen to limit the system clock frequency to its maximum value F. The SSLE value can be changed dynamically without any PLL lock delay by writing the appropriate value to the PLL divisor register (PLLI DIV).

The core clock (CCLK) frequency can also be dynamically changed through the CSEL1–0 bits of the PLL_DIV register. As shown in Table 6, the supported CCLK divider ratios are 1, 2, 4, and 8. This programmable core clock feature is useful for fast core frequency modifications.

core clock ratio

The maximum PLL clock time that can be changed by programming the PLLYL CTL register is 40 μs. The maximum time to change the internal voltage by the internal voltage regulator is also 40 μs. The reset value of the PLLYROCCNT register is 0x200. This value should be programmed to ensure a wake-up time of 40µs on voltage changes or programming a new MSEL value. This value should be programmed to ensure a wake-up time of 80µs when both voltage and MSEL values are changed at the same time. The time base for the PLL_LOCKCNT register is the CLKIN period.

boot mode

The ADSP-BF561 has three mechanisms (see Table 7) for automatically loading the internal L1 instruction memory, L2, or external memory after reset. The fourth mode is to execute from external memory, bypassing the boot sequence.

The BMODE pin of the reset configuration register sampled during power-on reset and software-initiated reset implements the following modes:

• Execute from 16-bit external memory – Execution starts at address 0x2000 0000, 16-bit packed. The boot ROM is bypassed in this mode. All configuration settings are set for the slowest device possible (3 cycle hold time, 15 cycle R/W access time, 4 cycle settings). Note that in bypass mode, only Core A can execute instructions from external memory.

• Boot from 8-bit/16-bit external flash – The 8-bit/16-bit flash boot routine located in the boot ROM memory space uses asynchronous memory bank 0 setup.

All configuration settings are set for the slowest device (3 cycle hold time; 15 cycle R/W access time; 4 cycle settings).

• Boot from an SPI master device – The Blackfin processor operates in SPI slave mode, configured to receive bytes from the .LDR file from the SPI master (master) agent. In order to prevent the host device from transmitting when the boot ROM is busy, the Blackfin processor asserts a GPIO pin called host wait (HWAIT) to signal the host device that no further transmissions will be sent until the flag is de-asserted byte. The flag is selected by the user, and this information is transmitted to the Blackfin processor via bits 10:5 of the flag header.

• Boot from SPI Serial EEPROM (16-bit, 24-bit addressable) - SPI uses the PF2 output pin to select a single SPIEPROM device, submit a read command at address 0x0000, and begin clocking data to the beginning of the L1 instruction memory. A 16-bit, 24-bit addressable SPI compatible EPROM must be used.

For each boot mode, the bootloader protocol is used to transfer programs and data blocks from an external memory device to its designated memory location. Any boot sequence can load multiple memory blocks. After all the blocks are loaded, the core A program starts executing from the first-level instruction SRAM (0xFFA0 0000). Core B remains heldoff until core a clears bit 5 of SICA_SYSCR. After that, core B will start execution at address 0xFF60 0000.

Additionally, bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. In this case, the processor jumps directly to the beginning of the L1 instruction memory.

Instruction set description

The assembly language instruction set for the Blackfin processor family employs an algebraic syntax designed to simplify coding and readability. Instructions are specifically tuned to provide a flexible, densely coded instruction set that compiles to a very small final memory size. The instruction set also provides full-featured multifunction instructions, allowing programmers to use many processor core resources in a single instruction. Combined with many features often seen on microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture supports user (algorithm/application code) and supervisor (O/S cores, device drivers, debuggers, ISRs) operating modes, allowing multiple levels of access to core processor resources.

Assembly language takes advantage of the unique architecture of the processor and has the following advantages:

• Seamlessly integrated DSP/CPU functions optimized for 8-bit and 16-bit operation.

• Multi-problem load/store modified Harvard architecture that supports two 16-bit MACs or four 8-bit ALUs plus two loads/stores plus two pointer updates per cycle.

• All registers, I/O and memory are mapped into a unified 4Gbyte memory space, providing a simplified programming model.

• Microcontroller functions such as arbitrary bit and bit field manipulation, insertion and extraction; integer operations on 8-bit, 16-bit and 32-bit data types; and independent user and kernel stack pointers.

Code density enhancements, including a mix of 16-bit and 32-bit instructions (no mode switching, no code isolation). Common instructions are encoded in 16 bits.

development tools

ADSP-BF561 supports a complete set of cross-core software and hardware development tools, including analog device simulator and VisualDSP++ development environment. Emulator hardware that supports other emulated device processors also fully emulates the ADSP-BF561.

The VisualDSP++ project management environment allows programmers to develop and debug applications. The environment includes an easy-to-use assembler based on algebraic syntax, archiver (librarian/library generator), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler and C/C++ runtime Time library, which includes DSP and math functions. A key point of these tools is C/C++ code efficiency. Compilers have been developed to efficiently translate C/C++ code to BLASFIN assembly. The processor has architectural features that improve the efficiency of compiling C/C++ code.

The VisualDSP++ debugger has many important features. Data visualization enhances the plotting package, providing a remarkable level of flexibility. This graphical representation of user data enables programmers to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability becomes increasingly important to a designer's development schedule, thereby increasing productivity. Statistical analysis enables programmers to non-invasively poll the processor as it runs the program. This feature unique to VisualDSP++ enables software developers to passively collect important code execution metrics without disrupting the real-time nature of the program. Essentially, developers can quickly and efficiently identify bottlenecks in software. By using the profiler, the programmer can focus on those areas of the program that affect performance and take corrective action.

Using the VisualDSP++ debugger to debug C/C++ and assembler, programmers can:

View mixed C/C++ and assembly code (interleaved source and object information).

• Insert breakpoints.

• Set conditional breakpoints on registers, memory and stack.

• Trace instruction execution.

• Perform linear or statistical analysis of program execution.

• Fill, dump and graphically plot memory contents.

• Perform source-level debugging.

• Create custom debugger windows.

VisualDSP++ IDE allows programmers to define and manage software development. Its dialogs and property pages allow programmers to configure and manage all development tools, including color syntax highlighting in the VisualDSP++ editor. These features allow programmers to:

• Control how the development tool handles input and generates output.

• Maintain one-to-one communication with the tool's command line switches.

The VisualDSP++ kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and time constraints of embedded real-time programming. These capabilities enable engineers to develop code more efficiently, eliminating the need to start from scratch when developing new application code. VDK features include threads, critical and unscheduled areas, semaphores, events, and device flags. The VDK also supports priority-based, pre-emptive, collaborative, and time-phased scheduling methods. Furthermore, the VDK is designed to be extensible. If an application does not use a particular feature, the support code for that feature will be excluded from the target system.

Because the VDK is a library, developers can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used with standard command line tools. When using the VDK, the development environment helps developers perform many error-prone tasks and helps manage system resources, automatically generate various VDK-based objects, and visualize system state when debugging applications that use the VDK.

The Expert Linker can be used to visually manipulate the location of code and data in an embedded system. Memory utilization can be viewed in a color-coded graph. Code and data can be easily moved to different areas of the processor or external memory by dragging the mouse. Runtime stack and heap usage can be checked. The Expert Linker is fully compatible with existing Linker Definition Files (LDFs), allowing developers to move between graphical and textual environments.

The analog device emulator uses the ADSP-BF561's IEEE1149.1 JTAG test access port to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and the processor stack. Non-intrusive in-circuit emulation is ensured by using the processor's JTAG interface. The emulator does not affect the loading or timing of the target system.

In addition to the software and hardware development tools provided by analog devices, third parties also provide a range of tools to support the Blackfin processor family. Third-party software tools include DSP libraries, real-time operating systems, and block diagram design tools.

EZ-KIT Lite Evaluation Board

To evaluate the ADSP-BF561 processor, use the ADSP-BF561 EZ-KIT Lite board available from Analog Devices. Order part number ADDS-BF561-EZLITE. The board features on-chip emulation and is equipped with ® to enable software development. Provides multiple sub-cards.

Design an emulator-compatible processor board

Analog Devices Family Simulators are the tools every system developer needs to test and debug hardware and software systems. The analog device provides an IEEE1149.1 JTAG Test Access Port (TAP) on the ADSP-BF561. The simulator uses the TAP to access the internal features of the processor, allowing developers to load code, set breakpoints, watch variables, watch memory, and inspect registers. The processor must be paused to send data and commands, but once the emulator is done, the processor is set to run at full speed without affecting system timing.

To use these emulators, the target board must contain a header that connects the processor's JTAG port to the emulator.

For detailed information on target board design issues, including mechanical layout, uniprocessor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the Analog Devices JTAG Emulation Technical Reference on the Analog Devices website ( ) (EE-68) - Use the website on "EE-68" to search for regular updates to keep up with improvements in emulator support.

Related documents

The following publications describing the ADSP-BF561 processor (and related processors) can be ordered from any analog sales office or accessed electronically on our website:

• Getting Started with Blackfin Processors

• ADSP-BF561 Blackfin Processor Hardware Reference

• ADSP-BF53x/BF56x Blackfin Processor Programming Reference

• ADSP-BF561 Blackfin Processor Exception List